JPH0277752U - - Google Patents

Info

Publication number
JPH0277752U
JPH0277752U JP15430288U JP15430288U JPH0277752U JP H0277752 U JPH0277752 U JP H0277752U JP 15430288 U JP15430288 U JP 15430288U JP 15430288 U JP15430288 U JP 15430288U JP H0277752 U JPH0277752 U JP H0277752U
Authority
JP
Japan
Prior art keywords
input
bus
output port
port card
system bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15430288U
Other languages
Japanese (ja)
Other versions
JPH0530197Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988154302U priority Critical patent/JPH0530197Y2/ja
Publication of JPH0277752U publication Critical patent/JPH0277752U/ja
Application granted granted Critical
Publication of JPH0530197Y2 publication Critical patent/JPH0530197Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの考案の一実施例を示す機能ブロツ
ク図、第２図は従来の技術を説明するための機能
ブロツク図である。 １……マイクロコンピユータカード、２……シ
ステムバス、３……入出力ポートカード、１７…
…ＯＲゲート、１９……デコーダ回路、２０……
タイムアウト監視回路、２１……ＦＩＦＯメモリ
、２２……バス回路、２３……監視モード選択ス
イツチ。 FIG. 1 is a functional block diagram showing one embodiment of this invention, and FIG. 2 is a functional block diagram for explaining the conventional technology. 1... Microcomputer card, 2... System bus, 3... Input/output port card, 17...
...OR gate, 19...decoder circuit, 20...
Timeout monitoring circuit, 21...FIFO memory, 22...bus circuit, 23...monitoring mode selection switch.

Claims (1)

【実用新案登録請求の範囲】 (1) システムバスに複数の入出力ポートカード
を接続するときに中継するバスバツフア回路であ
つて、システムバスより入出力ポートカードをア
クセスしたときに予め設定されたクロツク数間に
、入出力ポートカードからアクノレツジ信号が返
つてこないと前記入出力ポートカードの代りにア
クノリツジ信号を前記システムバスを介してマイ
クロコンピユータに返すタイムアウト監視回路と
、その入出力ポートカードアドレスを記憶し、入
出力ポートカードアクセス後に前記マイクロコン
ピータにより読み出されるＦＩＦＯメモリを有す
ることを特徴とするバス中継式バスバツフア回路
。 (2) モードスイツチの設定によりシステムバス
上のアドレス信号またはデータ信号を入出力リー
ドパルスまたは入出力ライトパルスでラツチしモ
ニタするバス監視部を有する請求項第１項記載の
バス中継式バスバツフア回路。[Claims for Utility Model Registration] (1) A bus buffer circuit that relays when multiple input/output port cards are connected to a system bus, and which provides a clock that is set in advance when an input/output port card is accessed from the system bus. A timeout monitoring circuit that returns an acknowledge signal to the microcomputer via the system bus in place of the input/output port card if an acknowledge signal is not returned from the input/output port card within a few seconds, and stores the input/output port card address. A bus relay type bus buffer circuit comprising a FIFO memory which is read out by the microcomputer after input/output port card access. 2. The bus relay type bus buffer circuit according to claim 1, further comprising a bus monitoring section that latches and monitors an address signal or a data signal on the system bus with an input/output read pulse or an input/output write pulse according to the setting of a mode switch.
JP1988154302U 1988-11-29 1988-11-29 Expired - Lifetime JPH0530197Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988154302U JPH0530197Y2 (en) 1988-11-29 1988-11-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988154302U JPH0530197Y2 (en) 1988-11-29 1988-11-29

Publications (2)

Publication Number Publication Date
JPH0277752U true JPH0277752U (en) 1990-06-14
JPH0530197Y2 JPH0530197Y2 (en) 1993-08-02

Family

ID=31430911

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988154302U Expired - Lifetime JPH0530197Y2 (en) 1988-11-29 1988-11-29

Country Status (1)

Country Link
JP (1) JPH0530197Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11306109A (en) * 1998-04-16 1999-11-05 Fuji Electric Co Ltd Bus monitor display unit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5384638A (en) * 1976-12-30 1978-07-26 Fujitsu Ltd Trouble supervisory system
JPS5543682A (en) * 1978-09-22 1980-03-27 Hitachi Ltd Input/output unit control system
JPS57106035U (en) * 1980-12-19 1982-06-30

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5384638A (en) * 1976-12-30 1978-07-26 Fujitsu Ltd Trouble supervisory system
JPS5543682A (en) * 1978-09-22 1980-03-27 Hitachi Ltd Input/output unit control system
JPS57106035U (en) * 1980-12-19 1982-06-30

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11306109A (en) * 1998-04-16 1999-11-05 Fuji Electric Co Ltd Bus monitor display unit

Also Published As

Publication number Publication date
JPH0530197Y2 (en) 1993-08-02

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