JPS62146253U

JPS62146253U -

Info

Publication number: JPS62146253U
Application number: JP3072586U
Authority: JP
Priority date: 1986-03-04
Filing date: 1986-03-04
Publication date: 1987-09-16

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例を示すブロツク図、
第２図は実施例の動作説明するためのタイムチヤ
ート、第３図は従来のプロセツサシステムの構成
を示す図である。１……ホストプロセツサ、２……システムバス
、３……システムバスインタフエース、４……ロ
ーカルバス、５……２ポートメモリ、６……ロー
カルプロセツサ、７……コントローラモジユール
、８……ステータスレジスタ、９……バス開閉回
路。 FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a time chart for explaining the operation of the embodiment, and FIG. 3 is a diagram showing the configuration of a conventional processor system. 1...Host processor, 2...System bus, 3...System bus interface, 4...Local bus, 5...2 port memory, 6...Local processor, 7...Controller module, 8... ...Status register, 9...Bus opening/closing circuit.

Claims

[Scope of utility model registration claim] 2-port memory connected to a local bus,
a local processor that executes data processing based on the commands stored in the two-port memory and writes the execution results to the two-port memory;
writing commands and data to be executed by the local processor to the two-port memory via the system bus and the local bus;
In a processor system comprising a host processor that receives an execution end signal from a local processor and reads an execution result stored in the two-port memory, a two-port processor is provided at a connection between the system bus and the local bus. A bus opening/closing circuit for prohibiting or permitting access to the memory and local processor is provided, and a status register is provided for outputting status information indicating the opening/closing status of this bus opening/closing circuit to the system bus side. The host program is configured to control the bus opening/closing circuit to an open state and to store status information indicating that the bus opening/closing circuit is in the open state in the status register from the start to the end of execution. A processor system characterized in that a processor is configured to be able to access a two-port memory and a local processor only when the bus opening/closing circuit is in a closed state by referring to status information in the status register.