JPS59174644U - Debugging device - Google Patents
Debugging deviceInfo
- Publication number
- JPS59174644U JPS59174644U JP6508183U JP6508183U JPS59174644U JP S59174644 U JPS59174644 U JP S59174644U JP 6508183 U JP6508183 U JP 6508183U JP 6508183 U JP6508183 U JP 6508183U JP S59174644 U JPS59174644 U JP S59174644U
- Authority
- JP
- Japan
- Prior art keywords
- address
- data
- processor
- program
- debugging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Debugging And Monitoring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の１実施例に係るデバッグ装置の概略の
構成を示すブロック図、第２図は第１図のデバッグ装置
の動作説明のためのフローチャートである。
１・・・デバッグ装置、２・・・プロセッサ、５・・・
ビットマツプメモリ、２０・・・実機、２１・・・プロ
セッサ、２２・・・プログラムメモリ、２３・・・コン
＋ロールバス、２４・・・アドレスバス、２５・・・デ
ータバス。FIG. 1 is a block diagram showing a general configuration of a debugging device according to an embodiment of the present invention, and FIG. 2 is a flowchart for explaining the operation of the debugging device shown in FIG. 1. 1...Debug device, 2...Processor, 5...
Bitmap memory, 20... Actual machine, 21... Processor, 22... Program memory, 23... Control + roll bus, 24... Address bus, 25... Data bus.
Claims (1)
プログラムメモリとを具備する実機の、システムバスも
しくは該プロセッサのリード端子からアドレス信号、デ
ータ信号およびコントロー−生信号を取出してプログラ
ムデバッグを行なうデバッグ装置であって、該デバッグ
装置は、該実機におけるアドレスおよびデータ空間に対
応したビット数を有するビットマツプメモリを具備し、
該実機のアドレスバスおよびデータバスに送出されるア
ドレスおよびデータ値をアドレス信号として該ビットマ
ツプメモリをアクセスし、アクセスしたビットに所定値
のデ゛−夕を書込むことにより該実機のプロセッサのプ
ログラム実行状態を記憶することを特徴とするデバッグ
装置。A debugging device that performs program debugging by extracting address signals, data signals, and controller raw signals from the system bus or lead terminals of the processor of an actual machine, which is equipped with a processor and a program memory that stores a control program for the processor. The debug device includes a bitmap memory having a number of bits corresponding to the address and data space of the actual device,
The program of the processor of the actual device is accessed by using the address and data value sent to the address bus and data bus of the actual device as an address signal, and a predetermined value of data is written to the accessed bit. A debugging device characterized by storing an execution state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6508183U JPS59174644U (en) | 1983-05-02 | 1983-05-02 | Debugging device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6508183U JPS59174644U (en) | 1983-05-02 | 1983-05-02 | Debugging device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59174644U true JPS59174644U (en) | 1984-11-21 |
Family
ID=30195275
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6508183U Pending JPS59174644U (en) | 1983-05-02 | 1983-05-02 | Debugging device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59174644U (en) |
-
1983
- 1983-05-02 JP JP6508183U patent/JPS59174644U/en active Pending
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