JPS61190636A - Information processor with trace function - Google Patents

Abstract

PURPOSE:To trace easily an interface signal by storing simultaneously the interface signal in an external system and a micro instruction address by hardware. CONSTITUTION:In case that the log of the interface signal is stored, a tracer write control signal 101 is set to the high level by the execution of a microinstruction to write it on tracers 16 and 17. The value of a storage register 11 is written on the tracer 16, and the interface signal is written on the tracer 17. These stored interface signal and value of the storage register 11 are transmitted to a data bus 103 and are read out thereby. When tracers are stopped, the last read value is the latest data because an address counter 15 indicates an address following the last write address.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an information processing device having a tracing function.
In particular, the present invention relates to an information processing device having an interface signal tracing function.

(Prior Art) In an information processing device, by tracing the history of changes in interface signals with external systems, important information is obtained for debugging the information processing device, analyzing failures in the information processing system, and the like.

Conventionally, when tracing the history of changes in such ink process signals, a microinstruction reads the interface signal under predetermined conditions, and then stores the value in a storage circuit such as a memory, or A method of directly measuring the 7-process signal using a measuring device such as a logic tracer has been used.

However, in the former case, it takes a lot of time to read the interface signals and store them in memory etc., and normal microinstruction processing stops during that time. It also has the disadvantage that it is difficult to grasp the time relationship with the microinstructions that operate it.

The latter case has the disadvantage that an expensive measuring device must be prepared and furthermore, it must be set up, which takes time and effort.

(Object of the Invention) The object of the present invention is to eliminate the drawbacks of conventional information processing devices and to improve the state of interface signals with external systems.
t-Hardware Information that has a trace function that allows easy tracing of interface signals with external systems by storing and storing in memory etc. at each time interval and simultaneously storing and storing the address of the microinstruction being executed. Our goal is to provide control equipment.

(Structure of the Invention) According to the present invention, in an information processing device that has an internal processor, is controlled by microinstructions, and is connected to an external system such as a processor, an interface signal with the external system is provided. a storage section for storing the address of the microinstruction, a means for simultaneously loading the ink 7 process signal and the microinstruction into the storage section, and a means for reading out the stored contents. IP! ! An enemy information processing device is obtained.

(Example) Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an information processing system including an embodiment of the invention, and FIG. 2 shows an embodiment of the invention.

1 and 2, the present embodiment is an information processing device 10 that is connected to an external system 200 such as a processor, has an internal processor, is controlled by microinstructions, and has an interface signal with the external system 200. a storage section 17 for storing microinstruction addresses at certain time intervals, a storage section 16 for storing microinstruction addresses, an address counter 15 of the storage section, a writing means for writing to the storage section 16. and reading means for reading the contents.

This embodiment includes a microinstruction address storage register (hereinafter abbreviated as MAR) 11, a microinstruction storage memory (hereinafter abbreviated as C8) 12. It has an executing microinstruction storage register (hereinafter abbreviated as MIR) 13, a decoder 14 for decoding the executing microinstruction, a memory section 16, 17, and AND circuits 8 and 9 for controlling an address counter 15, etc. .

The address counter 15 is connected to storage units 16 and 17 that store interface signals and microinstructions, and each storage unit is composed of a tracer (B) that stores microinstruction addresses and a tracer (B) that stores interface signals. ing.

The AND circuit 18 is the microinstruction switching clock lOO
The AND circuit 19 is connected to supply the signal 101 that controls writing to the tracers (4) and (B)', and the AND circuit 19 is connected to the address when reading the count-clock 102 to the tracers (4) and (B)'. - Connected to counter 15. The storage units 16 and 17 consisting of tracers (A) and (B) are connected to the data bus 103 at the time of reading, and the tracer (B) is connected to the interface signal 20.
0-1 to 200-Nt'' through interface signal drivers/receivers 110-1 to 1lo-N.

Next, the operation of this embodiment will be explained.1 In this embodiment, the contents of the microinstruction storage memory 12 corresponding to the value of the microinstruction address storage register 11 appear at the output, and the output value is the leading edge of the microinstruction switching clock 100. The microinstruction storage register 13 receives the instruction. Contents IIi of microinstruction storage register 13, decoder 14
is coded and the command is executed. Furthermore, the contents of the microinstruction address storage register 11 are updated according to the execution content, and accordingly, the contents of the microinstruction storage memory 11 are updated.
The output value of 2 is also updated. The updated contents are loaded into the microinstruction storage register 13 at the leading edge of the next microinstruction switching clock 100, and the next microinstruction is executed.

By repeating the above operations, microinstructions are executed one after another.

Interface (If you want to remember the history of issue 1.

For example, by executing a microinstruction, it is possible to set the tracer write control signal 101 to high level and cause the retracers 0J16 and (B) 17 to write. In this case, the contents of the microinstruction storage register 13 are updated when the microinstruction switching clock 100 falls at 9. Furthermore, the microinstruction switching clock 10
If the tracer write control signal 101 is at a high level when 0 rises to a high level, the output of the AND circuit 19 becomes a low level, and tracers (1) and (B) receive honor. A signal is generated and the tracer (A
) is written with the value of the storage register 11, and tracer (B) with the interface signal. Next, when the microinstruction switching clock 100 falls again,
The output signal of the AND circuit 19 changes from Low level to High level.
Raise to level 9 and finish filling tracers (A) and (B). Furthermore, as the output signal of the AND circuit 19 rises, the output of the AND circuit 18 also goes LOW.
9. Rise from level to High level. Address counter 15 is incremented by 1 and indicates the next address. or.

When the micro-instruction switching clock 100 falls again, the next micro-instruction is stored in the storage register 13, and the above operation is traced one after another by returning <9. If you want to stop the tracer,
For example, the tracer write control signal 101 may be set to the L6w level by executing a microinstruction.

The value of the stored interface signal storage register 11 is read by sending it to the data bus 103. Simultaneous K, count clock 102 when reading is 1
When the clock is output, the address counter 5 is incremented by one.

When the tracer is stopped, address counter 5 points to the address next to the last written address, so
If only the capacity of the storage section is read, the first value read out is the oldest value, and the last value read out is the newest data.

(Effects of the Invention) As explained above, the present invention is configured such that the interface signal with the external system and the microinstruction address are simultaneously stored in hardware, thereby making it easier to analyze, data can be easily collected, etc. effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an information processing system including an information processing apparatus of the invention, and FIG. 2 is a diagram showing an embodiment of the invention. 10... Information processing device, 11... Old microinstruction storage register, 12... Microinstruction storage memory. 13...Executing microinstruction storage register, 1
4...Executing microinstruction decoder, 15...
...Tracer address counter, 16...
... A tracer (A) that stores the microinstruction address,
17... Tracer (B) for storing interface signals, 18° 19... AND circuit, 100
・・・・・・Micro instruction switching clock, 101・
...Write control signal to tracers (A) and (B), 102...°°° Address counter count clock when reading tracers (A) and (B), 10
3. Old... Data bus when reading tracers (A) and (B), 200... External system. 110-1 to 110-N... Interface signal driver/receiver, 200-1 to 200-N...
...−interface signal.

Claims (1)

[Claims] In an information processing device that has an internal processor, is controlled by microinstructions, and is connected to an external system such as a processor, a storage unit that stores an interface signal with the external system, and an address of the microinstruction. 1. An information processing apparatus comprising: a storage section for storing the interface signal and the microinstruction; means for simultaneously writing the interface signal and the microinstruction into the storage section; and means for reading out the stored contents.