JPS59158450A - Program test device - Google Patents

Abstract

PURPOSE:To collect especially a C0 index among test coverage indexes by such as designating the address for the instruction of a program with an address signal outputted from a CPU when executing a test program by the CPU. CONSTITUTION:A program to be tested is stored in an ROM2. A CPU1 reads sequentially an instruction stored in the ROM2 with address designation. This data is given to a memory 23 and logical 1 value is written in a corresponding byte. When an instruction in the program of the ROM2 is executed in this way, the information representing which instruction of the program is executed, i.e., the C0 index is stored in the memory 23 by writing ''1'' to the corresponding byte in the memory 23. When the collection of data, i.e., the execution of test case is all finished, the data (C0 index) stored in the memory 23 is read and collected and displayed via a CPU22.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a program testing device, and more particularly to a device for checking the integrity of, for example, testing (or debugging) a program.

Description of Prior Art Generally, when testing a program after it has been created, the program to be tested is executed using various test cases to check its operation. At this time, it is very important to clarify the parts of the program that were actually executed and the parts that were not executed in order to check the completeness of the test. Therefore, the test coverage metric (test cov
test (
or debugging) is proposed. However, until now there has been no equipment capable of collecting such test coverage indicators. In particular, test the program to be tested by running it in real time on an actual machine]
...There was no equipment that could collect coverage indicators.

OBJECTS OF THE INVENTION Therefore, it is an object of the present invention to provide a program testing device that can collect the Co index (Have all statements in the program been executed?) among the test coverage indexes.

Structure and Effects of the Invention In summary, when a program to be tested is executed by a central processing unit, each instruction of the program is addressed by an address signal output from the central processing unit, and each instruction is A corresponding storage area of a storage means having a storage area of at least 1 bit, each storage area consisting of at least one bit, is addressed, and predetermined information (corresponding instruction is executed) is stored in the addressed storage area. The system is designed to write information (information indicating what happened).

According to this invention, Co metrics can be collected and the integrity of testing (or debugging) can be easily checked. Furthermore, in the present invention, CO indicators can be collected using an actual device. Furthermore, the Co index can be collected in real time while the central processing unit is executing the program to be tested.

Description of examples FIG. 1 is a block diagram showing one embodiment of the present invention.

In the configuration, the ROM 2 stores a program to be tested. This ROM2 has address bus AB
It is connected to CPU1 via 1. CPU1 is ROM2
The instructions in the program are sequentially read out and executed. Address bus AB1 is also provided to multiplexer 21. A CPU 22 is further connected to this multiplexer 21 via an address bus AB2.

That is, multiplexer 21 switches between the address output to address bus AB1 and the address output to address bus AB2. The output of multiplexer 21 is given to memory 23. This memory 23 includes a plurality of bytes (for example, 64 bytes) each consisting of one bit. Each pie 1 to 1 in the memory 23 corresponds to each byte included in the ROM 2, and a corresponding address is assigned. Therefore, from CPU1 to address bus A
When address data is output to B1, the instruction stored in the corresponding byte is addressed in the ROM 2, and the byte corresponding to the instruction is addressed in the memory 23. Write enable of memory 23 (W> terminal is O
The output of the control circuit 25 is applied via the R gate 24. This control circuit 25 receives a run signal @ (a signal indicating that the program is being executed) output from the CPU 1 and an access enable signal @ (a signal indicating that the CPU 1 is running the ROM 2).
This includes an AND gate that performs a logical product with a signal representing the timing of accessing the data. Further, a clear write command signal output from the CPU 22 is applied to the data input terminal (IN) of the memory 23 . This clear write command signal is also applied to the above-mentioned write enable terminal via the OR gate 24. The output terminal (OUT) of the memory 23 is CP1. J22 is connected to data bus DB2.

5- FIG. 2 is a flowchart for explaining the operation of the CPU 22 shown in FIG. 1. The operation of the embodiment shown in FIG. 1 will be explained below with reference to FIG.

First, in step (abbreviated as S in the figure) 1, the memory 23 is cleared. Then, in step 2, C
o An instruction to collect indicators is given.

Subsequently, in step 3, the CPU is caused to start executing the program to be tested stored in the ROM2. Therefore, the CPUI sequentially outputs address data to the address bus ABI, and sequentially addresses and reads instructions included in the program stored in the ROM2.

Next, in step 4, the address data output from the CPU 1 is sent to the memory 23 via the multiplexer 21.
and logical 1-1 in the corresponding byte of memory 23.
is written. To explain the operation at this time in more detail, in synchronization with the output of address data from CPU1,
The control circuit 25 outputs a high level signal.

This high-6=level signal is applied to the write enable terminal (W>) of the memory 23 via the OR gate 24, making the memory 23 ready for writing.At this time, the input terminal (IN) of the memory 23 is It is low level.Here, memory 2
3, when the input terminal (IN) is at low level, logic "1" is written to the addressed byte, and conversely, when the input terminal 'j' (IN) is at high level, the addressed byte is written. A logical rOJ is configured to be written to the byte. In the above case, since the input terminal (IN) is at a low level, the corresponding byte of the memory 23 specified by the address data from the CPLll has a logic "
1" is written. In this way, when an instruction in the program of the ROM 2 is executed, a logic "1" is written to the corresponding byte of the memory 23. Also, bytes (in memory 23) corresponding to unexecuted instructions are logic "0"
It remains as it is. Therefore, the memory 23 stores information indicating which instruction in the program has been executed, that is, the Co index.

Next, the process proceeds to step 5, where the operation of the CPU 1 is stopped. Subsequently, in step 6, it is determined whether data collection has been completed, that is, whether all test cases have been executed. If the data collection is not completed, that is, if there are still unexecuted cases, the operations from step 3 onwards are repeated again. When data collection is completed, that is, when all test cases have been executed, the process proceeds to step 7, and the data (Co index) stored in the memory 23 is read out. At this time,
Multiplexer 21 is switched to the address bus AS2 side. Therefore, the memory 23 is addressed based on the address data output from the CPU 22. 1-bit data output from the output terminal (OUT) of the memory 23 is read into the CPU 22 via the data bus DB2.

Next, the process proceeds to step 8, where the CPU 22 aggregates the data read from the memory 23, that is, the Co index, and outputs the data to a display device (not shown) for display.

Note that the totalized Co index may be printed as shown in FIG.

Note that when clearing the data stored in the memory 23, a high-level clear write command signal is output from the CPU 22. This clear write command signal causes the write enable terminal (W> of the memory 23 to go high, and the input terminal (IN) to go high.Furthermore,
CPU22 outputs address data to address bus AB2.

Each byte of memory 23 is sequentially addressed by this address data. At this time, since the input terminal (IN) of the memory 23 is at a high level, the memory 23
The byte addressed in 3 has a logic '0'
is written.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a flowchart for explaining the operation of the CPU 22 shown in FIG. FIG. 3 is a diagram showing an example of printing of the Co index. In the figure, 1 is a CPU that executes a program to be tested, 2 is a ROM 121 that stores a program to be tested, is a multiplexer, 22 is a CPU 123 that performs a Co index collection operation, is a memory that stores a Co index, 25 shows the control circuit. Patent applicant Tateishi Electric Co., Ltd. 10-

Claims (1)

[Scope of Claims] A program storage means for storing a program to be tested, a central processing unit for sequentially reading and executing each instruction included in the program to be tested, and a storage area corresponding to each of the instructions, each of which includes: A storage means having a storage area of at least one bit, and addressing a corresponding storage area of the storage means based on an address signal output from the central processing unit for addressing each of the instructions. and means for writing information indicating that the corresponding instruction has been executed into a storage area of the storage means addressed by the addressing means.