JPH04359326A - History information recording system - Google Patents

Abstract

PURPOSE:To preserve history information of a recent past as well as that of a remote past by changing bit positions of a RAM at each time of recording. CONSTITUTION:A storage part 1 is a RAM having the 1k-byte capacity and is constituted as (4 bytes)X(256 entries). An address signal AD from a counter 12 and a write signal WE from a write control circuit 13 are supplied to the storage part 1. A transposing circuit 10 transposes 3-byte recording information inputted from a bus 11 to 4-byte information and outputs this data to a bus 2. The counter 12 has 10-bit word length, and lower 8 bits are used as the address signal AD to the storage part 1, and upper 2 bits are used as a control signal AGN to the transposing circuit 10 and are outputted to the write control circuit 13. This circuit 13 sets the write signal WE to '1' to perform the write operation in the storage part 1 when a recording timing signal RT is '1' and the signal AGN satisfies a prescribed condition.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a history information recording method for recording the operating state of a data processing device as a history, and analyzing it when a failure occurs to determine the cause.

0002

2. Description of the Related Art Recently, computer systems have become larger and more complex, and demands for system reliability have also tended to increase. In order to meet demands for system reliability, improving the efficiency of preventive maintenance including debugging and quickly identifying the cause of a failure have become major issues. As one means to meet the above request, a history information recording system has been put into practical use that records the operating state of a data processing device as a history and uses this history for debugging or investigating the cause of a failure. FIG. 3 shows the configuration of a conventional history information recording system. In FIG. 3, the storage unit 1 has, for example, 1K
It is a RAM with a capacity of bytes. The storage unit 1 is configured to store 256 history information entries with a word length of 4 bytes. History information includes processor programs and
A counter, data on a data bus, some bits representing the internal state of the processor, etc.

[0003] History information is input from bus 2. When the recording timing signal RT supplied from the terminal 8 is "1", the write signal WE becomes "1", and the history information input is written into the storage section 1. Counter 4 has a length of 8 bits and counts from 0 to 255. Counter 4 is OR
When the CE signal from the circuit 5 is "1", it becomes operational, and the count value that increases by 1 is stored at the address (
AD). The OR circuit 5 receives the recording timing signal RT and the read signal READ from the input terminals 8 and 9, respectively, performs a logical sum of these input signals, and generates a CE signal. That is, OR circuit 5
operates the counter 4 when the read signal or write signal is "1".

[0004] When recording historical information, the historical information is supplied to the storage unit 1 via the bus 2 and at the same time, the RT
Set the signal to “1”. The RT signal becomes the RAM write signal WE and at the same time becomes the CE signal that operates the counter 4. In one recording, 0 to 255 entries of history information are stored. When each recording is completed, the contents of the counter 4 change from a state of all "1"s, that is, 255, to a state of all "0s", that is, 0, by incrementing. Therefore, the new history information is overwritten at the same address as the history information 256 entries ago. In this way, the history information for the latest 256 entries is always left in the storage unit 1. If a fault is detected,
The RT signal input from the input terminal 8 is suppressed, and thereby,
Prevent history information from being updated thereafter. FIG. 4 shows the storage status of history information in the storage unit 1. As shown in the figure, the history information is numbered in ascending order from the oldest to the oldest. When reading history information, the READ signal is set to 256.
Set to “1” during the cycle. As a result, the history information is read out in order from the oldest to the oldest.

[0005]

[Problems to be Solved by the Invention] As mentioned above, history information is stored in the RAM constituting the storage unit 1;
The capacity of M is limited, and therefore the total amount of history information that can be stored is also limited. The capacity of recordable history information is word length x number of entries. Therefore, there is a trade-off between the word length and the number of entries in the recorded history information, and these must be carefully determined. When looking at historical information from the perspective of investigating the cause of a failure, there are various cases in which the cause of the failure is immediately before the failure was detected, and cases in which it is in the relatively distant past.

In the former case, even if the number of entries is small,
The larger the amount of information in one entry, the better; in the latter case,
If the number of entries is not large, it is not possible to investigate the cause of the failure. Conventionally, in order to be applicable to both of the above cases, a method has been considered in which the word length and number of entries of history information are made variable and these are switched. For example, a 1K byte RAM may be used by switching between 4 bytes x 256 entries and 1 byte x 1K entries. However, the method of switching settings as described above has a problem in that it is necessary to predict failures that will appear in advance and make settings. Also,
In a setting where the number of entries is large, only the minimum amount of information can be obtained regarding the state immediately before a failure, which makes failure analysis difficult.

The present invention was made in view of the problems in the prior art described above, and uses a RAM with a minimum storage capacity to store detailed historical information for a short period of time and minimum information for a long period of time. The purpose of the present invention is to provide a history information recording method that can simultaneously store both types of information.

[0008]

[Means for Solving the Problems] A history information recording method according to the present invention includes: a storage section for recording operation history information of a data processing device; a means for specifying a location in the storage section where the next history information is to be stored; In the data processing apparatus, the storage section is configured to record new history information in the area where the oldest history information was recorded until there is no free space in the storage section. Each time, before writing the history information to be recorded into the storage unit, the bit position where past history information is stored is different from the bit position where new history information is written. It is configured to include means for sorting.

[0009]

[Operation] With the above configuration, each of the N bits constituting one word of input history information is associated with the M bit positions of an entry of M bits (M>N) constituting one word of the storage part, stored in the corresponding bit position. The correspondence between the N bits of input history information and the M bit positions of the entries in the storage section is such that important parts of the previously recorded history information are not erased by the current recording. , controlled to be saved. As described above, for important items, it is possible to save as much old historical information as possible and at the same time record all new information.

0010

[Examples] Examples of the present invention will be described in detail below. FIG. 1 shows the configuration of a history information recording system according to the present invention. In FIG. 1, a storage unit 1 is a RAM having a capacity of 1 Kbyte, and is configured as 4 bytes×256 entries. When storage unit 1 is divided into four blocks of 1 byte x 256 entries, these blocks are called banks,
The four banks are named banks 0, 1, 2 and 3. The input of the storage unit 1 is connected to a 4-byte bus 2. Each byte of bus 2 is connected to each bank of storage unit 1. The storage unit 1 receives an address signal AD from the counter 12.
However, a write signal WE is supplied from the write control circuit 13, respectively.

The sorting circuit 10 inputs 3 bytes of history information to be recorded from the bus 11, as described below.
Sort into 4 bytes and send to bus 2. The operation of the reordering circuit 10 is controlled by the AGN signal sent from the counter 12. The counter 12 has a word length of 10 bits, and the lower 8 bits are the address signal A of the storage section 1.
D, and the upper two bits become the control signal AGN of the rearrangement circuit 10 and are output to the write control circuit 13. The write control circuit 13 receives a recording timing signal R.
When T is “1” and the AGN signal from the counter 12 satisfies predetermined conditions, the write signal WE is set to “1”.
and causes the storage unit 1 to perform a write operation.

The operation of the circuit shown in FIG. 1 will be explained below. The history information input to the bus 11 consists of 3 bytes,
Byte 0 contains highly important information, here the value of the processor's program counter, and bytes 1 and 2 contain relatively less important information, here the value on the data bus.

[Table 1] Table 1 shows the sorting circuit 10 and write control circuit 13.
Indicates the rules governing the behavior of For the 3-byte history information input (bytes 0, 1, 2), the combination of banks to be written differs depending on the contents of the upper 2 bits (AGN signal) of the counter 12. For example, byte 0 of history information input,
1 and 2 are banks 0 and 2 when the AGN signal is “00”.
When the AGN signal is "01", the signals are stored in banks 1, 2, and 3, respectively.

The write control circuit 13 controls writing for each bank using the AGN signal, and writes to banks that do not correspond to any byte of history information (the negative part in Table 1).
, the WE signal is not output even if the recording timing signal RT is "1". In other words, the next count (2 counts) of the AGN signal is stored in the bank where byte 0 is written.
56 clock), the control is such that nothing is written.

FIG. 2 shows the storage unit 1 controlled as described above.
An example of recorded contents at a certain point in time is shown. In FIG. 2, the value of the upper two bits of the counter 12 is "10". 256 entries are saved for bytes 0 to 2 of the history information, and an additional 256 entries are saved for byte 0, which is highly important. Since the value of the program counter of the processor is recorded in byte 0, it is possible to trace the execution of programs in the processor from the past for 512 entries. As described above, reading of the history information recorded in the storage unit 1 is realized by setting the READ signal to "1" for 256 cycles. At this time, the upper two bits of the counter 12 are also output, and are used to distinguish between a bank in which bytes 0 to 2 are written at the same time and a bank in which only byte 0 of 256 entries in the past is stored.

[0015] The above output information can be displayed as is or after being edited by hardware or software. In order to ensure continuity of recording before and after reading history information, it is necessary to take measures such as decrementing the upper two bits of the counter 12 before or after reading, but this can be done using a simple circuit. It is possible to add. In the above embodiment, the storage unit 1, the sorting circuit 10, and the counter 12 are each shown as dedicated hardware. However, it is clear that a similar method can be implemented using general-purpose circuitry and software control within the data processing device.

[0016]

[Effects of the Invention] As explained above, according to the present invention,
Regarding historical information, it is possible to store a wide range of information in a short period of time and to store a minimum amount of information in a long period of time. This significantly improves the ability of the history information recording system to use history information to investigate the cause of a failure in a data processing device.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of the present invention.

FIG. 2 is a memory map for explaining the operation of the circuit in FIG. 1;

FIG. 3 is a diagram showing a conventional technique.

FIG. 4 is a memory map for explaining the operation of the circuit in FIG. 3;

[Explanation of symbols]

1 Storage units 2, 3, 11 Buses 4, 12 Counter 5 OR circuit 6 Control line 7 Address line 8, 9 Input terminal 10 Sorting circuit 13 Write control circuit AD
Address signal AGN Sorting control signal CE Counter operation signal RT
Recording timing signal READ Read signal WE Write signal

Claims (1)

[Claims] 1. A storage section for recording operation history information of a data processing device; means for specifying a location in the storage section where the next history information is to be stored; In the data processing apparatus, the storage section has a word length larger than the history information to be recorded, and each time, Before writing the history information to be recorded into the storage unit, the apparatus is characterized by comprising means for rearranging the history information so that the bit position where past history information is stored is different from the bit position where new history information is written. Historical information recording method.