JPS61208150A - Collecting device for fault data - Google Patents

Abstract

PURPOSE:To collect fault information on transient software on a virtual storage system by recording the contents of a main storage write data register when a main storage write address coincides with an investigation object address. CONSTITUTION:A state flip-flop 14 which is set when the transient software is rolled in a main storage allows an AND gate 16 to control the output 38 of a comparing circuit 15 which compares the contents of a main storage address register 10 holding a write address of the main storage 12 with the contents of an investigation object address register 13 holding an investigation object address of fault occurrence. When a coincidence signal is obtained according to the set state of the flip-flip, a storage control circuit 20 is put in operation to store the contents of a data register 11 in a fault data storage circuit 21.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a fault data collection device for investigating the cause of a fault, and more particularly to maintenance and diagnosis of a data processing device using the fault data collection device.

(Prior Art) Conventionally, failures in data processing apparatuses have been detected by an abnormality detection circuit provided in the hardware itself or a data validity check means incorporated in software. It is easy to isolate the cause of the failure when the hardware detects an abnormality in other hardware, but when the hardware detects a software abnormality or the software detects an abnormality in data, it is easy to isolate the cause of the failure. It is not easy to investigate the cause of failure. Therefore, when an abnormality is detected, the system usually stops operating or interrupts the execution of the problematic business program and outputs the data in main memory to an output device such as a line printer. They adopted a method of logically considering the various traces of information left behind to find the cause. For example, even if it turns out that the data in main memory (data in a broad sense, including the program itself) is invalid, it is still necessary to check it using hardware or software to investigate the true cause. I had to think of tools.

(Problem that the invention attempts to solve) Therefore, the investigation takes a long time, and it is necessary to stop the system several times in order to understand the point in time when the data becomes incorrect. The disadvantage was that it had a large impact on people.

Conventionally, in order to collect such data, tracing devices have been created to trace the data written to a specific address in main memory, but software that does not reside in main memory has a physical address that is set in advance. Since it is not determined that
The drawback was that it could not be used with virtual memory systems.

Furthermore, although some virtual memory systems include means for tracing write data by logical addresses rather than by physical addresses, main memory accesses made from peripherals via channels are done by physical addresses; The problem is that the cause of the failure cannot be detected if the input data from the system is incorrect.

An object of the present invention is to eliminate the above-mentioned drawbacks by chronologically storing data that is written to any physical address only when non-resident software exists in the main memory in a virtual memory system. It is an object of the present invention to provide a fault data collection device having a wide range of applicability and configured so that fault investigation can be easily conducted without stopping the system.

(Means for Solving the Problems) A fault data collection device according to the present invention is configured to include a state flip-flop, an address register to be investigated, a comparison circuit, and a fault data storage circuit.

The status flag frog is used to indicate whether or not the target data exists on the main memory.

The investigation target address register is for storing the main memory address where the target data exists.

The comparison circuit is for comparing the contents of the main memory address register included in the main memory and the contents of the address register to be investigated.

The faulty data storage circuit stores the contents of the main memory write data register included in the main memory when the state flip-flop is set when writing data to the main memory and a match is obtained from the comparison result. It is something that can be memorized.

(Example) Next, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a failure data collection device according to the present invention. In FIG. 1, 10 is a main memory address register, 11 is a main memory write data register, 12 is a main memory element matrix, 13 is an address register to be investigated, 14 is a status flag flag, 15 is a comparison circuit, and 16 is an AND gate. , 17 is an instruction address register, 18 is an input/output channel register, 19 is a selection circuit, 20 is a storage control circuit, and 21 is a fault data storage circuit.

A first example showing an embodiment of the failure data collection device according to the present invention.
In the figure, main memory, as known to those skilled in the art, is comprised of a main memory address register 10, a main memory write data register 11, a main memory element matrix 12, and control circuitry (not shown). In the main memory, the data on the write data signal line 30 input from the main memory write data register 11 is input to the address specified by the address selection signal line 32 input from the main memory address register 10 to the main memory element matrix 12. written. The data read from the above address is
It is output to the read data signal line 31.

In the present invention, the contents of the investigation target address register 13 for storing addresses to be data investigated;
Status information of the status flip-flop 14 indicating whether or not data exists on the main memory is given by a software command from a control circuit (not shown) through an address signal line 55 and a data signal line 36, respectively. There is.

When non-resident software is needed in a virtual storage system, first, the virtual storage management software creates a correspondence between logical addresses and physical addresses on the main memory. Next, the non-resident software is rolled into the main memory from the external auxiliary storage of the magnetic disk device and executed, and the virtual memory management software rolls out the non-resident software from the main memory to the external auxiliary storage as necessary. Ru.

When correlating the logical address and physical address of non-resident software, the operating system including the virtual memory management software sets the address to be data collected in the investigation target address register 13.

Next, the state flip-flop 14 is set before executing an input/output command for rolling the target non-resident software from the external auxiliary storage device onto the main memory.

Also, when rolling out, state flip-flop 1
Reset 4.

The contents of the main memory address register 10 and the contents of the investigation target address register 13 are input to the comparison circuit 15 through signal lines 55 and 54, respectively, and if a match is obtained in the output of the comparison circuit 15, the output signal line 38 is set. . This set output signal is input to AND gate 16. If state flip-flop 14 is set, signal line 3
Since the output signal on 7 is applied to the other input terminal of AND gate 16, the state of output signal line 39 of AND gate 16 becomes logic %11. During main memory writing, the information on the output signal line 45 of the selection circuit 19 and the information on the output signal line 44 of the main memory write register 11 are sent to the fault data storage circuit 21 by the storage control circuit 20 via the control signal line 40.
write to.

A if state flip-flop 14 is not set.
The ND gate 16 does not operate, and writing to the fault data storage circuit 21 is not performed. When resident software is to be investigated, the target address is set in the register 13, but the state flip-flop 14 is controlled by the operating system so that it always remains set. Writing is performed in the fault data storage circuit 21 every time a fault is detected.

Writing to main memory is performed by software instructions, as well as by hardware during data transfer with peripheral devices. An instruction address register 17 and a channel number register 18 for data transfer, which are normally provided in a data processing device, are also provided in this embodiment, and the output of each register is a data signal *42.
．． 41 is input to the selection circuit 19. The selection circuit 19 is controlled by the value of an output signal line 43 of a control circuit (not shown). In the case of main memory writing by software commands, the information on the input signal line 42 is converted into an output signal? s
46, and in the case of writing to main memory while transferring data to and from a peripheral device, the input signal #! Since the information on 41 is sent to the output signal @45, any of the information will be stored in the fault data storage circuit 21.

Although the above embodiments have been described with reference to a single address to be investigated, it is also easy to construct a structure in which a plurality of addresses are investigated using associative memory. The information stored in the failure data storage circuit 21 can also be easily configured to be read out to the outside by software instructions according to known techniques.

(Effects of the Invention) As described above, the present invention detects a match between addresses and stores the write data and the software instruction that performed the write operation, or the requester information of the input/output operation, thereby preventing unauthorized operation. This has the advantage of being able to collect data in such a way that it can directly point out problems, remove faults early, and improve the operability of the data processing system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a failure data collection device according to the present invention. 10... Main memory address register 11... Main memory write data register 12... Main memory element group matrix 1B... Address register to be investigated 14... Flip-flop 15... Comparison circuit 16... AND Gate 17...Instruction address register 18...I/O channel register 19...Selection circuit 20...Storage control circuit 21...Storage circuit

Claims (1)

[Claims] a state flip-flop indicating whether or not the target data exists in the main memory; an investigation target address register for storing the main memory address where the target data exists; a comparison circuit for comparing the contents of the main memory address register with the contents of the address register to be investigated; and the state flip-flop is set when writing data to the main memory, and a match is found from the result of the comparison. 1. A fault data collection device comprising: a fault data storage circuit capable of storing the contents of a main memory write data register included in the main memory when the main memory write data register is obtained.