SU1124314A1 - Device for restoring information when occuring faults in computer blocks - Google Patents

Abstract

A DEVICE FOR THE RECOVERY OF INFORMATION WHEN A Digital Computer Block Fails, containing a group of data registers, an address decoder and a blocking trigger; the device fault input is connected to the zero input of the lock trigger, the address input of the device data to be restored is connected to the address decoder input, characterized in that, for the sake of simplicity, a request trigger, a write enable trigger, an AND element and a group of OR elements are entered into the device the device reference information record is connected to the single input of the request trigger, the output of which is the output of the device reference information recording request, the end input of the device connection operation With zero inputs for request triggers and write enable, the device write enable input is connected to the first input of the AND element, the output of which is connected to the single input of the write enable trigger, the single output of which is connected to the write enable inputs of each data register of the group, the first output of the address decoder is connected to a single lock trigger input, each output of the output group of the address decoder is connected to the read enable input of the corresponding group data register, each information input One group of device inputs is connected to the information input of the corresponding group data register, the information output of each group data register is connected to the corresponding input of the corresponding OR element, the outputs of the OR group elements are device information recovery outputs.

Description

The invention relates to computing and can be used to increase the reliability of information processing and the reliability of machines in operation, as well as in the development of high-reliability digital computers. It is known a device for recovering information from a digital computer, an essential one to one repetition of a microcommand that caused a malfunction, or a repetition of program section 1. The disadvantages of this device are the need to analyze each executed microcommand for the possibility of eliminating the consequences of its repetition, as well as the complexity writing programs with regard to the organization of sections suitable for repetition. The closest device to the proposed one is a device for eliminating the consequences of failures, containing a memory block, data transfer registers, sign triggers, a group of elements AND, a lock block, a counter, a data output block, a real-time repetition of the command, during the execution of which information distortion was detected, by reading this command and information from the data transfer registers 2J. The drawbacks of the device are the need to send the command or the Operand to the device when accessing the memory and its redundancy and complexity structures. The invention’s pitch is to simplify the device ..: The goal is achieved by having a device containing a group of data registers, an address decoder and a lock trigger, the device fault input being connected to the zero input of the lock trigger, the addressable year of the device data being restored, A request trigger, a write enable trigger, an AND element and a group of OR elements are entered, and the recording entry of the device reference information is connected to the single input of the trigger-Eapros, the output of which It is the output of a request for recording reference information of the device, the input of the end of the operation of the device is connected to the zero inputs of the request and enable recording triggers, the input for enabling the recording of devices is connected to the first input of the element, and whose output is connected to the single input of the recording enable trigger whose single output is connected to the inputs enable the recording of each data register of the group, the first output of the address decoder is connected to the jHbiM one input of the lock trigger, each output of the output group of the address encoder nen to the input resolution corresponding to the reading register OF DATA groups, each group of data input devices with inputs coupled An information input of the respective data register group inormatsionny OF DATA output of each register group is connected to the corresponding input of the Related element; ORT groups, the outputs of the elements of the LI group are the outputs of the device information recovery. The drawing shows a diagram of a predictable device. The device consists of a trigger 1 request, element And 2, trigger 3 write permission / trigger 4 blocking, decoder 5 addresses, a group of data registers 6, a group of elements OR 7. The device works as follows. When there are no distortions in the digital computer, the request trigger 1 generates, in the last cycle of each operation, an information request signal coming from the output of trigger 1 to the output of the device reference information request. Trigger 1 is set to a single state by the start of the request for information, which is generated in the digital computer after the result of this operation is written to the main registers of the digital computer module, and is reset by the signal of the end of the information request. Information from the main registers of an ALU digital computer by the information request signal is transmitted to a group of information inputs of the device, from where it arrives at the information inputs of the corresponding data registers b. The write enable entries of the registers 6 receive a recording signal of information from the output of the write enable trigger 3, which is set to one by the information recording start signal received from the output of the AND 2 element in the absence of a blocking signal, and is reset by the request ending signal. Writing information to data registers is performed simultaneously by an information recording signal. The information on the data registers in the absence of a fault signal changes with each new operation, but is not used for solving the tasks of a digital computer. If an error is detected during the operation of the digital computer, as indicated by the malfunction signal from the digital computer monitoring circuit arriving at the device fault input, the write lock trigger 4 is set to the zero state, as a result of which a second level signal is received at the second input of the element 2.

which leads to a constant zero state of trigger 3 for recording resolution. Thus, the recording signal is not generated until the record lock trigger 4 removes the inhibit signal, the data registers are not written, and therefore, the state of the main registers of the ALU of the digital computer is stored on them, erroneously performed operation According to the fault signal, the digital computer goes through the interrupt circuit to the execution of the fault signal processing program. In order to restore the main registers of the ALU of the digital computer, the program sequentially executes read instructions from the data registers 6. At the same time, the address code of the corresponding register of the data is sent to the address input of the device data to be restored. When the address is decoded, the output of the address decoder 5 generates an information read signal, which is fed to the read register input of the data register with the desired address. The information from the data register output goes to the input of the group of OR elements, and from their outputs to the outputs of the recovered information of the device. Further, the information is fed to the reception register of the information of the ALU digital computer. From the register of receiving information on the command

the fault signal handling program code is rewritten into a specific RAM cell. Thus, the contents of all data registers are rewritten in RAM.

The removal of the write inhibit signal to the 6-data registers is done by setting the lock trigger 4 to one state. To do this, use the device address command to the zero address. The signal received during the decoding of the zero address is fed to the single input of trigger 4 and sets it to the single state. As a result, the second input of the And 2 element receives a high level signal, not preventing the development of the information recording resolution signal.

The information read from the device and recorded in the RAM is used to restore the state of the main registers of the digital computer drive module. This is done with a number of transfer instructions from a specific RAM cell to the corresponding main register of the ALU digital computer. When the command counter is restored, the DVR is translated into a repetition of an incorrectly executed command.

The proposed device has a simple universal structure and ensures the effective elimination of failures detected by the digital computer control circuit.

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Claims (1)

DEVICE FOR RESTORATION - ‘INFORMATION INFORMATION AT FAILURES IN BLOCKS OF A COMPUTER, containing a group of data registers, an address decoder and a lock trigger; moreover, the device malfunction input is connected to the zero input of the lock trigger, the address input of the restored data of the device is connected to the input of the address decoder, characterized in that, for the sake of simplification, a request trigger, a write enable trigger, an AND element, and an OR group of elements are input, and the input recording the device’s reference information is connected to a single input of the request trigger, the output of which is the output of the request recording the device’s reference information, the input of the end of the operation of the device is connected to by the input inputs of the triggers of request and recording permission, the input of the recording permission of the device is connected to the first input of the And element, the output of which is connected to a single input of the recording permission trigger, the single output of which is connected to the recording permission inputs of each group data register, the first output of the address decoder is connected to a single input blocking trigger, each output of the group of outputs of the address decoder is connected to the read permission input of the corresponding group data register, each information input of the group is rows of devices connected to the data input of the corresponding data register groups, each group of data output data register connected to the corresponding input of the respective OR gate group OR element outputs E group are output information recovery device.