SU1439600A1 - Device for determining electronic computer capacity - Google Patents

Description

A one-bit memory block, a switch and a timer are inserted into the device: the device’s address input is connected to the one-bit memory block address input and to the first input of the third comparison unit, the output of the zone storage unit I is connected to the second input of the third comparison unit, the output I of which is connected to the third input of the branch of the microprogram control unit, the output of the OR element and the device start input are connected respectively to the switching input and the first I start input of the timer, the first and I second outputs of the switch yens

respectively, a write input and a read input of a single-bit memory unit; the second output of the switch is connected to the input B of the timer, the output of the end of the time interval and the information output of which are connected respectively to the switching input of the mode of the microprogrammed control unit and the second information input of the zone memory unit, . the output of the one-bit memory block is connected to the second start input of the timer, with the counting input of the current value counter and the input of the start of the cycle of the microprogram control unit.

The invention relates to computing technology, in particular, to organizing the monitoring of the efficiency of the functioning of computing systems.

The purpose of the invention is to expand the functionality of the device by allowing the number of executed commands of each type per unit of time to be counted.

Fig. 1 shows a functional diagram of the device J in Fig. 2 — a functional diagram of the control unit in Fig. 3. - the functional diagram of the comparison block J in FIG. 4 - the functional diagram of the timer, in FIG. 3 and 6 the operation algorithm of the control unit.

The device includes 1-3 comparison blocks, a current address memory block 4, a zone memory block 5, a block of a memory of a number of accesses, a single bit memory block 7, a block of 8 MHKponporpat-JMisoro control, a block 9 print, switch 10, current value counter 11, address counter 12, fill counter 13, number of accesses counter 14, timer 15, VDI element 16, address input 17.1, input 17.2 match, input 17.3 reset, stop input 18. The printing block in the composition of the device is not vkodit.

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five

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Firmware control unit 8 consists of a sequence | but connected by the modifier 19, the register of the micro-command address 20, the decoder of the micro-address address 21, the fixed memory block 22, has an initial setup input 23, a clock input 24.

The operation of the control unit 8 is based on the principle of microprogram control, it operates according to the clock generator signals in accordance with the microprogram recorded in the permanent memory block 22. Signal processing from external units is performed by a register modifier 20, and therefore, the order of action of control unit 8.

Blocks 1-3 comparisons are identical. For example, we describe block 1, which consists of n elements 25.1, 25.25 ...,; 25.p EXCLUSIVE OR, Element OR 26, .ELEMENT NOT 27, Element AND 28 and 29; . Timer 15 contains a time counter 30, trigger 31, elements H 32, OR 33 and 34.

Blocks 4-6 of memory can be implemented, for example, on floppy dnskah-150 or floppy disks. The one-bit high-speed memory unit 7 is a semiconductor memory with an address organization with a capacity of M words but 1 bit, where M t is the length of the address code of the controlled computer.

The device works as follows.

In the initial state, the counters of the number of calls (implemented by the algorithm block 43), the current values of i, the address i, the filling (k) of the time counter 30, all the cells of the memory blocks 4-7 contain the code 00 ... O, on the address register 20 the microcommand sets the address of the initial micro-, manda, the modifier is set to its original position, the contents of the trigger 31 is zero, the switch 10 is set to the Record position.

The device begins to function in the recording mode, in which the region of monitored addresses is specified, which is carried out as follows. In a controlled computer

20, a single signal will not be generated at the output of the memory block 7, the device will remain in a state of waiting for an address entering the monitored area. The following is executed the program ENTRY OF THE AREA, which carries out the sequential access to the memory cells included in the specified area and {sending their contents in the production area to the monitored area of the pan cell, while the contents of the cell of the blocks devices turn

the controlled area does not change. It is better to arrange shipment by dummy address, i.e. the address of a disconnected or physically non-existent device; in this case, during the operation of the ENTERING AREA program, the contents of all memory cells do not change. At the input 17.1 of the device, the addresses of all cells in the monitored area appear sequentially. Ka input 17.2 — read signals, which through switch 10 are fed to the write input of block 7, in which

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In parallel with the fixation of calls, the device processes them. 30 According to the signal of block 8, the current value counter 11 is reduced by a unit and read from the memory block 4 the contents of the last significant cell. The signal of block 8 is returned by comparison block 1, to the inputs of which the output information of memory blocks 4 and 5 is fed. Simultaneously produced for 35

Writing to the counter 14 of the contents of the program corresponding to the addresses is included, up to the corresponding memory cell of block 6.

units in the controlled area, correspond to one, the remaining addresses - zero. Units are also contained in block 7 by the addresses of the commands of the ENTER AREA program, but this is not essential, since this program is not used in computer control mode.

 At the end of the program, the INPUT AREA switch is set to position 2, in which signals from the output of element 16 OR are supplied to the read input of block 7 and the stop input of timer 15, the device in this case is ready to work in gg, the contents of counter 12 have reached

control mode In this revs, the computers execute a program located in a given area, and the addresses

the value recorded in the filling counter 13 (i.e., the number of addresses addressed was accessed) and the contents of the selected

0

executable commands, on inputs 17.2 and 17.3 control signals that access program commands, the signal from the output of the OR 16 element suspends timer 15 and reads the contents of block 7 at the address at input 17.1. In the event that the address is in a controlled area, the output of block 7 will be

A single signal is generated that starts a pause timer, increases by one the contents of the current value counter 11 and sets the modifier 19 to a state in which the block 8 writes the monitored address to the current value memory block 4 with the next clock signal. Otherwise

0, no single signal will be generated at the output of the memory block 7, the device will remain in a state of waiting for an address entering the monitored area. Upon further processing to the monitored area of the memory of the device units

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In parallel with the fixation of calls, the device processes them. The signal of block 8 is used to reduce the content of current value counter 11 by one unit and is read from memory block 4 of the contents of the last significant cell. The signal of block 8 is returned by comparison block 1, to the inputs of which the output information of memory blocks 4 and 5 is fed. Simultaneously produced for

In the case of equality of the contents of the selected cell block 4 and the first cell of block 5 (i.e. at this address in a controlled computer previously

4g reversal) a unit is added to counter 14 and its content is recorded in memory block 6 at an unchanged address, i.e. to the same cell, from where the previous quantity was read

gQ hits. If the contents of the cells of blocks 4 and 5 are not equal, the contents of the counter 12 are enlarged and compared with the contents of the next cell of the memory 5. If a

same contents of counter 12 reached

the value recorded in the filling counter 13 (i.e., all the addresses that were accessed were searched) and the contents of the selected

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cells of memory 4 turned out to be inactive for any of the cells of the ami of block 5 (they were registered for the first time), then the contents of the selected cell of memory 4 are overwritten into a free cell of memory 5, for which the content is increased by one counters 12 and 13.

The device ends up being monitored at the end of the set time interval — in this case, an overflow signal is generated from the counter 30, or from input 18. The signal from the output of timer 15 is fed to the operating mode switching input 8. At the same time, unit 3 finishes processing the current information and waits for the printout of the contents of memory blocks 5 and 6, which is produced during the execution of the computer-controlled output program. This program differs in functions from the program OUTPUT OF THE AREA only in that the time interval between organized transfers is observed to exceed the operating time of the printing unit 9. At the input 17.1, the addresses belonging to the monitored area appear sequentially, and to the input 17.2 there is a control signal that polls black 7, at the output of which a single signal is generated, which starts the operation cycle of the control unit 8 in a mode.

The address on the bus is compared in series with the contents of f-T.J

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In the event of a 3 rd address (from the blistering of the following, they increased the trace of the continuation of the treatment with the Pro cate programmer on the other hand. T REMAINS of the system with the reversal of external measurement

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all cells of block 5 are compared. In case of equality of the address with the contents of one of the cells, the signal from comparison unit 3 outputs this address (from block 5) and the recorded number of hits on it (from block 6) to print block 9 and waits for the next one. If the adress on the bus is not equal to the contents of this cell, the contents of counter 12 are increased, the contents of the next cell are selected. The described process continues until the content counters 12 of the address and filling 13 match, after which the device proceeds to wait for the next address at input 17.1 The process ends after the search program CANNED all addresses of the monitored area. The contents of the time counter 30 are then output, after which the device of the computer performance boost can be turned off. Thus, the ordered (according to the program output) addresses of a given area with a fixed number of references to them are printed. The total number of hits for a given time interval N-represents the performance of the computer itself. At the end of monitoring the signals of the external timer to input 18, it is possible to measure the relative execution time of programs belonging to the control area, which expands the functionality of the device.

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Claims (1)

DEVICE FOR DETERMINING COMPUTER PRODUCTIVITY, comprising first, second and third comparison units, a firmware control unit, a current address memory unit, a zone memory unit, a number of access memory units, an address counter, a current value counter, a fill counter, an number of access counts and an OR element, moreover, the address input of the device is connected to the address input of the current address memory unit, the output of which is connected to the first information inputs of the zone memory unit and the first comparison unit, the output of the zone memory unit is dined with the second information input of the first comparison unit and is the first information output. the device’s house, the outputs of the inequality and equality of the first comparison unit are connected respectively to the first branch input of the microprogram control unit and to the counting input of the counter of the number of calls, the output of which is the second nnfor-. the device’s output and is connected to the information input of the number of accesses memory block, the output of which is connected to the information input of the number of accesses counter, the output of the address counter is connected to the first information input of the second comparison unit and the address inputs of the memory zones and the number of accesses, the output of the current values counter is connected with informational. by the input of the memory block of the current addresses, the output of the fill counter is connected to the second information input of the second comparison unit, the output of which is connected to the second branch input of the firmware control unit, the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh , the twelfth and thirteenth outputs of which are connected respectively to the input of the subtraction of the counter of the current values and the input of the record, the read input of the memory block of the current addresses, the write input of the memory block of the number of hits, the readout of the memory blocks of the zones and the number of accesses, the setting input to zero and the counting input of the address counter, with the input of the fill counter record, the polling inputs of the first, second and third comparison blocks, the equality output of the third comparison block is the third information output of the device, reading inputs and. zeroing the device are connected respectively to the first and second inputs of the computer element, characterized in that, in order to expand the functionality of the device by providing the possibility of counting the number of executed commands of each type per unit of time, S and 1439600, a single-bit memory unit, a switch and a timer are introduced into the device, and the address input of the device is connected to the address input of the single-bit memory unit and to the first input of the third comparison unit, output I of the zone memory unit is connected to the second input of the third comparison unit, the output of which is connected to the third branch input of the microprogram control unit, the output of the OR element and input j of the device start are connected respectively to the switching input and the first input of the timer start, the first and second outputs the switch is connected respectively to the recording input and the read input of a single-bit memory block, the second output of the switch is connected to the stop input of the timer. the output of the end of the time interval and the information output of which is connected respectively to the mode switching input of the microprogram control unit and the second information input of the zone memory block, the output of the one-bit memory block is connected to the second input of the timer start, with the counting input of the current value counter and the input, the beginning of the microprogram control block cycle .