SU1472909A1 - Dynamic addressing memory - Google Patents

Abstract

The invention relates to the field of computing, in particular, to storage devices, and can be used, for example, in processors with asynchronous calculation management for storing operands and results of operations. The invention improves the performance of a memory device with dynamic addressing, containing data buffering unit 1 and generating lower address bits of the storage unit, control unit 2, memory unit 3, first memory unit 4, number of copies of information, buffer register unit 7, by introducing the second unit the memory 5 of the number of copies of the information and the block 6 of the store memory, which makes it possible to ensure simultaneous execution of recording and reading operations from the memory device with dynamic addressing. 5 il.

Description

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The invention relates to computing, in particular, to storage devices (RAM), and can be used, for example, in processors with asynchronous calculation management for storing operands and results of operations.

The purpose of the invention is to increase the capacity of the device by allowing simultaneous recording and reading operations.

Figure 1 shows a block diagram of a memory device with dynamic addressing; Fig. 2 is a functional block diagram of the control unit; FIG. 3 is a functional block diagram of the data buffering and generation of lower address bits; 4 is a functional block diagram of the buffer registers; in FIG. 3, the interaction of the memory device with dynamic addressing with the external environment;

The memory with dynamic addressing (see FIG. 1) contains a block 1 for buffering data and forming lower-order address bits, control block 2, memory block 3 (basic information), first and second memory blocks 4 and 5 of the number of copies of the basic information block 6 of the store memory for storing addresses of free cells of block 3, block 7 of the buffer registers. Unit 1 has two groups of inputs 8–11 and 12–15, as well as input 16 clock pulses and outputs 17–28, Control unit 2 has inputs 29–35, output 36, input 37, outputs 38–40, input 41, outputs 42 and 43, input 44, output 45 and input 46. The buffer register unit 7 has inputs 47-51 and outputs 52-55.

Control unit 2 (see FIG. 2) contains elements 55-66, including multiplexers 65 and 66, switching information and control signals of blocks 4 and 5, adders 58 and 59, and registers 63 and 64, which reduce the content of the above blocks 4 and 5 of the memory of the number of copies per unit and fixation of the obtained values, elements 56 and 57 for zero verification, multiplexer 60, AND 61 and D-flip-flop 62, which produce the write-enable signal of block 6 of storage memory.

Block 1 (see FIG. 3) contains the elements 67-84, including the buffer registers of the input signals of the memory with dynamic addressing, hectare also 0

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ki the lengths of the vectors of the written and read data with schemes for analyzing their contents to zero. Store memory block 6 has an organization, where t is the address width of the main information vector. Block 7 buffer registers (see figure 4) contains the elements 85 and 86 of the delay required between the latches conveyor devices, as well as D-triggers 87-90 output signals of the charger with dynamic addressing.

The structure of the input information for recording on the first group of inputs of a memory device with dynamic addressing is as follows (see Fig. 5): data of the basic information (D), length of the data vector (DV); the number of copies of the data (QC), the first accompanying signal, the arrival of which indicates the need to perform a write operation (CC1); the destination address to which it is necessary to send information located on the first group of outputs of a dynamic-addressable memory (AU) memory.

The first group of outputs of the memory with dynamic addressing contains the following information about the recorded data: the value of the length of the vector of the recorded data (DV), the number of the memory bank that stores the number of copies of the recorded data (NB); dynamically formed address of the recorded information (A), the second accompanying signal, indicating the presence of information on the first group of outputs of the memory with dynamic addressing (CC2).

The second group of inputs of the memory device with dynamic addressing is intended for performing a read operation and contains the address of the required data (A), the number of the memory bank storing the number of copies of the required data (NB); the length of the data vector (DV), the third accompanying signal, indicating the need to perform the reading operation (CVD).

The second group of outputs of the memory with dynamic addressing is intended for reading the required information and contains read data (D), data vector length (DV), the fourth accompanying signal, indicating the presence of read information (CC4).

The number of copies of the recorded data indicates the number of read operations,

required to free memory cells occupied by this data.

The device has the following notation: n is the data size; t is the size of the register of the length of the vector $ 1 - the maximum length of the vector (); K is the register size of the number of copies of the data; S is the maximum number of copies of the data (); m is the data address width.

Storage device with dynamic addressing works as follows.

The setting of the initial state of the memory device is performed once before the start of its operation and is accomplished by repeatedly performing a read operation from the memory at sequential addresses in the interval from 0 to 2. As a result, the store memory block is completely filled with the addresses of free vectors of the basic information of block 3.

A write and read operation occurs at strictly defined points in time defined by a sequence of clock pulses, which is fed to the input of clock pulses of a memory device with dynamic addressing.

Dynamic addressing memory is designed for use in conveyor processing systems and is a two-stage conveyor for reading data and a single-stage conveyor for writing data. Reading and writing data is carried out simultaneously. Data can be fed to the input of the device and removed from its outputs every machine cycle. From the moment information arrives at the inputs of a memory device with dynamic addressing, the required operation requires two clock periods for reading and one period for writing data. All the input information received at the input of the memory with dynamic addressing is stored in the registers of the data buffering unit 1 and the formation of lower address bits.

A data vector record is made in the free cells of block 3. A data vector is written to the memory sequentially over the elements. The vector length register in data buffering unit 1 and the formation of lower address bits sets the offset for each

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vector element relative to the starting address of the data vector. The addresses of the free data vectors of block 3 are stored in block 6 of store memory, and by the time the vector is written the address of the first free vector is applied to the higher bits of the block 3 write address. The data vector length register is connected to the lower bits of the block 3 write address. for each element of the data vector, the register content is decremented by one. When the value of the vector length register becomes zero, the vector recording is stopped and the next address of the free data vector is extracted from the store memory block 6.

Each data vector is associated with a characteristic such as the number of copies of the vector. The number of copies of the vector indicates the number of read operations for this vector, after which the release of memory with dynamic addressing from this vector, i.e. the address of the vector is recorded in block 6 of the store of addresses of free vectors. The number of copies of the data vectors is recorded in one of two blocks 4 and 5 of the memory. The memory block number, in which the number of copies of the data vector is written, is chosen opposite to the specified signal by the Memory Bank Number on the group of inputs of the read-only memory with dynamic addressing. The addresses of the data vector record and its number of copies in block 3 and the first and second blocks 4 and 5 are the same. The address of the recorded data vector, its length and the number of the memory bank in which the number of copies of the vector, is, are output to the first group of outputs of the memory device with dynamic addressing.

The reading of the data vector from the dynamic addressable memory is as follows.

The address of the data vector, its length, and the number of copies are fed to the second group of memory inputs with dynamic addressing, the station. Similarly, the data writing operation is performed by element-wise reading of the vector from block 3 by decreasing the value of the register of the length of the vector connected to the lower bits of the reading address of block 3. In addition, the number of copies of the data vector is read from the specified memory bank and compared to zero.

If the number of copies of the data vector becomes zero, then the address of this vector is recorded in block 6 of the storage of free data vectors. The operations of writing and reading data from a memory device with dynamic addressing can be combined in time. Recording mode

The initiation of the write operation is performed according to the active value of the first accompanying signal. With the arrival of a clock pulse, information is written from the first group of memory inputs to the buffer registers 69-71, 80 of block 1. At the same time, the free vector address from block 6 of the store memory is written to the buffer register 88 of the buffer register block 7. This address from output 54 of block 7 of the buffer registers goes through input 30 of control block 2 to multiplexers 65 and 66 of this block and through outputs 38 and 42 to the write address of block 5 and 4. In addition, the address of the free vector goes to high bits the entry address of the recording block 3. Thus, the starting address is set, which will be used to record the vector in the memory with dynamic addressing.

The input state of the bank number of the second group of inputs of the dynamic addressable memory is recorded in the trigger 83 of block 1 and through the output 23 of this block enters the input 48 of block 7 and the input 34 of control block 2, where it controls the operation of multiplexer 60.

At the output 55 of the block 7 of the buffer registers, the value of the input of the number of the memory bank of the second group of inputs of the memory with dynamic addressing appears at the predetermined moment of time recorded on the trigger 90 of block 7. This value is fed to the input 44 of the control block 2 controls the operation of multiplexers 65 and 66 of this block, commuting the write circuit of the first and second blocks 4 and 5 of the number of copies of the memory. -This switchboard prepares for recording in the next cycle the value of the number of copies of the data stored in the buffer register 80 of block 1, v one of the memory blocks 4 or 5. The following also records this data from the buffer register of block 1 into block 3 On the first group of outputs of the memory with dynamic addressing

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information appears on the length of the recorded vector, the number of the memory bank, and the address of its entry in the dynamic addressing memory device and the second accompanying signal indicating the completion of the write operation.

After writing each element of the data vector, the length of the vector written in the buffer register of block 1 is reduced by one and analyzed to zero. This is provided by the capabilities of the buffer register 70 of block 1 itself and the elements 67 and 75 of this block. The equality to zero of the contents of this register causes the reading of a new free vector address from block 6 of store memory and writing the number of copies of the vector from the buffer registers of block 1 to blocks 4 or 5 of memory.

The read operation is initiated by the active value of the third accompanying signal. With the arrival of the clock pulse, information is recorded from the second group of memory inputs with dynamic addressing to the buffer registers 72-74, block 1. The address of the data vector from the output 26 of block 1 is fed to the read address of blocks 4 and 5 of the memory, as well as older bits dy entry address reading block 3.

The number of copies of vector data read at a given address from the first or second memory block 4 and 5 is reduced by one at adders 58 and 59 of control block 2, and then checked for zero by elements 56 and 57 of the same block. The multiplexer 60 of control unit 2, depending on the memory bank number specified at the input of the memory with dynamic addressing, selects one of the output signals of these elements and, if there is a third accompanying signal on the second group of inputs, the memory with dynamic addressing is connected to the information input D of the flip-flop 62 of unit 2 management

The following also records the read from block 3 given in buffer register 87 of block 7 of buffer registers. In addition, the recording of the reduced per unit number of copies of the vector data in the registers 63 and 64 of the control unit 2 is carried out with the purpose of subsequent rewriting of this value into the specified second

group of memory inputs with dynamic addressing memory bank, i.e. first or second block 4 or 5 of memory. As mentioned above, the operation of the blocks 4 and 5 of the memory is carried out by the multiplexers 65 and 66 of the control block 2, which switch the information and control circuits of these blocks depending on the memory bank selected for the operation,

It should be noted that the processes of reading and writing information occur independently of each other and therefore can be combined in time. In addition, dynamic addressing memory can work with both vectors and scalar data (the length of the vector is equal to one). Dynamic addressing memory can be used in vector-stream processors, machines with dynamic architecture, etc.

invention formula

A memory device with dynamic addressing, containing a data buffering unit and generating lower-order address bits, a buffer register block, a memory block, a first memory block of the number of copies of information, and a control block, the first input of the control block connected to the output of the first block the number of copies, the information input, the recording address input and the write resolution input of which are connected respectively to the first, second and third outputs of the control unit, the write permission input, the information input, the low The address of the memory block write address is connected to the first, second, and third outputs of the data buffering block and the formation of the lower address bits, respectively. The output of the memory block is connected to the first information input of the buffer register block, the fourth output of the data buffering block and the lower address bits. with the second input of the control unit, characterized in that, in order to increase the capacity of the memory device with dynamic addressing by providing simultaneous implementation of operations recording and reading information, the second memory block of the number of copies of the

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the formations and the store memory block, the information input, the write address input and the write enable input of the second memory block of the number of copies of information are connected respectively to the fourth, fifth and sixth outputs of the control unit, the third input of which is connected to the output of the second memory block of the number of copies information, and the seventh output is connected to the write enable input of the store-memory block, whose information output is connected to the second input of the buffer register block, and the enable input of the store-read operation AM - with the fourth input of the control unit and connected to the fifth output of the data buffering block and forming the lower bits of the address, the corresponding bits of the sixth output of which are connected to the read address inputs of the first and second memory blocks of the number of copies of information and the higher bits the memory block read addresses, the seventh output of the data buffering block and the formation of the low-order bits of the address are connected to the information input of the store memory block and to the fifth input of the control block, the eighth and ninth outputs of the block b data FER and formation of low-order bits of the address, respectively, with the sixth and seventh inputs of the control unit and the third and fourth inputs of the block of buffer registers; the corresponding bits of the sixth output of the data buffering block and formation of the lower-order address bits are connected to the inputs of the lower address bits of the memory block ti, the first - the fourth inputs of the data buffering block and the formation of the low order bits form the recording entry of the device, the fifth - eighth inputs of the data buffering block and the formation of the low The address addresses of the device read input, the ninth input of the data buffering unit and the formation of the lower address bits, the eighth input of the control unit and the gate input of the buffer register block are connected to the input of the device clock, the tenth output of the data buffering unit and the formation of the lower address bits is The first output of the first group of device outputs, and the eleventh output of the data buffering unit and the formation of low address addresses is the first output of the second group of device outputs, the first the output of the buffer register unit is connected to the ninth input of the control unit and is the second output of the second group of device outputs, the second output of the buffer register unit is the third output of the second group of device outputs, the third output of the buffer register unit is connected to the tenth input of the control unit, the input

the higher bits of the memory block write is the second output of the first group of device outputs, the fourth output of the buffer register block is connected to the eleventh input of the control unit and is the third output of the first group of device outputs, the first input of the data buffering block and the lower address bits the fourth output of the first group of outputs of the device.

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Claims (1)

The claims 25 A memory device with dynamic addressing, which contains a block for buffering data and generating low order bits of the address, a block for buffer registers, a memory unit, a first memory unit for the number of copies of information and a control unit, the first input of the control unit being connected to the output of the first memory unit for the number of copies, information an input, a recording address input and a recording permission input which are connected respectively to the first, second and third outputs of the control unit, a recording permission input, an information input, a low-level input poisons of the write addresses of the memory block are connected respectively to the first, second and third outputs of the data buffering unit and the formation of low order bits, the output of the memory block is connected to the first information input of the buffer register block, the fourth 'output of the data buffering unit and the formation of the youngest 50 bits of the address is connected to the second the input of the control unit, which is characterized by the fact that, in order to increase the throughput of a memory device with dynamic addressing by ensuring simultaneous operations recording and reading information, a second memory block of the number of copies of information and a store memory block are introduced into it, and the information input, recording address input and write permission input 5 of the second memory block of the number of copies of information are connected respectively to the fourth, fifth and sixth outputs of the control unit, the third the input of which is connected to the output of the second 19 memory block of the number of copies of information, and the seventh output is connected to the write permission input of the store memory block, the information output of which is connected to the second input block buffer registers, and the input enable reading operations of the store memory block with the fourth input of the control unit and is connected to the fifth output of the data buffering unit and 29 generation of lower order bits, the corresponding bits of the sixth output of which are connected to the read address inputs of the first and second memory blocks of the number of copies information and 25 with the input of the upper bits of the read address of the memory block, the seventh output of the block of data buffering and the formation of the lower bits of the address is connected to the information input of the block mage memory and with the fifth input of the control unit, the eighth and ninth outputs of the data buffering unit and the formation of the lower order bits - respectively, with the sixth and seventh inputs of the control unit and the third and fourth inputs of the buffer register block, the corresponding bits of the sixth output of the data buffering unit and the formation of low the bits of the address Ιθ are connected to the inputs of the lower bits of the read address of the memory block, the first fourth inputs of the data buffering block and the formation of the lower bits of the address form the input record 15 devices, the fifth - eighth inputs of the data buffering unit and the formation of low order bits form the '/ device read input, the ninth input of the data buffering unit and the formation of low order bits, the eighth input of the control unit and the gate input of the buffer register block are connected to the input of the device clock pulses, the tenth output of the data buffering unit and the formation of the least significant bits of the address is the first output of the first group of device outputs, and the eleventh output of the data buffering unit and the formation of the least significant discharge J 1 1 2 dov addresses is the first output of the second group of device outputs, the first output of the buffer register block is connected to the ninth input of the control unit and is the second output of the second group of device outputs, the second output of the buffer register block is the third output of the second group of device outputs, the third output of the buffer register block connected to the tenth input of the control unit, the input of the most significant bits of the recording of the memory unit is the second output of the first corpse, the output of the device, the fourth output of the block of buffer registers soy Din with the eleventh input of the control unit and is the third output of the first group of device outputs, the first input of the data buffering unit and the formation of the least significant bits of the address is the fourth output of the first group of device outputs. Operand record Reading the operand. Fi, city 5