SU1605273A1 - Multichannel data acquisition device - Google Patents

Abstract

The invention relates to automation, remote control and computing, and can be used in information transmission and reception systems. The purpose of the invention is to increase the reliability of the received information. The device contains a pulse generator 1, a counter 2, a multiplexer 3, the first 4 and second 14 memory blocks, the first 5 and second 15 address generators, the first 6 and second 16 priority comparison units, elements And 7,8,12,13,19, 20, the first 9 and second 21 transmission control blocks, the first 10 and second 11 information processing blocks, the first 17 and second 18 parallel interfaces. The device allows detecting the “triggering” of any channel, approximating this “triggering”, i.e. clear from the “bounce”, precisely tied to the time when this “trigger” occurred, and generate output information about each “trigger” in any channel. 1 tab., 8 Il.

Description

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The invention relates to automation, telemechanics and computer technology and may find application in multi-channel information transmission and reception systems.

The purpose of the invention is to discover the reliability of the received information.

Fig. I represents the functional diagram of the device; figure 2 - functional scheme of the first memory block

ti; FIG. 3 is a functional diagram of the first address resolver; figure 4 is a diagram of the first and second information processing units; FIG. 3 is a functional diagram of the second address generator; FIG. in fig. b - functional scheme of the second transmission control unit; Fig. 7 is a block diagram of information in the first memory block; Fig. 8 is the same in the second memory block.

The device contains a pulse generator, a counter 2, a multiplexer 3, the first memory block 4, the first address generator 5, the first priority comparison block 6, the first 7 and. The second 8 And elements, the first transmission control block 9, the first 10 and second 11 information processing blocks the third 12 and fourth 13 And elements, the second memory block 14, the second address generator 15, the second priority comparison block 16, the first 17 and second 18 parallel interfaces, the fifth 19th and sixth 20 elements And, the second side 21 of the transmission control.

In addition, figure 1 shows the data highways MD for the microcomputer, the addresses MA and the control MU.

The memory block (Fig. 2) contains memory elements according to the number of crystals that can be executed on chips of the RUZ 132 series.

The address generator (FIG. 3) contains a decoder 23 made on a 533 series ID7 microcircuit, a multiplexer 24, a 533 PPC series IC chip elements OR 25) - 25. Each information processing unit performed on the microcomputer (FIG. 4) contains a microprocessor 26 of the type 1810 VM86, address register 27 is a 533TM9 microcircuit, RAM 2 of the stack segment is an interrupt segment ROM 29, the code segment ROM 30, the initial ROM 31 launch. All ROMs are executed on a 556PT7 microcircuit. The second address driver (FIG. 5) contains bus formers

five

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five

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32 - 35 drivers on chips. 589АП26.

The information output unit (FIG. 6) contains an AND 36 element, a buffer register 37, a control unit BU 38, made according to the pulse distributor circuit on an IC 533 IR16, shift register 39.

To ensure the operability of the device, its remaining blocks can be implemented as parallel-programmable interfaces such as 580ВВ55, the first block

9 transmission control - 589AP26, multiplexer 3 - 533KP11.

The device works as follows.

Before the device starts operation, a Reset signal is received, which reset the blocks.

10 and 11 and sets the counter to zero.

Then, the counter 2 recalculates the pulses from the generator 1 to digitize the time and control the multiplexer 3. The T multiplexer 2 polls the input channels and the information from the device input is sequentially recorded in the first memory block 4 in accordance with the address formed by the lower bits C} ,, .. , n counter 2. During the time of the first measurement, determined by one polling cycle of all channels, information from them is recorded in the first bits from the 1st to the 2nd cells of the memory block 4, as shown in Fig.7 1 (A - AJ). In the second dimension (the second polling cycle), the information received on all channels is recorded in the second bits of the same cells (Fig. 7, A - A), etc.

As a result, sixteen measurements (according to the number of RAM bits of the memory block 4) are recorded in the first 2 cells of the memory block 4. Consequently, it reads 16 measurements of the first channel in block 10 (microelectric) of the first cell of memory 4 in the general purpose register (RON). Then, the information is recorded in the second group of cells 2 1, ..., 2x2, which contain measurements from 17 to 32 of each of the Lig.7 channels (A.

A A - “eg zgBlock 10 (microcomputers) when referring to an external device decrypted on an AND 8 element, reads the contents (address and time) of counter 2.

ten

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through block 9, i.e. write address of information in memory block 4. Since memory block 4 represents the DS data segment for block 10 (microcomputer), the read address is formed in the SI register. Block 10 (microcomputer) calculates the difference between the write and read addresses and, if this difference is greater than the size of the group, i.e. between a read address and a write address, there is an entire group of channels, then block 10 proceeds to the algorithm for processing information of the channels of this group.

In order to eliminate conflicts that arise when simultaneously accessing memory block 4 for writing (from generator 1) and reading (from block 10), block 6 for comparison of priorities is turned on. If information is recorded in memory 4 and at this time, block 10 accesses the same block for reading, the information will be read after the end of the write cycle, and the readiness signal (RDY) is recorded for the time the information is written from block 10. If memory block 4 is busy reading information in block 10 and at that time a write request has arrived, then write access will occur after the end of the read cycle.

The control signals for writing and reading from the priority comparison unit 6 are sent to the shaper 5, which is the KONwyTHpyeT address for accessing the memory block 4. The structure of the recording of information in the memory block 4 is provided by the architecture of the memory block 4 itself and the address shaper 5.

The decoder 23 (Fig. 3) provides for the choice of a crystal in memory block 4 (Fig. 2, 22 (- 22, g) for each of the 16 bits of the cell, at the address that comes from counter 2 (bits n + 1 .. . + p4).

Access to memory block 4 (read or write) is made through multiplexer 24, which switches the lower bits of the address of memory block 4 OR from the block address address block 10 (microcomputer) or from the outputs of counter 2.

The algorithm of block 10 (microcomputer) is to determine the fact of channel triggering (by the fact that the signal channel triggers, the change in information in the channel within the limits of

thirty

25

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sixteen measurements, which are recorded in one cell of memory block 4. For this purpose, the previous states of all 2 input signal channels are located in the initial region of the SS stack segment (RAM 28 of the stack segment) addressed by the BP register of processor 26.

The channel triggering should be fixed if the passage to the new state is confirmed by at least two dimensions. A numerical example is provided for explanation.

Let the measurements on one of the channels be equal

A, jAgA AgAgA, /. , A., A, A, 00010001000 10,000

such one-time transitions to a unit are not considered to be triggered. Suppose that the previous state of this channel is also 0. To determine whether the microprocessor triggers, it logically multiplies this binary code, shifted one bit to the right, with the previous left bit the status of this channel

0001 0001 0001 0000 Previous sos x00 SHOO1000 SHOO

TOYANIE --QQQQ QQQQ QQQQ QQQQ

The zero result of the logical multiplication indicates that there is no channel trigger. Let the measurements on one channel be equal

A AjA A A-AgAvAgA A A A jA Ai gA 1111011110111011

The previous state is one. In this case, inverse measurements are logically multiplied along a channel with the same inversion shifted by one bit to the right.

Thus, if at least one of the two tests described gives a zero result, it means that the channel is not triggered, if there was a trigger, then the result will be different from zero. If there was no trigger in the channel, block 10 (microcomputer) proceeds to the analysis of the next channel until the channel that has been triggered is detected. As soon as the fact that the channel is triggered is detected, in accordance with the algorithm, block 10 (micro-computer) writes into memory block 14, which is an additional segment of ES with respect to block 10 (first micro-computer), the following data: the contents of counter 2 in two memory cells , the read address of memory block 4 (the contents of microprocessor register SI 26), all sixteen channel measurements in which the response is recorded (Fig. 8),

The second memory block 14 is a data segment for the block 11 (microcomputer), the Second block 11 (the second microcomputer) continues processing the information recorded in the memory block 14.

Since the information on channels goes to memory block 4 ahead of reading (from this same block 4) to processing unit 10, the time, which is determined by counting 2, has gone ahead with respect to the group of channels whose information is currently being processed. To determine the actual recording time of the channel that is currently being processed by block 10, it is necessary to subtract from the counter code 2 the number of complete cell groups (2 cells in each group) by multiplying by the memorization time of one group, i.e. . time t of the first change

rheni in a group of 16 channels - t

An integer number of groups of cells is determined within the difference between the address of the record (the contents of the counter 2 and the least significant bits) and the address of the read (the next cell in the second memory block). The number of the triggered channel is determined by the lower n-bits of the read address. Next, the second block 11 (second microcomputer) proceeds to the chattering process of sixteen measurements, which are recorded in the last cell of the recording channel response. In this stack segment (RAM 28 SS segment) of the second block 11 (second microcomputer), the previous states of all 2 channels, which are initially rewritten from the RAM stack of the first block 10 (first micro computers), are selected and then selected channels. Bounce elimination is performed according to the following algorithm. The previous state of the channel and two subsequent states are considered, the value (1 or 0) that prevails in the three considered values is recorded in the current state of the channel. An explanation of the algorithm provides a numerical example. Let the following measurements be recorded;

A, A A A A A A A-yAgAqA oA ,, A ,, A, A ,, 00010110110 1 1 111

the previous state of this channel is equal to 0. The chattering is performed according to the following algorithm.

Consider the previous value (0) and the next two Ag (0,0,0) and write the current (converted measurement) 0. Then the obtained transformed measurement 0 is considered and two subsequent ones (A,) and in the current state again recorded O, Next consider the recorded current (0) and A2 OiAz O measurements, etc. in accordance with the table.

Next, the measurement sequence number is determined, after which the channel triggered, in this case No. 6. Since each subsequent measurement on the channel is lagging behind the time interval determined by the polling time of all channels (polling cycle), 1 c, then to determine the exact time triggered ten. to the channel, the number of measurements before triggering N 6 is multiplied by the value of t c (the time of the polling cycle) and the value of the first measurement in the group of 16 channels is added to the result obtained.

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+ Nt

Next, the second block 11 (the second microcomputer) provides information about the channel triggering (the exact response time T p, the channel number N, the new state of the channel, in this case 1) to the input of block 21.

The release of information is carried out 25 in the following order.

The value of the channel tcp trip time is entered into register 37 by the request of block 11 as an external device, the address of the address is decrypted on AND 36, the signal from which starts control block 38, which writes the contents of register 37 to shift register 39. According to the signals generated by the control unit 33, information from the register 39 arrives at the output device.

In the same way, all other information about channel triggering is output to the device. The following describes devices that perform auxiliary functions, i.e., Memory 14 is accessed from two blocks 10 and 11 (two microelectric computers), and these calls are decrypted on AND 12 and 19 elements, so the second priority comparison unit 16 is introduced, which distributes in time to the general memory block 14 from two blocks (a microcomputer) and controls the second driver 15 addresses. In this block, bus drivers 32.33 or 34.35 (FIGS. -5) are alternately opened, connected to the address (MA) and control (I-iy) bus of the address bus and control memory block 14 of one of the two blocks (micro computers) . To implement two-way communication between the blocks

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10 and 11 (microcomputer) two parallel interfaces 17 and 18 of type 580 BB55 are used. With the help of the registers A of these interfaces, two-way information is exchanged between blocks 10 and 11. To this end, in accordance with the work program of the computer 10

and 11, a mode II program is recorded in registers A of interfaces 17 and 8, providing two-way synchronous exchange between registers A of parallel programmable interfaces.

The registers B of the interfaces are designed to form interrupt vectors and, in accordance with the program of each microcomputer 10 and 11, a mode I program is written in them — a one-way synchronous write to register 13.

The operation of parallel-programmable interfaces 17 and 18 will be considered with reference to solving the problem of transferring the write address of memory block 14, which is stored in blocks 10 and 11. This write address is in register D1 of block 10 (first microcomputer), which is an additional segment (ES ).

This write address must be transferred to block 11 (second micro-computer) so that when reading information from the second memory block 14, the read address does not exceed the write address. Block 11 (the second microelectric computer), accessing AND 20 to the internal interface 18 device, writes the interrupt vector for its unit 10 (the first microcomputer) into its register. Block 10 (the first microcomputer) on this vector, which enters the VEC input to the interrupt request (input 1-1), interrupts the execution of its main channel search program and proceeds to the interrupt program. According to the interrupt program, the first microprocessor 5 writes the contents of register D1 to an external device, which is register A of interface 17. 1.

Since both registers A are programmed in mode II of operation, the information in registers A of interface 17 is written to register A of interface 18. Then block 10 (the first microcomputer) writes the interrupt vector for the block to register B of interface 17

11 (second microcomputer), on this interruption request, block 11 (second microcomputer) stops performing its

the main program and proceeds to the execution of the interrupt program. According to this program, block 11 (the second micro computer) polls register A of interface 18 and writes its contents into the microprocessor of the second micro computer.

A multichannel device for collecting information allows detecting the operation of any channel, approximating this operation, i.e. clear bounce, precisely tied to the time when this triggering occurred, and form an output sequential frame containing information about each triggering in any channel.

Claims (1)

Invention Formula A multi-channel information collection device comprising a pulse generator, a first AND element, the output of which is connected to the first input of the first priority comparison unit, a first memory block, a counter, the first input of which is the control input of the device, second, third and fourth elements Is it possible that, in order to increase the reliability of the received information, a multiplexer is entered into it, the first and second address generators, the second priority comparison unit, the first and second transmission control units, the first The second and second processing unit, the second storage unit, the fifth and sixth And elements, the first and second parallel interfaces, the multiplexer information inputs are device information inputs, the multiplexer output is connected to the information input of the first memory block, the outputs of which are combined with the corresponding the outputs of the first transmission control unit and are connected to the corresponding information inputs of the second memory block, the first parallel interface and the corresponding information inputs / output m of the first information processing unit and the first parallel interface, the output of the pulse generator is connected to the second inputs of the counter and the first priority comparison unit, the first and second outputs of the last are connected respectively to the first and second control inputs of the first address generator, the information outputs of the latter are connected to the corresponding targeted the inputs of the first memory block, the first, second and third control inputs of which are connected to the control outputs of the same name of the first address generator, the counter outputs are connected to the corresponding address inputs of the multiplexer, the first address inputs of the first address generator and the information inputs of the first transmission control block, address the inputs / outputs of the first information processing unit are connected to the corresponding address inputs of the second address driver and to the corresponding first inputs of the first fourth floor And elements, the second inputs of which are connected to the corresponding control outputs of the first information processing unit, the output of the second element And are connected to the control input of the first transmission control unit, the output of the third element And are connected to the first input of the second priority comparison unit, the first and second outputs which are connected to the same control inputs of the second address generator, the third control input of which is connected to the corresponding control output of the first processing unit information, the output of the fourth element I is connected to the control input of the first parallel interface, the outputs of the second memory block are connected to the corresponding information inputs-outputs of the second information processing unit, first information inputs-outputs and inputs of the second parallel interface, information inputs of the second transmission control unit, the output of which is the information output of the device, address inputs / outputs of the second information processing unit are connected to the corresponding second address the inputs of the second address generator, the address inputs of the second transmission control block, the first inputs of the P and the sixth elements AND, the second inputs of which are the fourth control the input of the second address generator and the control input of the second transmission control unit are connected to the corresponding control outputs of the second information processing unit; the output The fifth element I is connected to the second input of the second priority comparison unit, the output of the sixth element I is connected to the control input of the second parallel interface, the third outputs of the first and second priority comparison block are connected to the enable input of the first processing unit and setting the inputs of the operation mode of which are connected respectively to the first information output and to the corresponding second information outputs of the second parallel interface, the second inst ormatsionnye inputs and outputs of which are connected to the respective second informatsirnn1m inputs-outputs of the first block of the parallel interface, the first 2 of processing information. the information output and the second information outputs of which are connected respectively to the control input of the mode request and the corresponding setting inputs of the operation of the second information processing unit, the information outputs of the second address generator are connected to the corresponding address inputs of the second memory block whose control inputs are connected to the corresponding 5trav - to the leaking outputs of the second address driver, the setup inputs of the first and second information processing units are combined with the first input m counter, the fourth output of the second priority comparing unit connected to the enabling input of the second block obFig. 2 Fig l Thebes FIG. five WELL fU MS J J5 J5 57 39 Sbfxod FIG. 6 Record of the first Record that / south of the day of Chuvani Cfitaoa-m i a2.nala ... on.strutsgtpura. uHcfiof na uu In na.f j rrtui.