SU1633417A1 - Computer system - Google Patents

Abstract

The invention relates to computing and can be used in the construction of multi-machine and multiprocessor computing systems. The purpose of the invention is to simplify the organization of the computational process of debugging mathematical software. The goal is achieved in that the computing system on the system contains m computing devices 1, m local operational storage devices 2, system random access memory 5, device 6 modifications, arbiter 7, element AND 8, m elements OR 9, group of m elements AND 10. 1 zp f-ly, 3 ill.

Description

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The invention relates to computing and can be used in the construction of multi-machine and multiprocessor trunk computing systems.

The purpose of the invention is to simplify the organization of the computational process and debug the mathematical software

Fig. 1 is a computer system diagram, Fig. 2 is a diagram of a modification device, Fig. 3 is a diagram of a control unit of a modification device.

The computing system contains m computing devices 1. m local random access memory 2, the trunk 3 of the data address, the trunk 4 of the control, system random access memory 5, the device 6 modifications, the arbiter 7 of the trunk, the element AND 8. the elements OR 9, the elements AND 10 group, random access memory 11, information input-output 12 of the computing system, input 13 of the sign of the interruption of the computing system

The modification device 6 comprises a data transmission unit 14, an address register 15, a permanent memory unit 16, a decoder 17, a control unit 18, a control unit start input 19, outputs from the first to eighth control unit 20-27, a number register 28, a multiplexer 29 , elements And 30 groups, adder 31

The control block 18 contains a key 32 of the key (TgCl), a trigger trigger 33 (TgSap) the first element AND 34, the first element OR 35, the first to fourth elements AND-NOT 36 -39, the second element And 40, from the fifth to the tenth AND elements - NOT 41 -46, control trigger 47 (TiYnp), shift register 48, eleventh AND-NOT element 49, 50 clock pulse generator, input 51 of the logic unit, inputs 52 of the logic zero, second element OR 53, trigger 54 read-write (TYWR), crystal sampling trigger 55 (TrCS), first resolution trigger 56 (TrEZl), second resolution trigger 57 (TrE / 2), response trigger 58 (Trg)

The computing system works

After the power is turned on, all operational memories of the system are cleared, the computing devices 1 are monitored. Then, the interrupt signal from input 13 initiates the solution of tasks in computing devices 1 (DVR), which start to access the random access memory 11 (RAM), sending a request and receiving permission to seize the highway from the arbitrator 7 One of the DVR 1, the exciting trunk, reads the sign of the head DVM 1 from RAM 11, if it exists, becomes the head and performs a modification of this sign for this the same exchange cycle. It then turns to the system operative storage device (RAM 5) for analyzing the state of the external environment, depending on which it forms applications for solving problems and channeling them into RAM 11 of CVM 1, turning to RAM 11 and removing, that it is not the head, it goes to the cell of the order, chooses an order and modifies the cell. The next of CVM 1, referring to the same cell of the order of RAM 11, does not receive the same information and starts to solve the next priority task and so on

dynamic balancing of task distribution between digital computers 1 is provided

The system information of all DVR 1 is obtained from the system RAM 5 connected to external devices of the computer system via information input / output 12. For storing the current operational information, DVR 1 has internal RAM. For storing the copied information, local RAM 2 is used.

Information i and DVR 1 are recorded in the 1st local RAM 2 via the external trunk. All local RAM 2 have the same key address, therefore information from any DVR 1 is written to all local RAM 2, thus is copied. In this case, the information in one of the DVR 1 that produces the record will arrive only after the answers from all local RAM 2 to the AND elements 8 have coincided. Then it goes through the corresponding element OR

Oh, and having tried on the corresponding element AND 10 by the signal "The exchange enters the corresponding digital computer 1. This ensures that any of the digital signal 1 is ready to perform any task

5 The modification device 6, together with the RAM 11, functions as follows: By the route 3 of the data addresses, the first information input / output of the block 14 receives the address. The low bits of the address from its second information input / output go to the address register 5, where they are fixed by the leading edge of the signal. The exchange coming from trunk 4 The high-order key bits of the address are decoded by the decoder 17 and the trigger 33 of the control block 18 is set by the signal Exchange After the trigger signal on trigger 47 is linked to the frequency of the generator 50 shifts off the shift register 48. At the same time, trigger 32 is set, permitting the passage of signals "Input or" Output

0 than elements And 34 and 40 to form control signals

In the mode "Information output from the digital computer 1 on the trigger 54 an impulse is formed which ensures the recording of information in the RAM 1 1. On the trigger 55 an impulse is generated,

5 providing the operation of the RAM II In the RAM 11, produce a recording of the input data received. 3 devices 6 modifications

In the mode "Entering information from I s and-on t, crystal samples are generated twice. The first time with a high level (reading level) SIG HIM read a second time — with a low level of this sign (recording level). Information from RAM 1 I is recorded and stored until the end of the exchange in the register of the 28th day and is outputted from it to the block 14. Then it from the output of the adder 31 through the multipexor 29 is rewritten into the RAM 11. Depending on the bit of the address of the block 16 of the permanent memory, you can modify the information with the following information

In the case when the information is not modified on the information inputs of the second group of the adder 31, the information is issued, and the first particles of the messages And 30 receive single information. At the output of the 31, the code will register 28 numbers ia

In the case of arithmetic mapping on the first entrances of the cement I 10, other than typical information, the information inputs of the first group of the adder 51 is present, the information read in the register 28 is clean. On the information screen of the second group of adders 51, the constant is expired in the right direction. Add a new code. At output i of Jurassic II there will be a motifi | van || ЫИ ko1 k t) d) yi and pettipch-h-V1

1U 1b | IP SchSor 21 V 05kh- 11

In / from the ich of 1kaii from the bücka Ib constant to us in nt ipfma bottom second groups of SUM 1 iropa 5 | you tat to null information .1 to the second inputs, s - ements And 10 you are in the necessary bits in the necessary digits On a eummayur i

A CAT WILL APPEAR. YV IS TYATED. YuM software

Understand and register, my register is 28 to constant. This KOI is rewritten in O5V II

(reading and downloading of the exchange and i exchange, and that operation can not be anything to do (interrupted)

In this way, the information in all the legal O 2s is copied so as to allow: Yuboi DVM 1 to solve the tube problem ei without special training. This provides for a dynamic distribution of data

1ah by placing the won on iaj.ain in o iV 11 of which may be better

it but the reading of information and its data

Form w yuirstsnich

 The system of current computational devices of m current operative storage devices and this dark storage device are computed; the input of the system interrupt feature is i by reference to the interruptions of all cleaned devices of the first and second outputs of the i (r i i 1 tp) computations tite 1 about usg

0

five

The pockets are connected to the input and to the read input of the first operational storage device of the first and the second output, respectively, which are connected to the information of the new input and to the sign of the sign on the information of the i compute the information device. You are hot. of the system is pkkshchen to the first VKhUT of the data output of the system operational memory, I remember the neck of the device that is marked with the simplification of the computation of the network

In the process and in the debugging of the mathematical support, it (the operative memory storage device of the arbitrator magistrate, a group of m items and the output of AND and m of elements IL1 will hold the device and the outputs of the request for the resolution of the capture of the common bus of all

Titles and devices: output, arbitrator magistrates are interconnected with each other through the permission request information outputs of the output of all computing devices, outputs of the data header of all current random access memory devices (output i output i and therefore data systematically the operational storage device and the first information input device of the modification device are interconnected via the master of the addresses of the third outputs of all the technical devices of all the operating systems of the operating system. the trials of controlling the equalities of the system operational memory of the device and the devices of 1IPHI are connected between themselves by means of the mattress and the fourth output of the i subtraction of the first device is connected to the first one And the groups you move with which is applied to the input and the sign of the i-th quest is calculated by the computational set-up of the system's output from the system operative for commemorating the device to the first points of all the moments OR, the first output. The devices for modifying the technology to the second inlets of all cements OR the type of output ii io yukatno about the operational device is connected to the i in uu uj temena I and the outlet, which is connected to the third one in all the topics I, G1I output imem, and 1Ielects, and the third, all topics, I, G1I output, and the output, and 1I devices, and the third, all topics, I, G1I output, and the output, and 1I devices, and the third, all topics, I, G1I output, and the output, and 1I devices, which is connected to the third input of all topics I, G1I output, and the output, and 1I devices, which is connected to the third input of all topics, I, G1I output, and the output, and 1I devices, which is connected to the third input of all topics And, G1I output, and the output, and 1I devices, which is connected to the third input of all topics And, G1I output, and the output, and 1I devices, which is connected to the third input of all topics And, G1I output, and the output, and 1Iplicates, and the third input of all the topics To the second input of the technical condition of the ith element of the second and third and fourth outputs of the device for the verification, respectively, are connected to the input of the input and recording and the accessory input promptly, on the memory of the device, an information input of which is connected to the information input OUTPUT oystva modification

0

0

five

0

2 (system in accordance with claim 1 from the fact that the device for modifying the transmission of the secret transmissions of the secret module to the permanent memory memory adder is a texttexter riistor aipeca reg indicator of the number of the genus rights and the encoder

7

and a group of elements And, the first information input-output of the device is connected to the first information input-output of the data transmission unit, the second information input-output of which is connected to the output of the number register, to the first information input of the multiplexer, to the first inputs of the elements of the AND group, to the information the input of the address register and the input of the decoder, the output of which is connected to the start input of the control unit, the second information input-output device is connected to the output of the multiplexer and to the information input re istra number control input device connected to the input mode of the control unit, the first to seventh outputs of which are connected with the responsibility to the control input of the data block to the input of recording-reading

one;

The address register, to the first, second, third device outputs, to the write-read input of the number register and to the multiplexer enable input, the output of the address register is connected to the fourth output of the device and to the address input of the permanent memory unit, the outputs of the first group of which are connected respectively to the second inputs of elements AND of the group, the outputs of which are connected to the information inputs of the first group of the adder, the information inputs of the second group of which are connected respectively to the outputs of the second group of the fixed memory block and the adder output is connected to the second information input of the multiplexer, the eight output control unit is connected to the input register number and authorization to the control input of the multiplexer.

FIG I

Claims (2)

Claim 1. A computing system containing a point of computing devices, m local random access memory and system memory, and the input of the interrupt sign of the system is connected to the interrupt inputs of all computing devices, the first and second outputs of the ith (where 1 = 1 ..... r) the computing device is connected respectively to the address input and to the reading input of its local random access memory, the first and second outputs of which are connected respectively to the information input and to the input sign and the availability of information of an i-ro computing device, the information input-output of the system is connected to the first input address output of the system random access memory, characterized in that, in order to simplify the organization of the computing process and debug mathematical software, it contains a modification device, random access memory , a line arbiter, a group of m AND elements, an AND element and m OR elements, the inputs and outputs of the request-permission to capture the common bus of all computing devices and inputs the arbiter d-output of the line are interconnected via the request-permission highway, information inputs and outputs of all computing devices, input and output addresses of the data address of all local random access memory devices, the second input and output of the data address of the system random access memory device and the first information input output of the device modifications are interconnected via the data-address highway. the third outputs of all computing devices, the recording inputs of all local random access memory devices, the control inputs of the system random access memory and the modification device are interconnected via a control line, the fourth output of the i-th computing device is connected to the first input of the i-ro element of the C group, the output of which connected to the input of the sign of receiving the task of the ι-th computing device, the output of the system random access memory is connected to the first inputs of all the element in OR, the first output of the modification device is connected to the second inputs of all OR elements, the third output of the i-th local random access memory is connected to the i-th input of the AND element, the output of which is connected to the third inputs of all OR elements, the output of the i-ro OR element is connected to the second input of the i-ro element I. the second, third and fourth outputs of the modification device are connected respectively to the read input, write input and address input of random access memory, the information input-output of which is connected to information nnomu input-output device modifications. 2. The system by π. 1, characterized in that the modification device comprises a data transmission unit, a read-only memory unit, an adder, a multiplexer, an address register, a number register, a control unit, a decoder 1633417 'and a group of AND elements, the first information input-output of the device connected to the first information input of the data transmission unit, the second information input-output of which is connected to the output of the number register, to the first information input of the multiplexer, to the first inputs of the elements of the And group, to the information the input of the address register and the input of the decoder, the output of which is connected to the start input of the control unit, the second information input-output device is connected to the output of the multiplexer and to the information input istra number, the control input device connected to the input mode of the control unit, the outputs of the first to seventh responsibility of which are connected with the control input to the data transmission unit to the input of recording and reading 8 of the address register, to the first, second, third outputs of the device, to the write-read input of the number register and to the resolution input of the multiplexer, the output of the address register is connected to the fourth output of the device and to the address input of the read-only memory, the outputs of the first group of which are connected respectively to the second inputs elements And groups, the outputs of which are connected to the information inputs 10 of the first group of the adder, the information inputs of the second group of which are connected respectively to the outputs of the second group of the permanent memory block , the adder output is connected to the second information input _{15 of the} multiplexer, the eighth output of the control unit is connected to the enable input of the number register and to the control input of the multiplexer. ΨΨ FIG. g