SU934464A1 - Multiplexor channel - Google Patents

Description

(54) MULTIPLEX CHANNEL

I

The invention relates to computing technology, is designed to exchange information between the main memory and external devices, and allows the processor to perform operations of the main program simultaneously with the execution of the input-output operation.

I / O channels are known that contain a control block, an operation and features code block, a subchannel block, a data block, an interrupt block and a communication block with external devices fl. “1: 2.

The disadvantage of these channels is the low performance of the channels in the selector mode due to their occupation with command chains during the execution of operations associated with mechanical movements in I / O devices.

A multiplex channel, a saddle selector subchannel, a command issuing unit, and a junction block are also known.

with RAM and central processor 3.

A disadvantage of the known channel when working with selector subchannels is a decrease in its performance with command chains when only one device is connected to the channel. The absence of a block of separation commands does not allow productive use of the channel

10 commands that only take an external device to run for a long time.

The closest to the proposed technical entity are I / O channels containing a channel control block, a current data address register and a data counter register forming a data block, a communication block with an interface, an operation code and pointer block, and a subchannel block G4 | .

The disadvantage of these channels when operating in the selector mode is that the once-running peripheral device, when executing the command chains, occupies the channel for the entire duration of the channel program, i.e., does not release the channel for the duration of the mechanical movements that take a significant amount of time. The purpose of the invention is to improve speed. The goal is achieved by the fact that a multiplex channel containing a control unit, a memory unit, a first register unit, a interface unit, a second register unit, a register, the control unit being connected to the first two-way communication with the first output output of the device, the second two-way communication to the memory unit, the third two-way communication with the first block of registers, which is two-way communication connected to the interface unit, which is two-way communication connected to the second input of the device, the first output of the connection interface With the first input of the memory unit, the first output of the control unit is connected to the first input of the second register block, the output of which is connected to the first input of the interface unit and to the second input of the memory unit, the first output of the control unit is connected to the first input of the register, the output of which is connected To the first input of the control unit, a command analysis block is additionally introduced, the first input of which is connected to the second output of the second register block, the second input is connected to the second output of the interface block, the first output of the analysis block to A command is connected to the second input of the interface unit, and the second output is connected to the second input of the register. Moreover, the command analysis block contains the first and second OR elements, the AND element and the trigger, with the first one; the trigger output is connected to the second block input, the second output is connected to the first block output, the first input of which is connected to the inputs of the first OR element, the second input of the AND element and the first input of the second OR element, the second input of which is connected to the second input of the block, and the output to the second input of the trigger, the first input of which is connected by the ci output of the AND element, the first input of which is connected to the output of the first element OR FIG. 1 shows a block diagram of a multiplex I / O channel; in fig. 2 - functional block diagram analysis commands. The multiplex channel contains a control unit 1, a memory unit 2, a first register unit 3, an interface unit 4, a second register unit 5, a register 6, and a command analysis unit 7. The command analysis block contains two OR elements. 8 and 9, element 10 and trigger 11. In the multiplex channel (Fig. 1), control unit 1 is connected by a first two-way communication with a first input / output, second two-way communication with a memory unit 2, and a third two-way communication with the first unit 3 registers, which are connected by two-way communication to the interface 4, which are connected by two-way communication to the second input-output of the device, the first output of which is connected to the first input of memory 2, the first output of control 1 is connected to the first input of the second unit 5 registers, first exit which is connected to the first input of the interface 4 and to the second input of the memory 2, the first output of the control unit 1 is connected to the first input of the register 6, the output of which is connected to the first input of the control unit 1, and the second input is connected to the second output of the 7 analysis of commands, the first output of which is connected to the second input of block 4, the first input of block 7 of command analysis is connected to the second output of the second block 5 of registers, and its second input is connected to the second output of block 4. In the command analysis block (Fig. 2), the inputs of the first element OR 8 are connected to the corresponding second outputs of the second register block 5, and the output is connected to the first input of the AND 1O element, the second input of which is connected to the corresponding output of the second register 5 block, the output of the AND 1O element connected to the setup input of the trigger 11, the first output of which is connected to the second input of the 4th interface unit, and the second output is connected to the second input of the register 6, the first input of the second element OR 9 is connected to the corresponding second output of the second unit 5 regis The second input is connected to the corresponding second output of the conjugation unit 4, and the output is connected to the reset input of the trigger 11. The control unit 1 is designed to receive input-output commands from the central processor, check the correctness of the control word and coordinate the operation of other channel blocks when execution of I / O commands and contains registers for receiving a command, a scheme for checking the correctness of a command word, a scheme for initial sampling of a device, a communication circuit with a random access memory for data exchange, and a control circuit for other devices kami. The memory unit 2 is designed to receive, store the completion of work on executing an I / O command and to form an interrupt under the following conditions: at the end of the channel, the end of the controller, the end of the WU and Attention. If there is a chain of interrupt commands, the following reasons are also given: faults in the device, a special case in the device is in use, an error in the program, a violation of the memory protection and a program-controlled interrupt in the channel command word. The block also generates channel state and device bytes for storing new information in the 64th main memory cell. The block contains the byte registers of the channel and device status, the scheme for receiving and extracting the status bytes, and the scheme for generating and issuing interrupts. The first block 3 of registers is intended for the exchange of information between I / O devices and RAM and counting the amount of information transmitted. It contains registers for receiving and issuing data, registers for storing the current value of the address and counter of transmitted bytes, a control circuit for receiving and transmitting data and a circuit for generating interchange memory requests. Interface unit 4 is designed to transmit and receive control and data signals through the interface and terminate operation when executing I / O commands. Normally, an I / O command ends when the device receives a CHANNEL END signal, if until that moment the channel does not detect a hardware failure or the operation is not terminated with the FREE I / O, STOP I / O, and STOP DEVICE commands. - The block contains a subscriber identifier register, a channel identifier register, a circuit for issuing a stop signal to the device by releasing INPUT-OUTPUT, 1N1: enter and STOP DEVICE, and the termination circuit with the device. The subscriber identifier register is used to receive control and special signals (the operation of the subscriber channel RAB-A, the address from the subscriber is ADR-A, the control from the subscriber is UPR-A, the information from the subscriber is INF-A, the return sample is VBR-A , data from subscriber DAN-A, subscriber requirement - TRB-A, subscriber disconnection - OTK-A), the Channel Identifier Register is used to transmit control and special signals (operation of the RAB-K channel, sampling - VBR-4, address from the channel - ADR-K, control from the UPR-K channel, information from the INF-K channel, data from the channel - DAN-K, blocks The second block of registers is intended for receiving, decoding a command code, storing a command, and also for receiving and storing pointers, a data chain, a chain of commands, a length lock, a write lock with a program-controlled interrupt, the Block contains command register, decipher and pointer register. The register 6 5 is written in the sub-channel register and is used to store control information for each operating device AND the data address of the control information state counter for each command s vvodavyvoda. It contains a subchannel memory and circuits for fetching and rewriting the control word of the device. By the channel number and the address of the operating device, at the initiative of the channel or at the request of the subscriber, the sampling and rewriting schemes search for the device control word in the memory and read it into channel registers for processing. the corrections of the control word are written back to the memory. The operation of blocks 1-6 of input and output channels is completely; it corresponds to the work of known input-output channels. The command analysis block 7 is used to improve the speed of the channel in selector mode when executing a bunch of commands and is revealed using the example of working with such high-speed devices as disks and magnetic tapes that require the selector mode of the channels. Usually, one device running in the selector mode takes the channel for the entire duration of the channel program execution. A channel program is one or several channel commands intended for their sequential execution. You can start the device after processing the channel program. To work with disks, use the INSTALL commands (command code 07) and PA RAIL INSTALLATIONS (command code O8), which after the byte of the status with the sign do not require any operations with the channel, i.e. during the execution time of these commands may be free to work with other input device devices. The execution time of these commands for different types of disks varies in the range of 8–13 O ms. Since almost every disk access is a chain of commands, starting with commands 07 or 08, the question arises about the radial use of this time. To work with a magnetic tape, use the ROTATING command (command code 07), RETURN and UNLOADING (command code OF), which, if necessary, include them in the coma chain, they can release the channel and the control device of the magnetic tape for up to 150s. The command analysis block is designed to release a channel operating in selector mode by the above commands when executing chains of commands after receiving a status byte with the CHANNEL FINISH sign, since the further execution of these commands does not require the equipment of the channel. This is achieved by resetting the channel of the BLOCK-BLK-K interface signal, the presence of which when receiving the status byte is an indication of the chain of commands for the device. Commands 07, OB, and OF from a chain of commands execute $ pots to a device without specifying a command chain attribute: they divide the operation of the channel and devices after the arrival of the status byte with the CHANNEL END sign. The call is released for working with other devices, and all the current information is needed is recorded in the subchannel. The multiplex channel containing the block of the analysis of commands works as follows. The processor program starts I / O operations with the BEGIN IN / OUT command. The command BEGIN INPUT gets block 1 control. This command specifies the channel and device and forces the channel to select the channel address word from a fixed main memory cell. The channel address word contains the security key and indicates the main memory location from which the channel selects the junction command channel word. The channel command word contains the command code to be executed and, if necessary, the area of the main memory to be used. The channel command in control block 1 is checked for validity. The command code and operation pointers are received in the second register block 5 for fixing. Dedicated commands O7, ОВ and OF from the board}) of the opcode of the operation code arrive at the inputs of the first element OR 8. If any of these commands are present, the output signal goes to the element 10, pr the presence of the instruction chain indicator (10) at the second input of the element 10 From the second register block 5, the output signal sets in one state a trigger 11, the first output of which goes to the channel identifier register in mate 4 to reset the BLK-K signal, and the second output goes to register 6. The channel attempts to dial the specified external device, send hell ec of the device through the interface unit 4 to all controllers connected to this channel. The controller that recognized the address is logically connected to the channel through the interface 4 and responds to the channel selection by sending the address of the selected device. Then the second block 5 of registers sends a command code to the device through block 4 of the conjugation. The device responds with a status byte with the CHANNEL-FINISH flag for commands 07, OB, and OF. Since the BLK-K signal is cleared, the device does not receive the indication of a chain of commands. The signal is terminated through memory block 2 and control block 1. enters the register 6 on the sampling schemes of rewriting the control word of the device. If there is a gfan in block 7, anag: signal command command, MUSIC STORAGE, CHANNEL QBijPOC. The device control word is written to the subchannel and the channel is reset, as is done in the multiplexed channel mode. The channel is free and can be productively used to work with other devices. When the device has finished mechanical movements, it will signal the KOHEU OPERATION signal of the device. The status byte with the END OF DEVICE feature is output to the channel at the request of the subscriber (TRB-A). The TRB-A signal from the re: gistra of subscriber identifiers of the block 4 of the interface from this device or from any other previously launched device enters the input of the element OR 9, which resets the trigger 11 To the second input of the element OR 9 the signal enters the CSC, which is processed in the second block 5 of registers upon receipt from the processor in block 1 of the control. START INPUT / OUTPUT commands, and flushes trigger 11. The technical and economic advantages of the proposed I / O channel, as compared with the known ones, are that the introduction of this block to increase the performance of the channels in selector mode, which was not previously known in input channels - output allows the channel, when executing certain commands in a chain of commands, to release the channel for productive work with other devices while the previously launched devices will work in offline mode Implementation commands not associated with data transmission.

Claims (4)

1. A multiplex channel containing a control unit, a memory unit, a first register unit, a interface unit, a second register unit, a register, wherein the control unit is connected by a first two-way communication with a first input-output device, a second two-way communication with a memory unit In this case, the third two-way communication with the first block of registers, which is connected by two-way communication to the interface unit, which is connected to the second input-output of the device by two-way communication, the first output of the interface unit is connected to the first memory input, the first the output of the control unit is connected to the first input of the second register unit, the output of which is connected to the first input of the interface unit and to the second run of the memory unit; the first output of the control unit is connected to the first input of the register, the output of which is connected to the first input of the control unit, what, with the channel speed circuit, into it a command analysis block is entered, the first input of which is connected to the second output of the second register block, the second input is connected to the second output of the interface block, the first output of the code analysis block the mand is connected to the second input of the interface block, and the second output to the second input of the register. 2. Channel pop. 1, differs in that the command analysis block contains the first and second OR elements, the AND element and the trigger, with the first trigger output connected to the second output of the block, the second output to the first output of the block, the first input of which is connected to. the inputs of the first element OR, the second input of the AND element and the first input of the second element OR, the second input of which is connected to the second input of the block and the output to the BTOpoNjy trigger input, the first input of which is connected to the output of the element And, the first input to the expensive connected to the output of the first element OR. Information sources, taken into account in the examination 1. Kattsan G. VychisdLtelye machines of the system 37O.-M., Mir, 1974. 2. USSR author's certificate number 525941, cl. bb F 3/04, 1976. 3. Mayorov S. A.. Novikov G. And .. Principles of organization of 1-block machines. Leningrad Association, Mechanical Engineering, 1974. 4. Kagan V.M., Kanevsky M.M. Digital computers and systems. M., Energie, 1973 (prototype). : i  f Vv, NJ