SU1596332A1 - Device for checking computing process of electronic computer - Google Patents

Abstract

The invention relates to computing and can be used in the construction of computing systems, for example, in automated process control systems. The aim of the invention is to expand the functionality of the device by controlling the access to the stack memory and its state at various priority levels. A device for controlling a computational process of a computer contains an interface unit, an operating highway, a priority register, a generator, a control element AND and M control units, each of which includes a time control node, two OR-NOT elements, two triggers, a delay element, three elements And, the main element, the reversible counter, the element AND-NOT, the first and second elements are NOT, the element OR, the first and second drivers. 4 il.

Description

The invention relates to computing and can be used in the construction of computing systems, for example, in automated process control systems.

The purpose of the invention is to expand the functionality of the device by providing control of access to the stack memory and its state at various priority levels.

FIG. 1 shows a functional diagram of the device for controlling the computing process of a computer; in fig. 2-funnel interface block; in fig. 3 diagram of the time control node, an example of execution; in fig. 4 is a functional circuit diagram of the interrupt generation unit.

A device for controlling the computing process of a computer contains (Fig. 1) a processor 1. RAM 2, communication devices with an object (USO) 3. Interface block 4, system (operational) highway 5, priority register 6, pulse generator 7, control unit the element AND 8 and M blocks 9 control, each of which includes the node lOi control time, the element OR NONE 11, the first trigger 12. the delay element 13, the first and second elements 14 and 15, the element AND NOT 16, the main element 17 , reversible counter 18, the second element OR NOT 19, the first element NOT 20, the third element AND 21, the element LEE 22, first and second formers 23 and 24, the second flip-flop 25 and a second NOT member 26.

Interface unit 4 (FIG. 2) includes first, second, and third trunk elements 27-29. the address selector 30, element or 31, the first element is NOT 32, the first.

the second, third and sixth elements OR-NOT 33-36, the tenth, eighth and ninth elements are NOT 37-39, the comparison circuit 40, the second, seventh, sixth, fifth, fourth, third elements are NOT 41-46, the seventh element ORIN E 47, the first element AND-E 48, trigger 49, the fourth element OR-NOT 50, interrupt-forming node 51, register 52, the twelfth and eleventh elements 53 and 54, the second element AND-71 55, the fifth element OR -NOT 56 and internal highway 57.

The time control node 10 (Fig. 3) contains the first, second, third AND-NE elements 58-60, the first and second elements AND 61 and 62, trigger 63, the counter 64 of the priority level, the counter 65 of the program time, the counter 66 of the time spent subprogrammes and register 67.

The interrupt forming node 51 (FIG. 4) constitutes a buffer element 68, first, second, third, fourth triggers 69-72, first and second elements AND 73 and 74, first and second AND-NE elements 75 and 76, first, second and the third elements are HE 77-79 and the interrupt vector register 80.

In real-time systems, such as control systems for multi-axis process devices, multi-channel measurement and control systems, there are a large number of functional tasks. When performing various tasks, a part of the operational memory — the stack — is used to store the necessary information when organizing nested procedures: calling a subroutine and returning from it; transfer control to the interrupt handler and return control to the interrupted program. The stack is also used for temporary storage of work variables of tasks, but it is necessary to ensure that its contents at the end of the task coincide with the initial, i.e. All the data that the task has written to the stack must be read from the stack by the time the task is completed.

In branched programs, errors are possible in which the number of variables written to the stack is not equal to the number read (for example, because of an error in conditional statements, the branch in which data was put on the stack but the program branch did not execute read from the stack). This can lead to system failure (program malfunction). The lack of operational control of the stack state makes it difficult to find such errors. Particularly difficult is finding and fixing errors in systems with absolute priorities of tasks.

Let, for example, the priorities of tasks be relative and one of the tasks (task A), which periodically executes, writes to the stack one more word than it reads from the stack. Bye in

the stack will have enough free space; this does not affect the correctness of other tasks. However, since a limited memory area is allocated for the stack, after several launches of task A, less free cells will remain in the stack than are required to store variables of another task (task B). Therefore, when performing task B, a stack overflow occurs. The stack overflow in many computers is fixed by the built-in control devices and, therefore, the error made in developing task A is performed during the execution of the correct task B. The stack overflow indicates the nature

errors, but the task in which this error was made is unknown, and for debugging it is necessary to analyze all the tasks of the system.

Debugging a system with Absolute Priorities is complicated by the fact that even a one-time start of an incorrectly programmed task A can lead to errors in calculations in tasks of lower priority.

Consider a situation that generates errors step by step.

1. Let task B be carried out and let after tego, as task B, write working variable X to the stack, its execution is interrupted by higher priority task A.

2. While task A is on the stack, it is one more variable than read, i.e. after completing the task in

ve The stack bus is variable Y.

3. Problem B continues his work and reads the contents of the stack. Instead of the variable X written to the stack, the other variable is read, Y, which leads to an error in the calculation. Such an error can only occur when using the final result of the system, as it is not monitored by hardware. But even if it appears immediately (for example, in

as an abnormal release of a controlled indication), it is usually perceived as an accidental failure, since it is not possible to make any assumptions about the cause of the error,

Indeed, task A and task B work autonomously correctly. Due to the asynchronous processes of processes A and B, a failed situation can occur rarely and without any regularity.

The essence of the invention is to expand the capabilities of the device by ensuring that not only the upper and lower boundaries of the stack are monitored, but also its state is checked after each task has been completed.

To do this, during the execution of the task, the difference between the number of reads from the stack and the entries in the stack is calculated. At the completion of the task, this difference should be zero. Since systems with absolute priorities can simultaneously perform several tasks, several hardware counters, the number of which is equal to the number of priority levels, are used to calculate these differences.

A device for controlling the computing process of the computer works as follows.

The device includes a processor 1 for executing 2 programs stored in RAM. During operation, processor 1 exchanges information with RAM 2 and USO 3 via interface bus 5. USO are the controllers of external devices.

The sequence of placing addresses, data and control signals on buses of the bus is the same for all devices connected to it, therefore, the external device registers are assigned certain addresses in the address space and exchanging with them at the processor's initiative is similar to accessing RAM cells.

The execution of functional tasks by the processor takes place under the control of a special set of programs - the operating system (OS). Functional tasks can be in one of three states: passive, when the task is not required to be performed; an idle state in which a task is required, but the processor is busy performing a task or interrupt processing; active, in which the task is performed by the processor.

When a processor is released after completing a task, it calls on the OS and selects the most priority of the tasks in the pending state for execution. Before performing the task of the 1st priority, the reversible counter 18i is checked for equality to zero, in which, when the task of the 1st priority is accumulated, the difference between the numbers of entries and reads from the stack is accumulated. If the equality to zero condition is not met, a vector interrupt occurs. Stack error. The state of counter 18i is monitored through element 17 | and may be adjusted. With each

writing B, the stack at summing input of counter 18i, corresponding to the current priority I, appears level 1, and with each reading from the stack, level 1 appears at the subtracting input of counter 18i.

Consider the operation of the device in more detail. When the power is turned on, the signal at the seventh output of block 4, level O, resets the contents of all reversing counters 18 to level O, and level O at the eleventh output prepares all triggers 25 for operation. , and the level O at the input of the control element And 8 prohibits the passage of pulses from generator 7. The program manager selects the highest priority from the task queue (for example, the 1st priority) and writes the corresponding code to the priority register 6. Recording is gated, as in a known device, by switching from Level O to Level 1 at the tenth output of the interface 4. At the outputs of the priority register 6, an i-ro priority code appears, which permits the recording of the first priority time for all tasks of the i-ro priority and the initial time code of the first executable program i ro priority. The entry of the code is gated by passing from the level O to the level 1 from the sixth output of the block 4 of the interface. After the transfers are completed, the level 1 at the first output of the interface 4 allows the pulses from the generator 7 to pass through the control element AND 8 to the enabling input of the node 10 controlling the time of the 1st priority. If the full program calls the subroutine, then in the time control node 10, the i-ro priority is entered with the initial code corresponding to this program. Recording is gated by the transition from level O to level 1 from the sixth output of the 4-gate block. Upon transfer of control to the subroutine, a level 1 impulse appears at the third output of the interface 4. Upon completion of the subprogram completion, a level 1 impulse appears at the fourth output of the interface 4. The control status code of node 10 of the time control of the 1st priority is fed to the information input of the interface 4 according to the level 1 signal at the second output of the interface 4.

If during the i-ro priority task, a request came from a higher, (1-1) -th, priority task, the i-ro processing time code for all i-th priority tasks is reset, and the time codes for the execution of the executed program and the time for the execution of the executed subroutine remain unchanged. After returning to the 1st priority task, the time count continues.

When the task 1 is addressed (priority to the stack with level O from the eighth output 4 mate, trigger 12 of control unit 9 of the first priority is activated. Level 1 is set at the inputs of the first and second elements 14 and 15. When writing to the stack, level 1 is set at the sixth output of the 4th interface unit and through the input of the first element I14, the summing input of the reversing counter 18 enters, simultaneously flushing the trigger 12 via the first OR-NOT element 11. When reading from the stack, level 0 at the eighth output of the 4th conjunction block again triggers 14 which level In it, 1 opens the second element And 15. Level 1 from the ninth output of block 4 of the interface through the input of the second element And 15 enters the subtractive input of the reversible counter 18 of the control block of the 1st priority.

If a standard OS is used in the computing system and there is no possibility to make changes to it, then in the task being performed, before the command to return to the OS (in many OS, this operation is called EXIT), it is necessary to programmatically set the zero priority in the priority register B. Moreover, if on the information output of the reversible counter 18, the code is not zero, then one input of the third element And 21 sets level 1. The signal from the first output of register 6 of priority level 1 through the third element And 21 goes to one input of element OR 22, so as level 1 at the input of the third element And 21

at this time, delay element 13 is supported. Next, the level 1 from the output of the OR element 22 enters the interrupt input of the conjugation block 4 and resolves the interrupt according to the vector Stack error.

If it is possible to modify the OS programs, in the computing system, the stack is checked by the OS after the completion of each task.

If during the writing to the stack the lower bound of the stack occurs, level 1 appears at the overflow output of the reversible counter 18i and through the pulse shaper 23 through the OR 22 element enters the interrupt input of the interface 4.

When reading from the stack, the transition of the upper stack limit sets the level G at the output of the loan of the ISi reversible counter. and through the pulse shaper 24 and the element OR 22 is fed to the interrupt input

4.Supprocessor block, allowing interrupt by vector. Stack error.

If an erroneous situation is detected, the task is to be corrected; the error signal is turned to the stack from the output of the element OR 22 and the level 1 pulse also goes through the second element NOT 26 to the S input of the second trigger 25. As a result, the output of the second

the trigger is set to level 1, which is fed to the input of the trunk element 17, indicating in which task of priority the error of accessing the stack occurred. When reading the state of the counter 18i

in the priority register, it is necessary to set the 1st priority code, the D level on the fifth and ninth outputs of the interface block 4, on the output of the IED 16 element, the O level, which opens

element 17. The code from the information output of the reversible counter 18 and the output of the second trigger 25 is fed to the information inputs of the main element 17, the output of which is connected to

operating line 5. To correct counter 18i, the required number of cycles is Read or Write to the stack. After this operation, the signal O from the eleventh output of block 4 of the pair must reset the second trigger 25i.

Consider according to the scheme shown in FIG. 2, the operation of unit 4 mate. Unit 4 mates allows you to connect unit 9

control to the operating highway 5 and supports its operation using standard external device access cycles. Consider the generation of control signals of control unit 9.

npi power on under the control of the monitor program is preparing the device for operation. The address selector 30 from the first output issues an address AO with the level O, which is fed to the input of the first element OR-NOT 33. The input to the other input of the first element OR-NOT 33 is output N output by the level O. The signal obtained in this way from the output of the first element OR -NON 33, level 1 arrives at the first input of the interrupt-forming unit 51, preparing it for operation. Level O at the control input of the first trunk element 27 allows passage of the start address of the stack to the input of register 52

(bits D5 -D15), and level 1 at the control input of register 52 gates its entry. Level O from the output of the first element. The HE 32 is fed to the seventh output of the 4th interface unit and to the input of the second element NAND 55 and forms the level O through the NOT 54 element at the eleventh output of the 4th interface unit.

The formation of the signal of the prohibition of pulses from the generator 7 occurs as follows. At the second output of the address selector 30, the address A1 signal appears, which is fed to the input of the second element OR-NOT 34 by the level O, the other input of which is connected to the signal line. Output H is level O. The resultant signal from the output of the second element OR-NOT 34 is through the element The HE 42 sets the level O on the go-go of the trigger 49. The trigger 49 is energized, and from the inverse output the level O is set on the first output of the 4th interface unit.

The recording of the initial time code of all tasks of the 1st priority, the initial time code of the Nth task of its priority and the initial code of the time of the 1st priority subroutine to the time control node 10 is gated with a signal Output N. The N level N is connected to the sixth output block 4 mates through the element NOT 46.

Writing to priority register 6 is carried out by the signals Address AB and Output N. The address selector 30 sets the sixth output level O, which is fed to the input of the fourth element OR NOT 50. whose other input is connected to the line Output H level O. The resultant signal sets the level 1 at the tenth output of block 4;

The monitoring of program execution time is carried out as follows. The write to the register 67 of the control word of the time control node 10 is performed by the signals Address Aa and Output. At the third output of the address selector 30 and the input of the third element OR NOT 35, the level O is set. Another input of the third element OR NOT 35 is connected to the line Output H of the level O. The resultant signal from the output of the third element OR NOT 35 sets the second output of block 4 interface level 1. The controlled code from the time control node 10 enters the information input of the interface 4 and the input of the third main element 29. The readout of the control code is performed by the signals Address Aa and Input N. The level O from the third output of the selector 30 a Dresa is fed to the input of the sixth element OR-HO 36. whose other input is connected to the line O. Level input. The total signal from the output of the OR-NOT 36 element through the element NO 37 is fed to the control input of the element 29. sets the level O. The input of the third main

element 29 is connected to its output and, respectively, to the inputs-outputs of the block 4 of the conjugation.

The reset of the trigger.45 is performed by the signals AG address and Input N. The second output of the selector 30 of the address and the input of the element OR NOT 47 is set to level O. Another input of the element OR NOT 47 is connected to the input line H of level A. The resultant signal from the output of the element OR-NOT 47 through the element NOT 43 sets the level O at the R input of the flip-flop 49. At the inverse output of the flip-flop 49 and the first output of the interface 4, level 1 is set.

Consider the pattern of signal generation for accessing the stack. When writing to the stack at the input of the second trunk element 28, the stack address is set. C signal

the lines are outputted by the level O through the element OR 31 and are fed to the control input of the element 28. The input is connected to the output of the second main element 28. and the signal is fed to the second input of the comparison circuit 40. If the codes on the first and second inputs of the circuit are equal, the comparison level 40 is set to output level 1. Signal Output H from the output of the element OR 31 through the element NOT 41 sets the level

 1 at the input of the first element AND-E 48. When the signals coincide, level 1 at the first and second inputs of the first element IS-NOT 48 at the eighth output of the comparison unit is set to level O. When reading from the stack, the second trunk element 28 and the first element AND-NOT 48 is opened by a signal from the H input line in the same way.

Line Input H level O is connected, to the ninth output of block 4 of the conjugation through the element NE-45. The output of which is also connected to the second input of the interrupt generating unit 51.

To read the state of the reversible counter 18, the Address signal is used.

AO. To read the code from the first exit of the counter 18 | the signal from the first output of the selector 30 of the address through the element HE 44 sets the level 1 at the fifth output of the 4-terminal block.

For monitoring the execution time of the subroutine, the signals Address A and Address A4 are used. When referring to the subroutine, the signal Address Az sets through the element NOT 38 at the third output of the block

4.control level 1. At the end of the subprogram, the signal Address A4 sets the NOT 39 element at the fourth output of interface 4 to the level G.

Interrupt generating node 51 generates a stack error and a sequence of SIPN and TPRN signals at occurrence of level 1 at the interrupt input of interface 4.

To reset the second trigger 25, the signals Address Address Ab and signal Output H are used. From the seventh output of the selector 30, the address level O arrives at the input of the element OR-NOT 56, at the other input of which the level O is set from the line Output N. The signal from the output of the element OR NOT 56 through the element NO 53, the element IS-NOT 55 and the element NOT 54 sets the level O to one of the eleventh outputs of the 4-terminal block.

Consider according to the scheme shown in FIG. 3, the operation of time control node 10 (for example, priority 1). Level 1 at the information input of node 10 of time control is a sign of the 1st priority and opens the first, second and third elements of IS-NE 58-60 and the first element AND 61. Writing the initial time code to counters 64-66 from the group of inputs of node 10 The gate is output by G, which generates a differential from level 1 to level O at the clock inputs of the counters.

The signal from generator 7 is fed to the subtractive inputs of counters 64 and 65 through the first element 61 and 61. When addressing the subroutine, the signal Address Az through the second element AND-NOT 59 cocks the trigger 63. At the output of the trigger 63 a level 1 is set, allowing the pulses to pass from the first element I 61 to the input of counter 66. Upon completion of the subprogram, the signal Address A through the third element IS-NOT 60 sets the level O at the second input of the trigger 63. At the output of the trigger 63 vt the second input of the second element I 62 sets the level O that closes it. The recording in register 67 is gated with a level 1 signal from the enable input of the time control node 10.

Consider the operation of the interrupt-forming unit 51 (FIG. 4). The level at the first input of the interrupt-forming unit 51 charges the second trigger 70. Accordingly, the level 1 is set at the second input of the first element AND 73. The stack error signal is fed by the third input of the forming unit 51 interrupts and to the input of the first eleTlent NOT 77. Level O at the first input of the first trigger 69 cocks it. Level 1 from the output of the first trigger 69 is fed to the first input of the first element And 73. Accordingly, the third trigger 71 is activated, allowing the level of OTRN to pass through the level O to the third output of the interrupt-forming node 51;

Witnesses. .Processor 1, having received the TPRN signal via the operational highway 5, produces the Input H and PRD-1N signals, which are fed to the inputs of node 51. The Input H signal

the level difference O to level 1 sets the first output of the fourth trigger 72 to level 1, and the second sets the level O. The signal SPR-1H through the second element HE78 establishes the level 1 on the first

0 and the second inputs, respectively, of the second element AND-NOT 76 and the second element AND 74. The signal from the output of the second element AND-NOT 76, the level O arrives at the second input of the buffer element 68 and enables the transmission

5 addresses of the interrupt vector from register 80 via buffer element 68 to the output of interrupt-forming node 51. The signal from the output of the second element AND 74 through the third element HE 79 sets the level 1 to

Claims (1)

0 output node 51 form interrupts. Apparatus of the Invention A device for controlling a computer computational process, comprising a priority register, a clock pulse generator, 5 control element I and M of the control unit (M is the number of priority levels), each of which contains a time control node, the output of the clock generator connected to the first input 0 of the control element I, the output of which is connected to the first permitting input of the time control node i-ro control unit (1 1, M), the group of information inputs of the priority register and M control nodes 5 times are connected to the input-output of the device for connection to the system mainline of the controlled computer, characterized in that, in order to extend the functionality by 0 to ensure control of calls to the stack memory and its state at different priority levels, the device contains an interface block, and each control block contains the first OR-NOT element, 5. first trigger, delay element, first and second elements AND, element NAND, main element, reversible counter, second element OR NOT, first element NOT, third element AND, element OR, first and second pulse shapers, second trigger , the second element is NOT, the second input of the control element AND is connected to the first output of the interface block, the second, third and fourth outputs 5 of which are connected respectively to the second, third and fourth permitting inputs of the time control unit i-ro of the control unit, the fifth output of the interface block is connected to the first input of the I-NO element of the i-ro control unit whose output is connected to the control input of the trunk element The 1 st control unit, the output of which is connected to the input-output of the device for connection to the system main line of the controlled computer, the sixth output of the interface block is connected to the fifth permitting input of the time control node, the first inputs of the first element And the first element OR of the 1st control unit, the seventh output of the interface block is connected to the reset input of the reversing counter of the 1st control unit, the eighth output of the interface block is connected to the S input of the first trigger of the i-ro control unit, the ninth the output of the interface unit is connected to the second input of the first OR-NOT element, the first input of the second AND element, the second input of the AND-NOT tape of the 1st control unit, the tenth output of the interface unit is connected to the control input of the priority register, the first output of the bit Dov which is connected to the first entrance of the third on the element AND of the 1st control unit, 0 + 1}, the output of the bits of the priority register is connected to the information input of the time control node, the input of the delay element, the second inputs of the first of the second AND elements and the third input | tape AND NES 1- control unit, in each control unit, the output of the first OR element is NOT connected to the R input of the first trigger, the output of which is connected to the third inputs of the first and second elements AND, the output of the first element AND is connected to the incremental input of the reverse counter, whose decrement input connected to the output the second element AND, the information output of the reversible counter is connected to the first information input of the main element and the input of the second element OR NOT, the output of which is connected to the input of the first element NOT, the output of which is connected to the second input of the third element AND, the third input of which is connected to the output of the delay element , the outputs of the loan and overflow of the reversible counter are connected respectively to the inputs of the first and second pulse shapers, the outputs of which are connected respectively to the first and second inputs of this ementa OR. the third input of which is connected to the output of the third element AND, the output of the element OR in each control unit is connected to the input of the second element NOT and the interrupt input of the interface unit, the output of the second element is NOT connected to the S input of the second trigger, the output of which is connected to the second information By the input of the main element, the information outputs of the time control nodes M of the control blocks are connected to the information input of the block the mate, the eleventh output of which is connected to the input of the second trigger of the i-ro control unit, the information input-output of the interface unit is connected to the input-output of the device for connection to the system main line of the controlled computer, the interface unit contains three main elements, an address selector, an OR element, twelve NOT elements, seven OR-NOT elements, two AND-NOT elements, a trigger, a comparison circuit, an interrupt generation node, a register, the information inputs of the first and second trunk elements and the output being third its main element is connected to the information input / output of the interface unit, the output of the first main element is connected to the information input of the register, the output of the first element OR is NOT connected to the control input of the register, the input of the first element NOT and the first input of the interrupt generating node, the output of the register is connected with the first input of the comparison unit, the second input of which is connected to the output of the second main element, the control input of which and the input of the second element are NOT connected to the output of the OR element, the first the input of which and the first inputs from the first, for the fifth OR-NOT elements, the input of the third element are NOT connected to the information input-output of the interface block, the second input of the OR element, the first inputs of the sixth and seventh OR-NOT elements and the input of the fourth element are NOT connected information input / output interface block, the output of the fourth element is NOT connected to the second input of the node form. no interrupts and is the ninth output of the block of support, the output of the second element is NOT connected to the first input of the first AND-NOT element, the second input of which is connected to the output of the comparison circuit, the first output of the address selector is connected to the second input of the first OR-NOT element and input the fifth element is NOT, the output of which is the fifth output of the interface block, the second output of the address selector is connected to the second inputs of the second and seventh elements OR NOT, the output of the seventh element OR NOT is connected to the input of the sixth element NOT, the output of which is connected n to R-input of the flip-flop, S-input thereof. connected to the output of the seventh element NOT, the input of which is connected to the output of the second element OR NOT, the third output of the address selector is connected to the second inputs of the third and sixth elements OR NOT, the fourth output of the address selector is connected to the input of the eighth element NOT, the output of which is the third the output of the interface unit, the fifth output of the address selector is connected to the input of the ninth element NOT, the output of which is the fourth output of the interface block, the sixth output of the address selector is connected to the second input of the fourth element OR NOT, in the stroke of which is the tenth output of the interface block, the output of the sixth element OR is NOT connected to the input of the ten element NOT, the output of which is connected to the control input of the third trunk element, whose information input is the information input of the interface block, the output of the first element is The eighth output of the interface, the output of the trigger is the first output of the interface, the outputs of the third element OR NOT and the third element are NOT the second and sixth outputs of the interface, third entry Interrupt-shaping node is the interrupt input of the interface unit, the first to fourth outputs and the fourth and fifth inputs of the interrupt NII node are connected to the information input output of the interface block, the output of the first element is NOT connected to the control input of the first trunk element, the first input of the second element and NOT and is the seventh output of the interface block, the output of the second element IS-NOT is connected to the input of the eleventh element NOT, the output of which is the eleventh output of the interface block, the seventh output of the address selector is connected to the second input of the fifth element OR NOT, the output of which is connected to the input of the twelfth element is NOT, the output of which is connected to the second input of the second element NAND, the inputs-outputs the address selector is connected to the information input / output of the interface unit. Fig.Z fi $.