SU1647594A1 - Programmable controller - Google Patents

Abstract

The invention relates to automation and computer technology, in particular, to software control of process equipment, and can be used in programmable process object control systems, the control algorithm of which is described using Boolean functions. The purpose of the invention is to increase the speed in the calculation of Boolean functions and reduce hardware costs. A programmable controller contains a computing unit and input-output units connected in series. To achieve the goal, a logical memory block is inserted into the controller, and each I / O block additionally contains a signal level matching node, a single vibrator and an OR element. The logical memory unit contains the first, second and third switches, the element is NOT. operative memory. 2 hp f-ly, 5 ill., 2 tab.

Description

The invention relates to the field of automation and computer technology, in particular to the software control of technological objects, the control algorithm of which is described using temporary Boolean functions.

The purpose of the invention .. is to increase the speed in the calculation of Boolean functions and reduce hardware costs.

Figure 1 presents the scheme of the programmable controller; Fig. 2 is a block diagram of a logical memory; Fig. 3, examples of the implementation of the computing unit and the signal level matching node, respectively; figure 5 - timing diagram of the phase of exchange.

The programmable controller (Fig. 1) contains a computational unit 1, a logical memory unit 2, 3i-3ri I / O units, signal level matching nodes 4i-4n, 5i-5n one-vibrators, amplifier nodes 6i-6n, buffer registers 7i-7n , the first shift registers 8i-8n, the elements OR 9i-9n, the triggers of the failure of UN On, the second shift registers 11Н1п, code converters 12i-12n, outputs 13i-13n and information inputs 14i-14n.

Computing unit 1 has address output 15, information input / output 16, outputs Record 17, Sample 18, Shift 19, and Receive 20.

The logical memory unit 2 has address input 21, information input / output 22, input Record 23, Sample input 24 and information input 25.

Each node 4i of the signal level matching (1, p) has an output 26, inputs 27-30 and outputs 31-33.

The block-logical memory (Fig. 2) contains a random-access memory 34, the first 35, and the second.

 Vj

SP

yu

swarm 36 and third 37 switches, element NOT 38.

The computing unit (FIG. 3) contains a computing node 39, a clock pulse generator 40, a bus driver 41, a system bus controller 42, a permanent memory 43, a RAM 44, a code converter 45.

The signal level matching node (Fig. 4) contains capacitors 46i-464, resistors 471-474, and Schmidt triggers 48t- 484.

The device works as follows.

The user program in the input programming language is a system of equations, where the arguments are input variables (input discrete signals), internal variables, output variables (output discrete signals), and functions are the internal and output variables.

During the translation process, the user program is converted into a sequence of one-bit logical instructions, then each such instruction is represented by several machine instructions of the computational node 39 (miro processor).

As a computing node 39 can be selected KR580IK80A. The mnemonic names of machine instructions are, for definiteness, given below in the language Assembler of the specified microprocessor.

8 tab. Table 1 lists the one-bit logical instructions (hereinafter instructions), their mnemonic codes, the algorithm for executing each instruction, the sequence of microprocessor machine instructions encoding each instruction, and the assembler instruction codes.

XX means the physical ad-. memory cells where the corresponding is stored is variable.

Boolean functions are computed using the 0th bit of registers A and B of the microprocessor, the constant 0 is stored in its register D.

PQ, IQ, SQ, RQ denote the addresses of block 2 of logical memory 2, when accessed, respectively

reading and writing the direct value of the variable Q;

reading inverse value of variable Q;

assigning the variable Q a value of 1 if the value of the 0th digit of register A is 1:

the assignment of the variable Q to the value O, if the value of the 0th bit of register A is equal to 1.

The following sequence of machine instructions is recorded in the RST1 program: RST1: ORA B

MOV B, A MOV A.M RET

For example, a user program consists of two equations: X1 + / X2 -X3 Y1 / X1 X3 + X2 Y2,

where X and Y denote some input and output device variables.

The program is encoded with the following sequence of machine instructions: CONTR MOV BD Instructions: X1

LDA PX1

LXJH, 1X2Instructions + / X2

RST1

LXIH, RCSInstructions -ChZ

ANAM

ORAB Instructions Y1

STA PY1

MOV B.DInstructions: / X1

LDA 1X1

LX1H, RCS Instructions - CAM ANAM

Lxfh PX2 Instructions + X2

RST1 ORAB Instruction SY2

STA SY2

RET End of Work

programs.

Each time the CONTR program is called, the values of the variables Y1, Y2 will be calculated from the values of the variables X1, X2, X.

The user program is stored in memory 43; variables on which one-bit logic instructions are executed are stored in memory 34; data organized byte-by-byte, for example, the current values of timers and counters, the working and stack areas of node 39, are stored in memory 44.

The operation of the node 39 is synchronized by the generator 40. In each cycle of reading or writing from the multi-bit address output of the node 39, through the bus driver 41, the address information is fed to the multi-bit inputs of memory 43, memory 44, inputs of converter 45, memory 34. The multi-control output of the control information unit 39 is fed to the same input of the system bus controller 42, which produces signals

Control Read (CTN) and Write (REC). These signals, along with the address information, are fed to the inputs of the converter 45.

KP580VK28 can be selected as a system bus controller.

At the outputs of the converter 45, signals are generated:

45 — memory sample 43;

45 — memory sample 44;

453-signal recording;

 signal sampling;

 Shift signal;

45- signal reception.

The operation of converter 45 is described by a truth table (Table 2).

Hereinafter, the expression “to give a signal Record, Sample, Shift, Reception” will be understood as the formation of a single value of such a signal with a duration determined by the duration of the control signals CTN and REC.

For all not listed in table. 2 combinations of the values of the signals CTN and ZAP values of the output signals of the converter 45 are defined as O.

The operation of the programmable controller as a whole in the folding time of two cyclically alternating phases: Calculation and Exchange.

In the Calculation phase, a user program is executed, with the values of the input, output, and internal variables being read and written to memory 34.

In the Exchange phase, the calculated values of the output variables from the memory 34 are transferred to the multi-bit outputs t3t-13n, and the values of the input variables are updated by transmitting signals from the multi-bit inputs 141-14p to the memory 34.

In the Calculation phase, the acceleration of the calculations of one-bit logical operations is achieved due to the excessive use of the address space of node 39. Let Si be the physical address determined by the bits of the AO ... A10 address, a certain one-bit variable Q in memory 34.

When translating a user program for such a variable, the following substitutions must be made:

PQ-Sj + 4 $ 0H:

IQ Si + 4800H;

SQ - Si + 4800H;

RQ Sj + 5WH,

The execution of a read command at node 39 by address PQ causes the following:

At the output 454 of the converter 45, a single value of the Sample signal is generated.

Signal Sampling at the third control input unlocks the third switch 37.

At the information output of the memory 34, the value of the variable Q determined by the bits of the address AO ... A10 is formed, which through the first information input and output of the third switch 37 and through the DO bit of the second and first multi-bit inputs-outputs of the system bus controller 42 enters information output node 39.

When the node 39 executes the read command at address Y, everything happens similarly to reading at address PQ, except that the output of the third switch 37 receives the inverted value of the variable Q from the output of the HE element 38.

When the node 39 executes the write to memory command at the PQ address, the following occurs.

At the output 45z of the converter 45, a single value of the signal Record is generated.

By a signal the recording on the third control input is unlocked by the second switch 36, and from its output a single signal is fed to the control input of memory 34.

The DO bit information of the multi bit information input / output node 39 through the system bus controller 42 goes to the first information input of the first switch 35, and from its output to the information input of memory 34. where it is recorded at the address determined by the address bits of the AO. ..A10.

The execution by the node 39 of the write to memory command at the SQ address causes the following.

At the output 45z of the converter 45, a single value of the signal Record is generated.

The Recording on the third control input unlocks the second switch 36, and a single signal is generated at its output, provided that its first information input receives a single information DO of the multi-bit information input-output node 39 through the system bus controller 42.

A single signal is applied to the information input of the memory 34 from the output of the first switch 35.

The execution by the node 39 of a write command at the address RQ occurs in a manner similar to that of the address SO. except that a zero signal is applied to the information input of the memory 34 from the output of the first switch 35.

The output functions of the first 35, second 36 and third 37 switches are described respectively by logical expressions: Inf.G- / A11 - / A12 + A11- / A12 +. All- A12 (1)

Record (/ A11- / A12 + Inf.G- AI- / A12 + Inf.G- / A11- A12 + A11 A12) (2) Sampling (Q / A11 / A12 + / QA11- / A1 + QA11 -A12). : (3)

Info.G and Info.2 indicate the signals, respectively, at the first information input-output 22 and at the second information input 25 of block 2 of the logical memory; through Q, a signal at information output of memory 34; through A11, A12 - signals of the 11th and 12th bits of the multi-bit address input of block 2 of the logical memory.

For definiteness, we assume that the bit width of the multi-bit outputs is the same and is equal to N, and the bit-width of the multi-bit inputs 14t-14n is the same and equal to M.

Before the exchange, the computing unit 1 generates a receive signal for storing the values of the input discrete signals in the second 111-1 tn shift registers.

For this, node 39 must execute the command

Sta,

In this case, the output 45 of the converter 45 generates a receive signal, which

through the fourth input and the fourth output of nodes 4i-4n are fed to the inputs of parallel recording of the second 111-11P shift registers, causing the current values of the input discrete signals received from the multi-input inputs 14i-14n to be stored through the multi-digit inputs.

In the future, the reception of discrete input signals and output of discrete signals for input-output blocks Zn, 3n-i ... 3i alternate.

Reading and writing information about the input and output signals in the memory 34 is carried out when the node 39 executes commands

read and write to the memory with the base address 58 / YI, which is loaded into the registers H, L of node 39. and the offset Si, which defines the physical address of the variable memory 34.

A fragment of the exchange program serving one I / O unit 3i is shown below;

Repeat / M O V M, A b

M times

./NX H

MOVM.A / NXH

repeat time

M About V M, A

/ NX H AL O V A, M L / NX I

M About V A, M

/ Nxh

 /

M O V A, M / NXH

When the MOVM, A command is executed in such a fragment, the Shift and Write signals are formed at the outputs 45z and 45s of the converter 45.

The value of the input discrete signal from the output of the serial information of the second 11p shift register of the last I / O unit Zp is fed through the corresponding output of the nodes 4i-4n and through the second information input of the first switch 35 to the information input

M-input variable

(M-1) - input variable

1- input variable N-input variable

(M-1) - output variable

at

V

1 output variable

memory 34. According to the signal recording, this information is stored at the address determined by the bits of the AO ... A10 of the multi-bit address input of the block 2 of the logical memory.

The Shift signal through the corresponding outputs of nodes 4i-4n arrives at the clock inputs of the first 8i-8n and second 11И1П shift registers, causing a sequential shift of information. Thereby, at the output of the serial information of the second 11n shift register, the value of the next discrete input signal is generated.

When the MOV A, M command is executed in the above fragment, Shift and Sample signals are generated at outputs 454 and 45s of converter 45.

The value of the output discrete signal, read at the address determined by the bits AO ... A10 at the information output of memory 34, through the first information input and output of the third switch 37, which is unlocked by the Sample signal, goes further through the first output and the second output of node 4i block input-output 3i to the input of the first 3i shift register.

According to the Shift signal, this value of the output discrete signal will be recorded in the lower order of the first 8i shift register of the I / O unit 3i.

After the output of the discrete signals of the I / O unit 3i is outputted by the computing unit 1, a Receive signal is output. The shift registers of the output discrete signals received in the first 8i-8n are written into the buffer registers 7i-7n, and then through the multi-bit input and output of the nodes of the 6i-6n amplifiers to the multi-output outputs I3i-13n of the programmable controler.

Time diagram of signals Record. Sample, Shift and Reception in the Exchange phase is shown in FIG. 5.

When a short circuit in the output discrete signal of one of the 3t I / O units occurs, a single signal is generated at the failure output of the amplifier amplifier 6i, which is fed to the installation input of the failure trigger U and sets it to state 1. through the element OR 9 to the input of zeroing of the buffer register 7i, causing the output discrete signals of this block to be turned off.

Also, a single signal from the output of the failure trigger 10) is fed to one of the bits of the multi-bit information input of the second 111 shift register. In the Exchange phase, information about the failure in this I / O unit 3 enters one of the memory cells 34. Failure information processing in the I / O ZH-3p units can be provided in the user program.

5i-5n monovibrators are triggered by each Receive signal. While the arrival period of the signals does not exceed a certain critical time T, zero-voltage is generated at the outputs of the 5i-5n one-shot

signal. The time T is chosen somewhat longer than the maximum time for the execution of the phase of the Calculation.

If as a result of a breakdown of the computing unit 1 or as a result of a communication link breaking between the computing unit 1 and the 3i-3n I / O blocks, the time between two signals is higher than T, then at the outputs of the one-shot 5i-5n

a single signal is generated which, via the OR 9i-9n elements, is input to the zeroing of the buffer registers 7i-7n, causing the output discrete signals to turn off. This puts the programmable controller in the safe state.

Claims (3)

1. A programmable controller that contains a computing unit and connected in series n input / output units, where n is the number of subscribers, each i-th input / output unit contains a node of amplifiers, where t 1, n, the buffer register, the first and second shift registers , the failure trigger, the i-th information input of the programmable controller is the information input of the parallel recording of the second shift a register whose serial information input is connected to the serial output of the first shift register, the information input and output of the buffer register are connected respectively to the parallel information output of the first shift register and the input of the amplifier node whose information output is the tth output of the programmable controller, the failure output the amplifier node is connected to the input of the failure trigger installation, characterized in that, in order to improve performance in calculating Boolean functions and reducing hardware costs, it contains a logical memory block, and every 1st I / O block additionally contains a signal level matching node, a single vibrator and an OR element, the output of which is connected to the zeroing input of the buffer register, the first and second inputs of the OR element are connected respectively to the one-vibrator output and output Failure trigger, the reset input of which is connected to the one-shot output; Failure trigger output; connect to the additional bit of the information input of the parallel write of the second shift register; Information input in series The first recording of the first shift register is connected to the first output of the signal level matching node; the clock inputs of the first and second shift registers are connected to the second output of the signal level matching node, the recording input of the buffer register, the single-vibrator input and the parallel recording input of the second shift register are connected to the third output signal alignment node, address input, signal inputs Record and Sampling of a logical memory block are connected to the same outputs of the computing unit, information input The d-output of the computational unit is connected to the information input-output of the logical memory unit and to the first input of the signal level matching node of the first I / O block, the fourth output of the signal level matching node of which is connected to the information input of the logical memory block, outputs of the Shift m Signal Reception the computing unit is connected to the second and third inputs of the node matching the signal levels of the first I / O unit, the second and third inputs of the node matching the signal levels (l + t) -ro of the input / output unit Switched to the second and third outputs of the i-ro signal level node of the I / O unit, the fourth output and the first input of the signal level matching node (fH) ro of the I / O unit, respectively, are connected to the fourth input of the signal level matching node and to the serial information output the second shift register of the 1st block I / o, the output of the sequential information of the second shift register of the n-th input-output connected to the fourth input of the node matching the signal levels of the n-th block input-output Yes. 2. The controller according to claim 1, about tl and h and y and y and so. that the logical memory unit contains the first, second and third switches, the element NOT, the operational memory whose address input is connected to the address input of the logical memory unit, the information input, the read / write input and the information memory output are connected respectively to the outputs of the first and the second switch and the first information input of the third switch, the output of which is connected to the first information input of the first, information input of the second switch and to the information input / output of the logical memory unit, the information input of which is connected to the second information input of the first switch, the first and the second control inputs of the first, second and third switches are connected to the higher bits of the address input of the logical memory block, the Record and Sample signals inputs of which are connected respectively to the third control inputs of the second and third switches, the element input and output are NOT connected respectively to the information output memory and the second information input of the third switch. 3. The controller according to claim 1, of which is that the computing unit contains a computing node, a clock generator, a system bus controller, a bus driver, a permanent and operational memory, and a code converter, the address output of the computing node being connected to the information input of the bus driver, the output of which is connected to the address inputs of the permanent and operational memory, with the first input of the code converter and is the address output of the block whose information input-output is connected through the data bus to the information input-output of the system bus controller, the output of the permanent memory and the information input-output of the RAM, the information input-output of the computing node is connected to the information input-output of the system bus controller, the output of which is connected to the input of Record the main memory and the second input of the code converter, the third input of which is connected to the output Read of the system bus controller, the control outputs of the computing node are connected to the corresponding control The inputs of the system bus controller, the output of the clock generator are connected to the clock input of the computing node, the first and second outputs of the code converter are connected respectively to the input of the Permanent memory sample and the input of the RAM memory sample, the third to the sixth outputs of the code converter are respectively outputs Record, Fetch, Shift and Receive block. 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