SU1462355A1 - Device for adamar conversion of digital sequence - Google Patents

Description

The invention relates to automation and computing, and is referred to as signal spectrum analyzers, and can be used with a number of digital signal processing devices, in particular, image processing devices.

The purpose of the invention is to increase the speed of the device by introducing the structure of the memory blocks, allowing simultaneous reading of the arguments of the current Hadamard transform step from the memory blocks and then simultaneously writing the results of the calculations into the memory blocks at the addresses required by the fast Hadamard transform algorithm.

The drawing shows a diagram of the device.

The digital sequence Hadamard transform device contains counter 1, trigger 2, switch 3 information signals, address generation switch 4, address switch 5, memory block 6, AND 7 element, buffer register 8, address switch 9, memory block 10 , element 11, buffer register 12, address switch 13, memory block 14, element 15, buffer register

16, address switch 17, memory block 18, AND 19, buffer register 20, address switch 21, memory block 22, AND 23 element, buffer register 24, address switch 25, memory block 26, And 27 element, buffer —th register 28, address switch 29, memory block 30, AND 31, buffer register 32, address switch 33, memory block 34, AND 35 buffer register 36, adder 37, subtractor 38, information switches 39 and 40 signals, elements OR 41-44, output 45 odd numbers of the device, input 46 of the device's synchronization, device setup input 47, input 48 of countable numbers roystva, the input device 49 of odd numbers, the input device 50 a predetermined mode and the output device 51 even numbers.

The device works as follows.

Before the start of the Hadamard transformation, the initial digital sequence of the dpina is entered into the operational memory. To do this, input device 50

14

 , ten

15

20

25

k - 5, and

462355

a logical unit signal is given which permits the passage of 48 even numbers supplied to the input and the input 49 of the odd numbers of the input sequence device through the switch 3 to the inputs of the memory blocks, and simultaneously the installation impulse input 47 is supplied to the installation pulse, which converts counter 1 and trigger 2 to initial state. In addition, it is necessary to apply clock pulses to the input 46 of the device synchronization corresponding to the arrival of the input sequence. Counter 1 starts the counting of incoming clock pulses and the generation of the K (K O, 1.2, .. ,, n / 2-1) number of the current step of the data entry procedure.

KoMNryTaTop 4 generates four current addresses according to the following rule: the first output of switch 4 will be A1 code, the second output of switch 4 will be A2 2 code (n -1) K, the third output of switch 4 will be A3 2 K + code 1, at the fourth output of the switch 4 will be A4 code. The incoming sequence is recorded in the fifth, sixth, seventh, and eighth memory blocks. In this case, the odd terms of the sequence coming from the input 48 of the odd numbers of the device are recorded in memory blocks 22 and 30, and the even terms of the sequence coming from the input 48 of the odd numbers of the device are recorded in the blocks 26 and 30 of memory. After finishing the input of the digital sequence, it is necessary to remove the control signal of the logical unit from the input 50 of the device.

After that, the conversion of the entered sequence starts, according to the fast Hadamard transform algorithm. For the sequence of the volume of numbers, n identical iterations of the transformation are required. Each iteration consists of 2 “- (n-1) steps. Denote the step number by the index K. At the Kth step, it is necessary to perform calculations using the formulas

thirty

35

40

45

50

55 x (2 K) X (K) + X (K + 2 (p-1)),

Х (+ 1) Х (К) - Х (К + 2 (п - - 1)).

where X (K) is an element of the sequence with the number K.

The required sequence element numbers corresponding to their addresses in the memory blocks are generated by the switch 4.

For convenience of further description, we divide eight memory blocks into two subgroups with the same composition and internal interrelations: even and odd, the fifth, sixth, seventh, and eighth memory blocks will enter into the odd subgroup, and the first, second, and even third and. fourth memory blocks.

The execution of one iteration consists in sampling two numbers from one subgroup of memory blocks, performing addition and subtraction operations and writing the results of these operations into another subgroup of memory blocks. When executing an iteration with an odd number — first, third, etc. — information is transferred from an odd subgroup to an even number, and if an iteration is executed with an even number — the second, fourth, etc., information is transmitted from an even number. subgroups in odd.

Let us consider in more detail the process of transmitting information during the Kth step of the jth iteration of the transformation. Let j be an odd number, then the information is transferred from the odd subgroup of memory blocks to even. In the case of an odd iteration, the signal from the inverse output of trigger 2 (logical zero) allows reading information from the memory blocks of the odd subgroup, and the signal from the direct output of trigger 2 (logical unit) allows writing information to the memory blocks of the even group. In addition, signals from the outputs of trigger 2 control the operation of all address switches.

Consider the process of selecting information from an odd subgroup. At the same time, the addresses A1 and the sixth memory block through the fifth and sixth address switches are fed the address A1 K, and the addresses of the seventh and eighth memory blocks through the seventh and eighth address switches are fed the address A2 K + 2 ( n-1) i.e. Sampling to the required addresses. If the address K is even, the element And 23 prohibits the passage

five

five

0

information through the buffer register 24, and the output of the element OR 43 through the buffer register 28 is the information from the output of the memory block 26. If the address K is odd, the information deny signal is output from AND 27 and the output of OR 43 is information from the output of memory 22 through the buffer register 24. Memory 30 and 34, i.e. the odd sequence elements are sampled only from memory 30, and the even sequence elements are sampled only from memory 34. In this case, memory blocks 22 and 26 are designed to store only the elements of the sequence belonging to the lower half of the address space, and memory blocks 30 and 34 to store only the elements of the sequence belonging to the upper half of the address space. The resulting elements are successively passed through the switches 39 and 40 to the inputs of the adder a 31 and the subtractor 38. At the output of the adder 37, the value of the sum of the numbers appears, and the output of the subtractor 38 is the difference value. numbers

Consider the process of writing information into an even subgroup of memory blocks, which occurs after performing addition and subtraction operations. The structure of an even subgroup is similar to the structure of an odd subgroup. The first memory block of the even subgroup corresponds to the fifth memory block of the odd subgroup, the second memory block of the even subgroup corresponds to the sixth memory block of the odd subgroup, the third memory block - 5 even subgroup corresponds to the seventh memory block of the odd subgroup, the fourth the memory block of the even subgroup corresponds to the eighth memory block of the fuzzy subgroup. The regions of the values of the elements of the processed sequence for the corresponding memory blocks coincide. Therefore, the elements of the sequence with even numbers 55, coming from the output of the adder 37, go through the switch 3 to the information inputs of the memory blocks 10 and 13. At the same time, the address inputs of these memory blocks are through the second 9 and

five

0

0

The fourth 17 address switches are delivered by the address A4 2 K generated by the switch 4 and all the elements of the sequence with even numbers are written to these memory blocks. Similarly, all the elements of the sequence with odd numbers are written to the first 6 and second 10 memory blocks. At the same time, the odd address A3 + 1 produced by the switch 4 is fed to the address inputs of these memory units through the first 5 and third 13 address switches.

Similarly, information is transmitted when an even-numbered conversion iteration occurs, but the transmission direction is reversed.

After completing the iterations in one of the subgroups of the memory block, the elements of the completely Hadamard-transformed input sequence will be recorded. In order to obtain output results, clock pulses must be fed to the device sync input 46, and the process of rewriting information will continue even during the output of 45 odd numbers of the device and the output of 51 even numbers of the device will appear elements of the Hadamard transformed input digital sequence.

Claims (1)

Invention Formula A digital sequence Hadamard transform device comprising the first and second switches 10 15 From the second to the eighth address switches, from the second to the eighth memory blocks, from the first to the eighth And elements, from the first to the eighth buffer registers, from the first to the fourth elements OR, the subtractor, the third and fourth switches, with output i-ro ( i 2.8) the address switch is connected to the information input of the i-ro memory block, the first output of the first switch is connected to the information input j-ro (j 1,4) of the memory block, the output of which is connected to the information input of the j-ro buffer register whose output is connected to the first input of the j-ro element OR, the second output of the first switch is connected to the information input of the (J + 4) th memory block, the output of the second is connected to the information input of the (j + 4) th buffer register, the code of which is connected to the second input of the j-ro element OR, 25 the first output of the second switch is connected to the first information inputs of the first, third, fifth, and seventh address switches, the second output of the second switch is connected to the first information inputs of the second, fourth and eighth address switches, the third output of the second switch is connected to the second data input of j-ro switch address, the fourth output of the second switch is connected to second data input of the (j + 4) th switch addresses, outputs of the first and second elements are connected to Hilti 20 thirty 35 „“ The first information inputs of the matches, the trigger, the adder, the first com- 40 h v v Actually, the third and fourth switches, the second information inputs of which are connected to the outputs of the third and fourth address, respectively, the first memory block and the counter, the counting input of which is the input of the synchronization device, the mode setting input of which is the control input of the first switch, the first information input which is connected to the output of the adder, the information output of the counter is connected to the information and control inputs of the second switch, the output of the first switch of the address is connected n to ad- esting input of the first memory unit and the installation counter input connected to the first adjusting input, and the trigger is input adjusting device, characterized in that, in order to increase bystrodeystvt l introduced therein five From the second to the eighth address switches, from the second to the eighth memory blocks, from the first to the eighth And elements, from the first to the eighth buffer registers, from the first to the fourth elements OR, the subtractor, the third and fourth switches, with output i-ro ( i 2.8) the address switch is connected to the information input of the i-ro memory block, the first output of the first switch is connected to the information input j-ro (j 1,4) of the memory block, the output of which is connected to the information input of the j-ro buffer register whose output is connected to the first input of the j-ro element OR, the second output of the first switch is connected to the information input of the (J + 4) th memory block, the output of the second is connected to the information input of the (j + 4) th buffer register, the code of which is connected to the second input of the j-ro element OR, 5 the first output of the second switch is connected to the first information inputs of the first, third, fifth, and seventh address switches, the second output of the second switch is connected to the first information inputs of the second, fourth and eighth address switches, the third output of the second switch is connected to the second the information input of the j-ro address switch, the fourth output of the second switch is connected to the second information input of the (j + 4) -th address switch, the outputs of the first and second SHS elements are connected to 0 0 five of the third and fourth switches, the second information inputs of which are connected to the outputs of the third and fourth elements of the OR, respectively, the transfer output of the counter is connected to the second setup input of the trigger, the direct output of which is connected to the control inputs of the first, second, fifth, and sixth terminals. 1 address switches, write control inputs (read) of the first, second, fifth, and sixth memory blocks, and the control input of the fourth switch, whose output is. 5 pogo is the output of odd numbers of the device and is connected to the first inputs of the adder and subtractor, the output of which is connected to the second information output of the first switch 0 7-. 14623558 pa, the third and fourth information flow of which is out of even The inputs of which are the input numbers of the device and connected to the even and odd numbered inputs of the adder and subtractor, sat down devices inverse output, outputs of high and low bits the trigger is connected to the control of the 1st switch (1 - 1.8) of the address switch the inputs of the third, fourth, seventh-connected respectively to the first th and eighth cocyutators inputs to the second inputs of the 1st element And control write (read) the output of which is connected to the input the third, fourth, seventh resolution of the recording of the 1st buffer the eighth memory block and the control register, the input of the third switch, you