SU1337904A1 - Device for fast fourier transform - Google Patents

Abstract

The invention relates to the field of computing and is intended to perform the Fast Fourier Transform (FFT) algorithm used in digital signal processing. The purpose of the invention is to simplify the device. The goal is achieved due to the fact that the device consists of two groups of memory blocks 1.2, an arithmetic unit 3 containing an adder 4, a subtractor 6, a multiplier 7 complex numbers and delay elements 7.8, a synchronization unit 9 consisting of triggers 10.11 and delay elements 12, switches 13 and 14, counters of addresses 15 and 16, decoder of address 17, shift register of iterations 18, block of elements And 19, block of permanent memory 20 and switch 21. The device implements FFT algorithms with decimation by frequency and constant structure from and era tio to iteration. 1 z.p. f-ly, 3 ill. i 1 DO DO SAE SO

Description

113

The invention relates to computing and is intended to perform a Fast Fourier Transform (FFT) algorithm, which is digitalized in signal processing.

The purpose of the invention is to simplify the device.

Figure 1 shows a block diagram of an apparatus for performing an FFT; in FIG. 2, the graph of the FFT algorithm; in fig. 3 - Basic FFT operation.

The device contains two groups of blocks 1 and 2 of memory with arbitrary sampling, each of which consists of two blocks 1.1 and 1.2 (2.1 and 2.2), arp- grammatically; b: gok 3, containing adder 4 i oMn: i (jKCHhix numbers, subtracted- 1 spruce 5 complex numbers, in jugger

6KOMnjleKCHbix numbers and two elements

7 and 8 delays, a synchronization unit 9 comprising two triggers 10 and 11

and delay element 12, the bottom of the data switch 13 and 14, two address counters 15 and 16, address decoder 17, shift register 18 iterations, block I 19, block 20 of permanent memory, and keyboard recorder 21 write signals.

The device implements FFT algorithms with decimation in frequency and constant structure from iteration to iteration, whose graph is shown in Fig. 2, where M (i 0,1, ..., logjN) denotes consecutive data arrays of the H1G1-corrected graph, and a | - elements of the array ГГ (n 0.1 ..., N). Such an algorithm makes it possible not to change the order of operand selection from the memory and recording the result of E) calculations at all stages of the FFT calculation, and also makes it possible to divide each memory block into only two sections with the simplest organization of the I / O buffer.

In this case, the vectors of the array M;

2t 2t

2m L lrathjiJ L 2 m-and N / 2 J

stored respectively in the fourth. and odd cells of sections A and B of the memory block.

Ob, and the formula for obtaining the elements of the array M from the elements of the array M, has the form

 but

t + n12

,,., (I) 2n ,,, “-

1 de m 0,1, ..., t -

i 0,0, ...,

According to formula (I) when calculating the values of a pair of neighboring elements

array M ;, proizvod1 "i

I'm about and a.

7t V m «i

15

Selects a pair of items.

and

a to ,, from the first and second half

GT1 + / 2

Massina M and swivel factor

t (W of gab.gp1tsy complex coefficients. On the c. structural scheme, this corresponds to the choice of a pair of like elements from blocks 1.1 (2.1) and 1.2 (2.2) of one group and transmitting them to the first and second informational

the inputs of unit 3 using the da1P1yh switch. Moreover, the choice of even or odd elements is determined by the value of the + 1-th bit of the counter 15 of the address connected to the switching

input switches 13 and 14 data.

Recording 1 results is performed in adjacent cells of blocks 2.1 (1.1) or 2.2 (1.2) of another group, depending on the value of the most significant bit.

an address counter 16 connected to the switch by the input of 21 write pulses. Selection of the desired pontor set, 0 t,. N / 2 -I, W-ITAL W, W,. . . W of block 20 CONSTANTLY memory is produced

at the address that is formed in accordance with formula (1) using the block of elements AND 19, the counter 15 of the address and the register of 18 iterations, the state of which at the first iteration

 I 1. . . I 1 I, on the second - 1 1 ... 1 1 O, on the third - 11 ... 100, on P-th - 00 ... 000.

Before starting the FFT in block 1 (RAM), there is

N elements of the original sample. Counters 15 and 16 addresses sbropgeny. The counter 16 is blocked by a low signal from the output of the element 12 delay. Counter 15 unlocked high

signal level from the output of the trigger II. The switch 13 and the switch 14 are opened by the low level of the signal from the output of the trigger 10. The address decoder 17 is set to a position where the outputs of the counter 15 and 16 of the address are connected to the HI.IM addresses of the first and second memory blocks, respectively.

The FFT calculation begins with the delivery of clock pulses (TI) to the clock input of the device. Under their influence, counter 15 starts to work,

causing readout of similar rar - Q 17 outputs of counters 15 and Dov operands a °, a, and W ° from block 16 and unlocks the counter 16 on the output of element 12, back of ger 10, switches overflow signal 16 to the counting input, closes 13, open at this 14, connects with

The main inputs of the group blocks are provided by the switch 21 in the latest reading modes and appropriately.

operative 1 and constant 20 memories to the inputs of the arithmetic unit 3 and further to the inputs of the adder 4, the subtractor 5 and the delay element 8 8. The corresponding bits of the sum (g

arrive at the input element 7 delay

and the differences of the same name

about

but

N12

- to the input of the multiplier 6, on

the other input of which comes the corresponding bits of the rotary multiplier W °, delayed by the required number of clock cycles by the delay element 8.

Through K clock pulses TI on the first and second outputs of the arithmetic unit 3, which are the outputs of the delay element 7 and the multiplier 6, the same digits of the result a and a, appear. At the output of the delay element 12, a high level appears from the output of the trigger 11, which enables the counting mode of the address counter 16 and opens the write signal switch 21. The recording of the indicated result bits is performed in memory block 2 at an address that is determined by the output state of counter 16.

After issuing in the arithmetic unit 3 last bits of operands s; -: -1

but,

and w

the signal of the quarantine comes in iterations and trig

 N / 2-1 N- 1

from counter 15 to register 1 inputs

Hera 11. In the register of 18 iterations, the code combination is shifted by one position in the direction of the higher bits. The trigger 11 is reset and locks the counter 15, prohibiting further reading of the operands from the operational block 1 and the permanent memory block 20.

Record the remaining 3 bits of the operands in the arithmetic unit a.

(„

and a goes on for food K

cycles, after which the trigger 11 is activated by the counter overflow signal

17 meter outputs 15 and

16 and unlocks the counter 15. At the same time, the counter 16 is blinking with a signal from the output of the delay element 12. The trigger 10, to the counting input of which the overflow signal of the counter 16 is received, switches, closes the switch 13, opens the commutator 14, connects with a decoder

16 to the addresses of the blocks of groups 2 and 1 and through the switch 21 sets the last read and write modes, respectively.

This completes the first iteration of the FFT calculation. The remaining iterations are similar.

Claims (1)

Invention Formula one . A device for performing a fast Fourier transform containing four memory blocks, two switches, an arithmetic unit, a block of this memory, a block of AND elements, a first address counter and a shift register of iterations, the output of which is connected to the first input of the block of AND elements, an output which is connected to the first address input, the block of permanent memory, the output of which is connected to the input of the arithmetic unit coefficients, the transfer output of the first address counter is connected to the clock input of the iteration shift register, and The formation output of the first address counter is connected to the second input of the AND block, characterized in that, in order to simplify the device, it contains two flip-flops, a delay element, a second address counter, an address decoder and a third switch, the first to fourth outputs of which are connected to the inputs enable read-write memory blocks, respectively, from the first to the fourth information outputs of the first and second address counters are connected respectively to the first and second inputs of the address decoder, the first output is cat The op is connected to the address inputs of the first and second memory blocks, the outputs of the real and imaginary parts of the operand are connected respectively to the first, second, third and fourth information inputs of the first switch, the first and second outputs of which are connected respectively to the first and second the second outputs of the second switch and the first and second outputs of the results of which are connected to the inputs of the right and left parts of the operand of the information inputs of the first, second, third and fourth blocks of memory, the second output the address decoder is connected to the front-end inputs of the third and fourth memory blocks, the outputs of the real and imaginary parts of the operand of which are connected respectively to the first, second, third and fourth information inputs of the second switch, the control input of which is connected, is inpn with the first control input of the first switch and the L + 1 (L-bit operand) bit of the first address counter, the counting input of which is connected to the information input of the third the switch, the counting input of the second address counter, and is the clock input of the device; the bit outputs from the first to the Lth first address counter are connected to the inputs of the corresponding bits of the second address input of the permanent memory unit; the transfer output of the first address counter By connecting the input of the installation of the first flip-flop, whose output is connected to input addresses and input of delay element resolution first counter counting, the output of which is connected to a first control input of the third kommutato337904 pa ten and the enable input of the second address counter, the output of the higher bit of which is connected to the second control input of the third switch, the third control input of which is connected to the second control inputs of the first and second switches, the third input of the decoder and connected to the output of the second trigger, clock input which is connected to the clock input of the first trigger and connected to the transfer output of the second address counter. 15 25 2, The device according to claim 1, characterized in that the arithmetic unit contains two delay elements, mind and complex number generator, connected to the high-end subtractor of complex numbers and the adder of complex numbers, the output of which is connected to the input of the first delay element, whose output is the output of the first result of the block, the output of the second result of which is the output of the multiplier of complex numbers, the first and second inputs of which are connected respectively to the output of the second delay element and the output of 30 ND subtractor of complex numbers, the first and second inputs of which are connected respectively to the first and second inputs of the adder of complex numbers and are odes of the first and second operands block specifying input coefficients kotoro- n is input to the second delay element. 35 7904 pa 6 ten and the enable input of the second address counter, the output of the higher bit of which is connected to the second control input of the third switch, the third control input of which is connected to the second control inputs of the first and second switches, the third input of the decoder and connected to the output of the second trigger, clock input which is connected to the clock input of the first trigger and connected to the transfer output of the second address counter.  g / tg PhieZ