SU1608786A1 - Digital rejector filter - Google Patents

Abstract

The invention relates to radio engineering, in particular digital filtering, and can be used in signal processing to suppress periodic noise. The purpose of the invention is to increase the selectivity by increasing the degree of suppression of higher harmonics and increasing the dynamic range by reducing the level of intrinsic noise. A digital notch filter containing an analog-to-digital converter (A / D converter) 1, input register 2, first adder 4, sum register 5, memory block 6, memory register 7, output register 9, digital-to-analog converter (D / A) 10, and a control unit 11, a multiplexer 3 and a second adder 8 are introduced. On blocks 3 through 7, a "current average" filter is implemented, which is connected to the direct-connection circuit of the device. The multiply operation in it is replaced by a shift operation. The input signal is fed through A / D converter 1 and input register 2 to the input of the second adder 8, and through multiplexer 3 to the first adder 4. In the "current average" filter for N clock cycles, the value of the "current average" input signal is calculated, which is subtracted from the input value signal in the second adder 8. The result is fixed in the output register 9. The device can adjust the notch band by changing the number of calculation cycles for the "current average". 3 il.

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The invention relates to radio engineering, in particular to digital filtering, and can be used in signal processing for rejection of periodic interference.

The purpose of the invention is to increase the selectivity by increasing the degree of suppression of higher harmonics and increasing the dynamic range by decreasing the intrinsic noise.

FIG. 1 shows the structural electrical circuit of the digital notch filter; in fig. 2 - time diagrams, according to his work; in fig. 3 is a structural electrical circuit of the control unit.

Digital notch filter contains analog-to-digital converter (ADC) 1, input register 2, multiplexer 3, first adder 4, sum register 5, memory block 6, memory register 7, second adder 8i output register 9, digital-to-analog converter ( DAC) 10 and control block It.

The control unit 11 contains the first trigger 12, the element AND 13, the generator 14, the delay element 15, the ring shift register 16, the elements AND 17-19, the elements OR 20-25, the second 26 and the third 27 triggers, the first 28 and the second 29 counters and switch 30 strip notch.

Digital notch filter works as follows.

In the proposed filter, the integrating type of the digital filter is replaced by a fundamentally different, using the operation of calculating the current average, similar to the inertial type.

The current average is the arithmetic average between the current value of the function and the previous one, i.e. delayed in time for a constant period of time; With respect to time-sampled signals, the operation of calculating the current average can be expressed by a difference equation;

  (+) -0-5, where x (n) is the current sampling value;

 - sampling value averaged over the previous cycle;

N is the number of samples in the averaging cycle.

The filter using the operation of calculating the current average has a transfer function

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H (Z)

. 1-b-Z- where b - the smoothing factor is 0.5.

The essential advantage of such a filter is that the multiplication by the smoothing factor b 0.5 is reduced to a simple shift of the result code to the right by one bit, which does not require expansion of the arithmetic

5 device and reduces the processing time of the sample. The disadvantage is that the notch band at b 0.5 becomes quite wide. The reduction of the rejection band is achieved by repeating the operation of calculating the current average. Using the current average filter in a non-feedback circuit reduces the level of intrinsic noise to the level of the lower bit and eliminates the effect of changing the amplitudes and phase shifts of the higher harmonics of the input signal introduced by the low pass filter when the filter is tuned.

0 Digital notch filter is designed to suppress periodic harmonics containing a number of interferences. Therefore, it acts cyclically. The cycle time of the TC must be maintained equal to the period

5 following interference. A cycle is made up of repeating clock cycles (T0). The number of cycles in a cycle is determined by the number of harmonics to be suppressed in the signal processing frequency band. In synchronous mode

0 of the work, the ratio Tc N should be performed, where N is the number of ADC samples 1 (samples) per period of the suppressed signal.

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5, the nozzle filter is not required in its initial state.

During the cycle time, the signal sample is converted sequentially using an A / D converter 1 to K-bit binary.

0 code, calculation of the current average operation, consisting of the read operation from memory block 6, the summation of the contents of the memory cell with the sampling code in the adder 4, the write of the obtained sum back to

5 the same cell of the memory block 6, subtracting the result obtained from the signal sampling code, performed by the adder 8, and inverse conversion of the result code to analog form using a DAC 10,

0 At the input of the control unit 11 is supplied

sync pulses, the period of which is equal to To -.

At any of the N clock cycles, the synchronization pulse arrives at the input of the S-flip-flop 12 and sets it to state 1. At the same time, the resolving potential is fed to the first input of the And 13 element and the generator 14 is started. To the second input of the And 13 element

impulses from the generator 14 are received. Through a delayed ele1 / 1ent 15, the pulse sequence arrives at the input of register 16. In the initial state, at the output of its first bit 01, the resolving potential 1 arrives at the first input of the element I 1, and in the remaining bits O. At the second input of the element And 17, the first pulse arrives (Fig. 2 a, b), which passes to the output of the element And 17 and is used in the C of the pulse C1 for recording information in register 2. The pulse arriving at ((CW register 16 , sets O at the output) deO1 and 1 at the output of Q2. ohm only one of the forty-eight output} Q1-Q48 in the register 16 is present pot1} ntsial corresponding to logic 1. The output of AND gate 18 is forty-seventh pulse, the output of gate AND 1 $ - forty-eighth.

The pulses from the outputs of the AND 17-19 elements are sent to the corresponding inputs of the elements OR 20-25, to the set inputs of the trigger 26, to the contacts 30 of the notch band and to form signals controlled by the operation of the digital notch ztra The second (Fig. 1) 1- in the cycle, the input sample converted into a binary paging code at the previous clock cycle from the control unit 11 im C1 (Fig. 2c) is written to register 1 / ultiplexer 3 performed on logic elements 2I - OR, passes the code entered in register 2 to the second input 4. This same code arrives at the input of the adder 8.

netbook 29 sets the i-th address of the 6 memory location. The number of bits of the logaN counter. Counter 29, having P bit — where P 1od2K, K is the number of operations of the 1 st current average, per clock, set to the zero state by the previous clock. When entering K (Fig. 2d), in accordance with the time diagram on memory block 6, reading from the io memory cell recorded on the previous cycle, when C2 (Fig. 2d) appeared, this code was written to register 7 memory, register register 7, the code arrives at the input of the adder 4. After the completion of the addition operation, the result is shifted by one (half sum) by the SOC signal (Fig. 2h) to the sum register 5. According to the signal-VC and ZP (Fig. 2d and k), arriving at 6 memories from control block 11, the register from the register of 5 sums is written

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in the same 1 cell of memory block 6. Then, a pulse arrives at the counting input of the counter 29, which sets the next subaddress of the memory cells li. The signals VI and V2 5 (Fig. 2m and n), coming from the outputs of trigger 26, multiplexer 3 switches the second input of the adder .4 to the output of the register 5 of the sum (Fig. 2i).

The repetition of the operation of the current medium 10th is as follows. The signal B K (Fig. 2d) is fed to the block 6 of the memory; the code from the second cell, also recorded on the previous cycle, is read from the second cell. When a pulse appears (Fig. 2o) C2, this code is written to register 7 in memory register 7 in register 7 of memory (Fig. 2g). The output of memory register 7 is connected to the first input of the first adder 4, the output of which determines the result of addition 20 of the contents of cell ii recorded on the previous cycle and the contents of register 5 of the sums recorded in cell io and resulting from the previous addition. Upon receipt of the impulse SZ 5 (Fig. 2h), the result obtained is recorded with a shift of the code one digit to the right into the register 5 of the sum. Then, using the signals VK and ZP (Fig. 2d and k), the result from the sum register 5 is written into cell ii of memory block 0 6. When a pulse arrives at the input of the counter 29, the subaddress of the memory cell is changed, and the entire sequence of operations is repeated before writing to the cell with the address ia. Such a repetition occurs until 5 times until the counter 29 enumerates all the K subaddresss and the ring shift register 16 returns to the output state (Fig. 2 °, p, p, s).

The second input of the adder 8 receives the 0 value of the signal sample in the parallel binary code stored in the input register 2 during the cycle.

The first input of the adder 8 (Fig. 2o, p, p, c) receives the contents of register 7 of memory - 5 ti (Fig. 2l) in the reverse code to provide the subtraction operation in the additional code.

The difference code comes from the output of the adder 8 by the C4 pulse (Fig. 2t), coming from the control block 11, once per period to the register 9, is fixed in the register 9 (Fig. 2y). From the output of this register, the difference code is fed to the input of the DAC 10, the output of which restores the discrete-5-analog waveform.

The width of the notch band of the digital comb filter is determined by the magnitude of TC 2, where K is the number of calculations of the current average per cycle. A change in the notch band is achieved using a different part of the total number K from 1 to 5, since all the results of the calculations obtained at the previous clock cycle appear sequentially at the output of the register. 7 and, therefore, at the input and output of the second adder. input and accumulated signal, which corresponds to the selected notch band. Thus, the order band is switched by switch 30. having K positions. The signal processing is repeated on all the other clock cycles. When the cycles are repeated, a synchronous accumulation of the periodic component of the input signal occurs, the repetition period of which is equal to the cycle period, and the amplitude-frequency characteristic of the filter becomes comb-like. The degree of suppression of the periodic noise is 6 dB per conversion bit, the noise level corresponds to the least significant bit. .

F o rumula and 3 bbt 6 n and Digital Notch Filter containing an analog-to-digital converter, an input register whose input is connected to the output of an analog-digital converter, an output register, a digital-to-analog converter whose input is connected to output register output, serially connected first adder, sum register, memory block and memory register whose output is connected to the first input of the first adder, as well as a control unit whose input is a synchronous input of digital notch fil The first and the eighth outputs of the control unit are connected to the input inputs of the input register, the sum register, and the memory register. the output register and the control input, the write input, the first and second address inputs of the memory block, respectively, characterized in that, in order to increase the selectivity

by increasing the degree of suppression of higher harmonics and increasing the dynamic range by reducing the intrinsic noise, a multiplexer and a second adder are introduced, the first input and output of which

connected to the inverse output of the memory register and the input of the output register, respectively, and the second input of the second adder is connected to the output of the input register and the first input of the multiplexer, the second

the input and output of which are connected to the output of the sum register and the second input of the first adder, respectively, the first and second control inputs of the multiplexer are connected to the ninth and tenth outputs of the control unit, respectively, and the input and output of the digital notch filter are analog-digital input, the converter and the output of the digital-analog converter, respectively.

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Claims (1)

Claim A digital notch filter containing an analog-to-digital converter, an input register, the input of which is connected to the output of the analog-to-digital converter, an output register, a digital-to-analog converter, whose input is connected to the output of the output register, the first adder, the sum register, the memory block, and the register are connected in series memory, the output of which is connected to the first input of the first adder, as well as a control unit, the input of which is the synchronization input of a digital notch filter, and the outputs of the control unit I am connected from the first to the eighth to the recording inputs of the input register, sum register, memory register, output register and to the control input, recording input, first and second address inputs of the memory block, respectively, characterized in that, in order to increase selectivity by increasing the degree of suppression higher harmonics and increase the dynamic range by reducing intrinsic noise, a multiplexer and a second adder are introduced, the first input and output of which are connected to the inverse output of the memory register and the output output the register, respectively, and the second input of the second adder is connected to the output of the input register and the first input of the multiplexer, the second input and output of which are connected to the output of the sum register and the second input of the first adder, respectively, the first and second control inputs of the multiplexer connected to the ninth and tenth outputs of the control unit respectively, and the input and output of the digital notch filter are the input of the analog-to-digital converter and the output of the digital-to-analog converter, respectively.