SU1660131A1 - Synchronous rejection filter - Google Patents

Description

The invention relates to electrical engineering and can be used in selective devices to suppress interference. The purpose of the invention is to reduce the level of interference

2

quantization. Synchronous notch filter contains subtractive amplifier 1, controlled voltage divider 2, keys 3 and 5, integrators 4 and 6, switch 7, analog-to-digital converter 8 shift register 9, memory block 10. Accumulator 11 digital-analog converter! 2, pulse distributor 13 , clock generator 14, block 15 scaling. The principle of the filter is based on the synchronous accumulation of the interference compensation signal, whose frequency is equal to or a multiple of the notch frequency. followed by subtracting it from the input signal on the subtractive amplifier II. The filter according to claim 2 f-ly differs in the implementation of block 15, given its sludge. 1 hp ff, 5 ill.

Fig1

IV I GIPOOI

1660131

The invention relates to radio engineering

and can be used in selector

interference suppression devices.

The purpose of the invention is to reduce the level

quantization noise.

FIG. 1 shows a block diagram of a synchronous notch filter; in fig. 2 - timing charts of signals at the inputs and outputs of the pulse distributor; in fig. 3 - functional block diagram scaling; in fig. 4 - voltage diagrams at characteristic points of the synchronous notch filter circuit; in fig. 5 timing diagrams of signals explaining the operation of the scaling unit.

Synchronous notch filter contains subtractive amplifier 1, controlled voltage divider 2, first key 3, first integrator 4, second key 5, second integrator 6, switch 7, analog-to-digital converter 8, register 9, memory block 10, adder 11, digital-to-analog converter 12, a pulse distributor 13, a clock generator 14 and a scaling unit 15.

The scaling unit 15 constitutes the first element OR 16, the shift register 17, the shift counter 18, the EXCLUSIVE OR 19 element, the inverter 20, ϋ-flip-flop 21, the clock generator 22, the AND 23 element, the second OR element 24, the decoder 25, the mantissa register 26 and register 27 order.

The principle of the synchronous notch filter is based on the synchronous accumulation in the feedback circuit of the subtracting amplifier 1 of the interference compensation signal, which is a stationary (average) component of the input periodic noise whose frequency is equal to or a multiple of the notch frequency of the synchronous notch filter. In the process of subtracting the input noise is suppressed, and the useful signal passes to the output of the synchronous notch filter.

Synchronous notch filter works as follows.

An input voltage containing an additive mixture of the useful signal and interference with the fundamental harmonic frequency G _o is fed to the non-inverting input of the deducting amplifier.

The period of the main harmonic interference is divided into N time intvorvalov. Difference sginal during the 1st time interval is fed through the first key 3 to the input of the first integrator 4 (Fig. 4a). The second key 5 is in the open state. The output of the second integrator 6 (Fig. 46) stores the result of integrating the differential signal for the previous (I - 1) -th time interval. The voltage from the output of this integrator (Fig. 46) through the switch 7 is fed to the input of the analog-digital converter 8 (Fig. 4c).

After the analog-digital converter, register 9 records the contents of the (I - 1) -th cell of the memory block 10. The output codes of the analog-to-digital converter 8 and register 9 are fed to the inputs of the adder 11. The result of the summation is recorded in the (I - 1) -th cell of the memory block 10, and the second integrator 6 is reset.

During the 0 + 1) -th time interval, the difference signal from the output of the subtracting amplifier 1 through the second key 5 is fed to the input of the second integrator 6, the first key

3 is open and the first integrator

4 stores the value of the integral of the difference signal for the ίth time interval (Fig. 4a). After conversion and summation, the final result is recorded in the ΐy cell of memory block 10 (FIG. 4g).

Thus, integrators 4 and 6 alternately through the clock are connected to the output of subtractive amplifier 1. At each time, one of the integrators works in the integration mode, and the other in the storage mode of the integration result for the previous interval (Fig. 4h, and).

The operation of the functional units of the synchronous notch filter is controlled by signals from the corresponding outputs of the distributor 13 pulses, which is synchronized by pulses from the output of the clock generator 14.

FIG. 2 shows the voltage plots at the inputs and outputs of the distributor 13 pulses (a - clock pulses at the first input of block 13; b - read pulse of the scaling result; c - impulse to start analog-digital converter 8; d-control signals of the first key 3 and switch 7; d is the control signal of the second key 4; e is the pulse of writing the number to the shift register 17; w is the signal of the end of the analog-digital conversion; 3 and the reset signals of the first and second integrators 4 and 6, respectively; k are the signals at the address inputs of the memory block 10 ; l - impulse write the input code to the register 9; m signal of the operation of the operation of the memory block 10; n - control signal sampling of the memory block 10).

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The pulse repetition frequency P _{5 of the} clock generator 1 determines the frequency of tuning Ro of the synchronous notch filter and is related to it by the ratio

Ρ ₅ = Ν · _ο .

The frequency P ₅ and, consequently, the frequency Po are controlled by changing the signal at the input of the notch filter tuning frequency setting.

To reduce the quantization noise when restoring the analog waveform of the noise compensation, the codes stored in the cells of the memory block 10 are fed to the input of the digital-to-analog converter 12 after the corresponding converter in the scaling block 15. Scaling unit 15 converts input binary numbers with a fixed decimal point into floating-point numbers, with the mantissa being fed to the digital-to-analog converter 12, and the order to the controlled voltage divider 2. The effect of this is similar to reducing the error in performing computational operations for floating-point numbers as compared with the error for fixed-point numbers.

If there is interference in the input signal of the synchronous notch filter whose frequency is equal to or a multiple of the notch frequency, then after a certain period of time, corresponding to the steady state, the average discrete values of the interference compensation signal will accumulate in the cells of the memory block 10. This means that a signal is applied to the inverting input of the subtracting amplifier 1, which in form and phase corresponds to the input noise. Therefore, when subtracting, the input interference is suppressed. For signals whose frequency does not coincide with the notch frequency and is not a multiple of it, each interval falls on non-repeated random values of the input signal. When summing, these signals are added with different signs and their total value tends to zero. Therefore, such signals are not compensated and pass at the output of the synchronous notch filter.

Scaling unit 15 (FIG. 3) operates as follows (FIG. 4e).

At the beginning of the Ιth time interval, the content of the (I + 1) -th cell of the memory block 10 is written to the register 17 at the first input of the first element OR 16 at the positive edge of the pulse (Fig. 5a). By the same

the front of the counter 18 shifts is set to zero.

Using the EXCLUSIVE OR 19 element, the output signals of register 17 are compared, corresponding to the sign and most significant digits. If the number recorded in register 17 is smaller in absolute value, the units of the most significant digit will be the same at the outputs, for example, zero for a positive input number or one for a negative number represented in the additional code.

On the positive edge of the pulse at the output of the inverter 20 Ω-flip-flop 21 is set in one state. The level of the logical unit at the direct output of this trigger (Fig. 56) transfers the register 17 from the parallel recording mode to the sequential shift mode, and also permits the passage of pulses from the output of the generator 22 (Fig. 5b) through the And 23 element (Fig. 5d) to the clock input counter 18 shifts. Simultaneously, the pulses from the output of the element And 23 through the first element OR 16 are fed to the synchronization input of the register 17, In this case, the code in the register 17 shifts towards the higher bits. If, after the M-th shift, the modulo code value becomes equal to or greater than the high-order unit, then the output of the EXCLUSIVE OR 19 element is the level of the logical unit (FIG. 5e), which through the second OR element 24 sets the Ω-flip-flop 21 to the zero state. The logic zero level at the direct output of the Ω-flip-flop 21 prohibits further passage of pulses to the clock input of the shift counter 18 and the synchronization input of the register 17. The scaling process ends at the th time interval. The resulting shift of the output code of the register 17 is the mantissa of the input number of the scaling unit 15, and the output code of the shift counter 18 is its order. The order code is fed to the input of the decoder 25, which converts it into a positional code. The output codes of the register 17 th decoder 25 are served respectively to the information inputs of the register 26 of the mantissa and register 27 of the order. Information is recorded in registers 26 and 27 at the beginning of each time interval along the positive edge of a pulse (FIG. 5e) at the synchronization inputs of these registers (read input of scaling unit 15), and the result of scaling the number read in the ΐth time interval c (1 + 1) -1 cells of memory block 10, written and read from block 15

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scaling at the beginning of the (I + 1) -th time interval. >

If the number recorded in the Ιth time interval in register 17 is modulo or greater than the unit of the most significant digit, then this number does not shift, since the level of the logical unit at the output of the EXCLUSIVE OR 19 element prevents the switching of the E-trigger 21. In this In the case of a mantissa, the input number is equal, and the order is zero (Fig. 5g).

The maximum number of shifts carried out in block 15 scaling is determined by the number of inputs of the controlled voltage divider 2. If the input number of the scaling unit 15 is such that after the maximum number of shifts, its value continues to be less than one unit of the most significant digit, then the level of the logical unit at the highest output of the decoder 25 sets the O-flip-flop 21 to the zero state, which prohibits a further shift of the input number by given time interval.

The voltage of the output of the output digital-to-analog Converter 12 during the ί-th time interval

- m

O | VHTSAP ⁼ io ΝμΙ '2:

where and _o - the value of the reference voltage of the digital-to-analog converter 12;

Ν _Μ ι - the code of the mantissa of the number stored in the Ι-th cell of the memory block 10;

M - the digit capacity of the digital-to-analog converter 12.

The voltage at the output of the controlled divider 2 while

~ Νπί

and1outDUDPH - and | vyTsAP * 2 =

~ (Μ + Νπΐ)

= and ₀ ν _Μ ι -2

where Μηΐ is the order code formed by the result of scaling the compensation signal of the! -th time interval.

Therefore, the amplitude of the interference at the output of the synchronous notch filter due to the quantization error of the digital-to-analog converter varies within

Thus, as a result of scaling the compensation signal, the level of quantization noise at each time

interval is reduced compared with the known device, 2 ^Νπ times, and with a decrease in the level of rejected interference, the level of quantization noise decreases.

As follows from the description of the operation of the synchronous notch filter, the output of the controlled voltage divider 2 generates a signal, which in form and phase coincides with the input signal whose frequency is equal to or a multiple of the frequency of the synchronous notch filter. Therefore, the output of the controlled voltage divider 2 can be used as a selective output of the synchronous filter. The presence of the scaling unit 15 and the controlled voltage divider 2 allows to increase the dynamic range of the selective synchronous filter by 2 ^K , where K is the maximum possible number of shifts of the input number of the scaling unit 15.

Claims (2)

Claim 1. A synchronous notch filter containing a digital-to-analog converter, serially connected clock generator and pulse distributor, serially connected subtractive amplifier, non-inverting input and output of which are the input and output of the synchronous notch filter, the first switch, the first integrator and the switch, the second switch connected in series, the output of which is connected to the output of the detracting amplifier, and the second integrator, the output of which is connected to the second input of the switch, Successively connected analog-to-digital converter, the control input and output of which are connected respectively to the output of the switch and to the second input of the pulse distributor, an adder, a memory unit and a register whose output is connected to the second input of the adder, while the first to the tenth outputs of the pulse distributor are connected respectively to the control inputs of the first and second keys, the switch, to the synchronization inputs of the analog-digital converter and the register, to the reset inputs of the first and second integrators, to the input m sample input control operating mode and the address inputs of the storage unit, characterized in that, in order to reduce the level of quantization noise introduced scaling unit, a group of inputs and to the inputs of the read and write outputs which are respectively connected to the storage unit and eleventh and dve1660131 ten The eight outputs of the pulse distributor, a controlled voltage divider, the output of which is connected to the inverting input of the subtractor amplifier, are connected to the first inputs of the controlled voltage divider outputs of the digital-to-analog converter, to the digital inputs of which are connected the first group of outputs of the scaling unit, the second group of outputs connected to the second inputs controlled voltage divider. 2. Filter pop. 1, characterized in that the scaling unit contains a series-connected element OR, the first input of which is the input of the recording of the scaling unit, the shift register. The inputs are a group of inputs of the scaling unit, and 20 mantissa register, the outputs of which are the first group of outputs of the scaling unit, connected in series the exclusive OR element, to the inputs of which are connected the outputs of the higher shift register row, the second OR element, 0-flip-flop, the counting input of which is connected to the input records of the first element OR through the inverter, the element And, the first and second inputs of which are connected respectively to the input of the shift register and the output of the clock generator, the shift counter, to the counting in ode which is connected a first input of first OR, decoder, output the most significant bit 15 is connected to the second input of the second OR gate, and a register of order, and the clock inputs of which are mantissa registers readout input scaling unit, a second group of outputs which are of the order of the register outputs. FIG. 2 1660131 Fig.z 1660131 1660131