SU842911A1 - Device for compressing signal train - Google Patents

Description

(54) DEVICE FOR COMPRESSION OF SEQUENCE

SIGNALS

The invention relates to computing and can be used in telemetry systems, in particular, in systems for collecting and processing information about a scientific experiment to reduce the amount of information in the absence of a priori information about possible fluctuations of the process under study.

A known system for compressing and restoring information comprises a code filter made up of a series of serially connected addendum modulo two and convolutions, a transmission channel, a recovery device, and a buffer memory 1.

However, this system has a limited range of compression of the input binary sequences, i.e. compression is possible under the condition that the neighboring "words of the original sequence differ from each other by no more than bits (k is the width of the original" words).

The closest in technical essence and the achieved result to the proposed is an adaptive device for compressing analog signals, containing a comparator, the output of which is connected to the input of an adaptive three-level quantizer (analog-digital converter) connected to the inputs of a long-series encoder and an interpolator whose output is connected with one of the inputs of the comparator 2.

This device has a low reliability of the processing of arbitrary sequences, which is caused by the dependence of the magnitude of the quantization error on the interpolation algorithm, it is also possible the appearance of large errors.

The purpose of the invention is to expand the field of application of the device by compressing arbitrary sequences of signals and increasing the reliability of the processing result.

The goal is achieved in that a device consisting of a comparator, one input of which is connected to the interpolator's output, and an output to the input of an analog-digital converter, the output of which is connected to the input of the interpolator, and a long series coder, has been entered into counters, the first group of elements And, the first manager

key, second group of AND elements, second control key, cyclic shift registers, OR element, ring interrogation counter, binary interrogation counter, code comparison block, first buffer register, multiplexer, storage register, second buffer register, third group of AND elements, generator codes, delay element, mode trigger, clock generator, decipher device, the input of which is connected to the output of the analog-digital converter, and the outputs are connected to the removable inputs of counters and the first inputs of the first group of elements And, to the second inputs of which the output of the first control key is connected, combined with the synchronization input of the long series encoder, the outputs of the first group of elements AND are connected to the shift inputs of cyclic shift registers, the outputs of the sequence bits of which are connected to the inputs of the element OR, the output of which is connected to the input a long series encoder, the output of the second control key is connected to the clock input of the code comparison unit, to the counting inputs of the binary interrogation counter and ring interrogation counter, the outputs of which are connected to the D-inputs of the first buffer register and to the second inputs of the multiplexer, to the first inputs of which the bit outputs of the counters are connected, and its outputs are connected to the first inputs of the code comparison unit and to the D-inputs of the memory register, the outputs of which bits are connected to the second inputs a code comparison unit, the output of which is connected to the write inputs of the memory register, the first and second buffer registers; to the D-inputs of the second buffer register are connected the outputs of the binary poll counter, the bits of the first and. the second buffer registers are connected respectively to the first inputs of the second and third groups of elements And, to the second inputs of which are connected the output of the last bit of the polling ring counter, which in turn is connected to the R input of the storage register and to the input of the delay element whose output is connected to the counting the input of the code generator, the outputs of the bits of which are connected to the D-inputs of cyclic shift registers, the outputs of the second group of elements And are connected to the R inputs of the counters and the outputs of the "Record cyclic shift Registries, outputs of the third group of elements I are connected to the device output currents, the output of the last digit of the code generator is connected to the first input of the mode trigger, the second input of which is connected to the control input of the device, the outputs of the mode trigger are connected to the first inputs of the first and second control key, whose second inputs are connected to the generator. mountain clock pulses.

A generalized diagram of a device for compressing information is shown in the drawing.

A device for compressing a message sequence consists of a comparator 1, whose input 2 is connected to the output of interpolator 3, and the output to the input of a / C-bit analog-digital converter of the A / D converter 4, the output of which is connected to the input of the interpolator 3 and input 5 of the precoder 6, which consists of / (- bit decoder 7, outputs 8 of which are connected to counting inputs 9 g-bit counters 10 and first inputs 11 of the first group of elements And 12, consisting of 2 elements, to the second inputs 13 of which output is connected first control key 14, and the outputs of the first group of elements 12 are connected to the shift inputs 15 / (of the cyclic shift register registers 16, the outputs of which are connected to the inputs of the element OR 17, the output of the second control key 18 is connected to the counting inputs of the 2K-ring ring polling counter (CS) 19 and / (- polling binary counter 20 to the clock input of the g-bit code comparison block 21); the CS outputs 19 are connected to the D inputs of the 2K bit first buffer register 22 and to the second the inputs of the 23 multiplexer (M) 24, since the first inputs of the 25 kotor oh the outputs of the bits of the meters 10 are connected; the outputs of M 24 are connected to the first inputs 26 of BSK 21 and to the D inputs of a large storage register 27, the outputs of which bits are connected to the second inputs 28 of the code comparison unit 21 having an output 29, the signal which appears, if a binary number is the first inputs 26 are larger than the binary number on the second inputs 28.

The output 29 is connected to the input “Record 30 of the holding register 27, to the input“ Record 31 of the first buffer register 22 and to the input “Record 32 of the second buffer register 22, to the D-inputs of which are connected the outputs of the binary 20 poll counter.

The outputs of the bits of the first buffer register 22 and the second buffer register 33 are connected respectively to the first inputs of the second and third groups of elements 34 and 35. The output “Transferring the ring counter 19 of the poll is connected to the second inputs of the group of elements 34 and 35 and the R input 36 of the storage register 27, as well as to the input of the delay element 37, the output of which is connected to the input of the generator 38 codes, the outputs of the bits of which are connected to the D-moves 39 of the cyclic shift register 16, and the output “Transfer of the generator 38 codes connected to the R-input of the mode trigger 40, P rvy output 41 which is connected to the first input of the second switch 18, and the inverted output 42 is connected to the first input to the first switch 14. The second input keys 18 and 14 connected to the generator output 43 of clock pulses. The S-44 44 mode trigger 40 is connected to the control bus. The outputs 45 of the third group of elements And 35 are connected to the output buses of the device, the output of the element OR 17 is connected to the information input 46 of the encoder 47 long series, and the output of the key 14 is connected to the clock input 48 of the encoder 47 long series. A device for compressing a sequence of messages operates in two modes: compression mode and retraining mode. Mode switching and device operation control is performed at input 44. In the measurement mode, the mode trigger 40 is set to zero, and N 2 consecutive samples of the measured signal HpN to the input 2 of the comparator 1 are fed into the output and the predicted value of the interpolator 3 output .l Error, the value of which, -Xf ,, from the output of comparator 1 is fed to the input of ADC 4, which digitizes it with the discharge code lin, and 1, l (-2-), where E is the recovered error value; L-step quantization of the ADC. The code from the output of the A / D converter 4 is fed to the input of the interpolator 3, which, from the T preceding reconstructed signals Xc- (1: 1.2 ... J), generates the predicted value Xn and supplies it to the input 2 of comparator 1 in the next measurement n + 1. The error signal is fed to the input 5 of the decoder 7, at output 8 of which a positive edge appears, entering the counting input 9 of the corresponding counter 10. The resolving potential from the output 8 of the decoder 7 is fed to the first input of the 11th element of the first group of elements And 12 In mode the first control key 14 is open, so the i-th element 12 passes a burst of K pulses from the output of the key 14 to the shift input 15 of the i-oro shift cyclic register 16 and sends the VL code recorded in it through the OR element 17 to the input 46 coder 47 follower Nost signals. At the same time to the clock input 48 of the encoder 47 of the sequence of signals from the output of the key 14 receives the clock pulses. Encoder 47 of a long series encodes a sequence of symbols according to the rule: Before the start of the measurement, counter 10 is reset, after N measurements in the i-th counter 10, the number of EL errors is written in binary form. The preparation mode is carried out after the first N measurements by applying a signal;) on control bus 44 to the 5-volt trigger signal 40 mode and setting it to "1. Key 14 closes. The key 18 is opened, and from its output clock pulses are received from the generator 43. The clock pulses arrive at the counting input of the binary counter 20 of the poll. to the sync clock input of the code comparison unit 21 and to the counting input of the polling ring counter 19, which in turn connects the values through the multiplexer 24 to the first inputs of the code comparison unit 21. Before connecting the register 27 is reset. If φ is not greater than the value recorded in register 27, then its content after the comparison clock is saved, otherwise, at the output 29 of the code control block 21, a single signal appears that writes the code of the outputs 24 into the storage register 27, i in unitary the code from the polling ring counter 19 - to the first buffer register 22, i in binary code-- from the binary polling counter 20 to the second buffer register 33. Thus, by the end of the 2-clock polling cycle, in the binary polling counter 20 i-error number recorded, repeated with most of all, and the first buffer register 22 - i-number errors in a unitary code. At the moment when the polling pulse passes, the transfer signal appears at the high bit 19 output of the ring interrogation counter, which zeroes the memory register 27 and enters the second inputs of the third group of elements 35, issues the i B code on the output buses 45, enters through the open register 22 and element 34 to the input of the record cyclic shift register 16 and the input of the counter 10; the cyclic shift register 16 records the contents of the 38 code generator, and the counter 10 is reset. The same pulse arrives at the input of the delay element 37, which delays it at the time of cyclic shift register 16 and then sends it to the counting input of the tener ;:. Оor 38 codes and sets the code V on it. Where j is the number of the polling cycle . The code generator 38 converts a sequence of counting pulses j received at its input into a sequence of unequal parallel codes i V; no to the rule: each code is not less than one than the previous code VV (j 1,2 ... 2). After 2 such cycles, a sequence {H (j) of interpolation errors is distributed to the output buses, distributed

in descending frequencies of their repetitions, each i-OM cyclic shift register 16 records the corresponding error code Vj, and the more often the error tit occurs, the more zeros in the code Vj (according to the operation rule of the 38 code generator).

Therefore, a zero in the sequence arriving in measurement mode at the information input 46 of the long series encoder 47 is more likely, regardless of the frequency distribution ("tweeter. This allows compression of the long series by the encoder 47.

With a sufficiently large number of samples of the input signal N, after which a preparatory cycle of error repetition is carried out, p is approaching the value of PJ. (Pi is the prediction probability with error P). ,

Thus, in the sequence at the input of the coder of 47 long runs, the code 0000 ... 0 is most often encountered. Since it corresponds to a probable ELI error regardless of its magnitude, the next in code for the 47 long series code is 00 ... 01 and the least likely code is 11 ... 11.

The interpolation error distribution Ei (j) does not change for the same input process, so the compression effect is achieved regardless of the degree of correspondence of the interpolation algorithm to the process under investigation.

The information recipient knows the sequence of codes {Vj, generated by the code generator 38, and the sequence. i arrives during the preparatory cycle.

Thus, from the sequence {Wl from the output of the encoder 47 long runs, the sequence

{Y (n), and then the sequence

()}

Since the prediction algorithm is also known, the sequence Xn is restored from the sequence {fi (n)} and the initial condition X (0) Xo}.

The advantages of the proposed device are due to the independence of the accuracy of signal conversion from the interpolation algorithm while maintaining the compression effect.

Claims (2)

Invention Formula A device for compressing a sequence of signals containing a comparator, one of the inputs of which is connected to the interpolator's output, and the output to the input of an analog-digital converter, whose input is connected to the input of the interpolator, and a long-series encoder, characterized in that application areas of the device by compressing arbitrary sequences of signals and increasing the reliability, counters are entered into it, the first group of elements is And, the first control key, the second group of AND elements, the second control key, cyclic shift registers, the OR element, the ring polling counter, the binary polling counter, the code comparison unit, first buffer register, multiplexer, storage register, second buffer register, third AND group, code generator, delay element, mode trigger, clock pulse generator, decoder whose input is connected to the analog-digital converter output, and outputs are connected to the counter inputs of counters and the first inputs of the first group AND, to the second inputs of which the output of the first control key is connected, combined with the Synchronizing input of the long series encoder, the outputs of the first group of elements AND are connected to the shifts m inputs of cyclic shift registers, the outputs of the last bits of which are connected to the inputs of the OR gate, the output 5 of which is connected to the input of the long series encoder, the output of the second control key is connected to the clock input of the code comparison unit, to the counting inputs of the binary interrogation counter and ring interrogation counter, the outputs of which 0 are connected to the D-inputs of the first buffer register and to the second inputs of the multiplexer, to the first inputs of which the bit outputs of the counters are connected, and its outputs are connected to the first inputs of the code comparison unit and to the D-inputs of the memory register, the outputs of which bits are connected to the second the inputs of the code comparison block, the output of which is connected to the recording inputs of the memory register, the first and second buffer registers; The D-BXOQ dam of the second buffer register is connected to the outputs of the binary poll counter, the bits of the first and second buffer registers are connected respectively to the first inputs of the second and third groups of elements AND, to the second inputs of which 5 connects the output of the last bit of the polling ring counter, which is connected to the R input of the memory register and to the input of the delay element whose output is connected to the counting input of the code generator, whose discharge inputs are connected  to D-inputs cyclic shift registers; the outputs of the second group of elements And are connected to the R-inputs of the counters and the outputs "Record cyclic shift registers, the outputs of the third group of elements 5 And connected to the output device's folders, the output of the last bit of the code generator is connected to the first input of the mode trigger, the second input of which is connected to the control input of the device, the outputs of the mode trigger are connected to the first inputs of the first and second control keys, the second inputs of which connected to a clock pulse generator. Sources of information taken into account in the examination 1.IEEE Int. Conf. Commun., San Francisco Vol 3, New York, 1975, p. 26-29. 2. USSR author's certificate number 437070, cl. G 06 F 7/22, 1971 (prototype).