SU653743A1 - Decoder - Google Patents

Description

The invention relates to decoding devices and can be used in communication systems with the temporary compression of telegraph signals.

A decoding device is known comprising a clock generator, two counters, two registers, gating and comparison units.

However, this device does not provide decoding of signals that are converted using a sliding index method with acknowledgment I,

A device for decoding telegraphic signals converted by a sliding index method is known, containing an input n-bit shift register, a clock generator, a generator (n-1) of bit code combinations of the transition time position, a code match decoder, a C element and a one-bit register shift, decoding on the principle of start-stop synchronization, based on the fact that the code combinations indicating the presence of a transition in a telegraph signal begin with a pulse, we call start and having a constant value - one.

However, such a device also does not provide decoding of signals converted by a sliding index method with confirmation 2.

The aim of the invention is to provide decoding of a digital telegraph signal converted by a sliding index method with confirmation.

This is achieved by the fact that in a decoding device containing an n-bit shift register, the first input of which is connected to the input width of the device, and the output is connected to the first input of the single-bit shift register, a clock generator, the output of which is connected to the control input of the shift shift register and with the input of the generator (n-1) -discharge code combinations of the temporary transition position, (n-) whose outputs are connected to the first group (n-1) of the decoder's inputs, the second group (n-1) of the inputs of the latter is connected with outputs (p-1) cells p-razr One register, and the output of the decoder is connected to the first input of the AND element, additionally

modulo 2 adder and the control unit of the n-bit shift register are entered. The first and second inputs of the modulo-2 adder are connected respectively to the first input and output of the one-bit shift register, the second input of which is connected to the output of the And element and to the control enable input of the control unit of the n-bit shift register. The control input of the latter is connected to the output of the n-bit shift register, and the first and second outputs with the installation buses in the "1" and "O n-bit shift register. The output of the modulo 2 adder is connected to the second input of the element I.

FIG. 1 shows a block diagram of a decoding device; in fig. 2 - time diagrams, according to his work.

The decoding device contains an input p-bit shift register 1, the signal input of which is the device input, a one-bit shift register 2, whose input and output signals are fed to the input of modulator 2 modulo 2, a clock frequency generator 4, the output of which is connected to The input of the register 1 and the generator input are 5 (n-1) -discharge code combinations of the transition time position, (n-1) whose outputs are connected to the (n-1) inputs of the decoder 6 corresponding to the code combinations, the rest ( ) the inputs of the decoder b connection s with the output and the corresponding (p-1) register cells 1, the output of the decoder 6 is connected to the input of the element I 7, the second input of which is connected to the output of the adder 3, the output of the element 7 and 7 is connected to the control input of the register 2 and c. The control resolution of the shift register setting control section 8, the second input of the node 8 is the control input and connected to the output of the register 1, the outputs of the node 8 are connected to the corresponding buses 9 and 10 of the installation in "O and" 1.

The device works as follows,.

The input signal converted by the sliding index method with confirmation (Fig. 2a) is fed to the signal input of register 1 and is sequentially recorded in register cells 1 by clock pulses (Fig. 26) generated by generator 4.

The signal from the output of register 1, which is the input signal for register 2, and the signal from the output of register 2 are compared by adder 3. At opposite values of the compared signals, at the output of adder 3 appears "1 (Fig. 2d), the opening element And 7. The code pattern generator 5 sequentially generates the code combinations of the transition time position, which bitwise by the decoder 5 are compared with those written in (n-)

register cells 1. At the moment of identification, an impulse is produced (Fig. 2c), the temporary position of which corresponds to the specified alphabet of the transition code. If two-bit encoding of the transition time position is used between clock pulses, one of the alphabets may be the following: 00 - I quarter, O - And quarter, 10 - P quarter, 11 - IV quarter. In the FIG. 2

example, the code combinations of the input signal correspond to I n P quarters). This pulse arrives at the other input of the element And 7, and at the time of the coincidence of the pulses (Fig. 26 and Fig. 2d) a pulse is formed (Fig. 2e). incoming, as a forwarding to the control input of register 2 for recording the change of state in the telegraph signal (Fig. 2e) and as a permission to control the input of the register setting control unit 8. To the second input

node 8 receives a pulse from the output of register 1, and depending on the polarity of this pulse ("O or" 1), the corresponding signals appear on lines 9 or 10. Thus, all the cells in register 1 are in the same state. At the output of register 2, which is also the output of the decoding device, there is a reconstructed telegraph signal (Fig. 2e).

Claims (2)

1. USSR author's certificate number 321944, cl. H 03 K 13/258, 1970. 2.Fefnmeldetechnik, 1971, No. 7, S 213-214 .DDR.