SU756614A1 - Noise generator - Google Patents

Description

The invention relates to the field of measurement technology and is intended to obtain stationary noise signals, 5

Known noise generator, containing a 20-bit shift register, clocked generator clock pulses; resistors are connected to all cells of the register *; they form a pre- | {forming filter and are connected to summing devices that are connected to a low-pass smoothing filter; the inputs of the register cells receive signals from the other cells of the ^ 5 register or from the outputs of adders modulo '’, the inputs of each of which receive signals from the outputs of the two other cells of the register; random signal is obtained by the result - 20

summation of the number of logical units in all bits of the register [1]:

However, since the summation, absolute values of ~ 25 logical level levels are subject to summation, which have a large variation when moving from a sample to a sample and are influenced by destabilizing factors, such a device requires

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individual selection of weight resistors, which leads to a decrease in the manufacturability of the device, and does not provide a high stability of the average value of the output voltage.

The closest in technical essence and essential features to the proposed is a noise generator containing a U-bit shift register, in the feedback circuit of which the modulator ¹¹ 2 ″ is included to receive the Ν-sequence, and the setup input of the register is connected to the output of the initial setting device states; weight summing resistors connected to the outputs of the register bits are also connected to the input of the summing amplifier; register shift is carried out using a clock generator .; the noise signal is obtained as a result of summing by the summing amplifier of the number of ~ logical units in all bits of the register [2],

Such a generator has a binomial amplitude distribution of the output voltage. Increasing the number of digits

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the shift register brings the distribution closer to the nominal one.

The maximum number of bits of the shift register is determined based on the fact that the contribution of one of the bits to the voltage output must be greater than the instability of the latter. The use of highly unstable output levels of logic circuits to form the output signal allows the use of only small-bit registers, which makes it difficult to obtain a normal law of noise amplitude distribution.

The purpose of the invention is to increase the degree of approximation of the distribution of the amplitudes of the noise to the normal law.

The goal is achieved by the fact that a device containing an I-bit shift register with a modulo "2" adder in the feedback circuit, the setup input of which is connected to the initial state bus, a clock generator whose output is connected to the synchronization inputs of the shift register, and a low pass filter whose output is an output device, further administered a second adder 'modulo' * ¹ 2 ¹ item and · reversible counter, adjusting input of which is connected to the adjusting input of the shift register n ,, froanalogovy converter, a capacitor and a buffer device, wherein the output of AND - 1 bit of the shift register is connected to one of the outputs of the second adder modulo 2 and to the input of subtracting the down counter, the input of addition is connected to the output of the first adder modulo '' 2 * ¹ and the input second adder unit ¹¹ for 2 '· whose output is connected to one input of aND IE, the other input of which is connected to the output sync generator, and its output connected to the input synchronization-down counter, bit rows to The yields orogo connected 'to corresponding inputs of a digital to analog converter, the output of which through a capacitor and a buffer device connected to the input of a lowpass filter.

The drawing shows a structural diagram of the proposed generator.

The generator contains a shift register 1 with adder 2 modulo "2" in the feedback circuit. The synchronization input of the shift register 1 is connected to one of the inputs of the element And 3 and the output of the clock generator 4. Output 5 And -1 discharge of the shift register 1 is connected to the subtraction input 6 of the reversing counter 7 and one of the inputs of the second adder 8 modulo "2" the output of which is connected to the synchronization input 9 of the reverse counter

7. ' The second input of the second adder 8 modulo "2 *" is connected to the input of the addition of 10 reversible counter 7 and the output of the first adder 2 modulo ¹ 2 ' ¹ . The discharge outputs of the reversible counter 7 are connected to the corresponding inputs of the digital-to-analog converter 11, the output of which is through a coupling capacitor 12, a buffer device 13 and a low-pass filter 14 connected to the output bus 15 of the generator.

The installation inputs of the shift register 1 and the reversible counter 7 are connected to the bus 16 to set the initial state.

The device works as follows.

Before starting work, bus 16 receives a setting impulse, which writes a certain number (not equal to zero) of logical ’’ ’1’ ’into shift register 1 and returns the reversing counter 7 to the initial state

In accordance with the state of the reversible counter 7 at the output of the digital-to-analog converter 11, a certain constant voltage level is established, which is separated from the output of the bus. 15 separation capacitor 12.

If absent 5 And - 1 bits of the shift register 1 is a logical '' 1 '', input to the subtraction input b of the reversible counter 7, and the output of the adder 2 modulo! '2' ¹ is the logical ¹ '0'', then the output adder 8 modulo '' 2 '' is set to logical ¹ '1''. In this case, the leading edge of the pulse from the clock generator 4, having passed ίβρθ3 element 3, enters the synchronization input 9 of the reversible counter 7. The back edge of the pulse of the generator 4 shifts the register 1 and changes the state of the reversing> counter 7, and the number of logic

'' 1 '', recorded in bits of register 1, and the number in the reversible counter 7 will decrease by one.

If the output 5 And - 1 of the shift register 1 is a logical '' 0 ' ¹ , and the output of the adder 2 modulo''2''is the logical''1'', which is fed to the addition input 10 of the reversible counter 7, then The output of the adder 8 modulo ¹ '2 "' is also set to logical '' 1 ''. The front edge of the pulse from the clock generator 4, passing through the element 3, enters the synchronization input 9 of the reversing counter 7. The back edge of the pulse of the generator 4 shifts the register 1 and changes the state of the reversing counter 7, and the number of logical '1''recorded in register bits 1, and the number in the reverse counter 7 increases by one. If at the exit 5 c - 1 discharge5

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yes, the shift register 1 and the output of the adder 2 modulo 2 '2 ’' are set to the same values of logic variables, the output of the adder 8 modulo '‘ 2 *' is set to logical '' 0 ''. In this case, the pulse of generator 5 to the synchronization input 9 of the shift register 1 through the element 3 does not arrive, but produces a shift of register 1. However, the number of logical ’'1' 'recorded in the bits of register 1 does not change.

Thus, as the clock pulses from generator 4 arrive, the change in the number of logical '' Ι ¹ 'recorded in the bits of the shift register corresponds to the change in' ³

the number recorded in the reversible counter 7, and the corresponding voltage level at the output of the digital-analog. At its sufficiently large value of the constant 20 of the time of the circuit, the capacitor 12 is a buffer device 13, the change in voltage at the output of the digital-to-analog converter 11 is completely fed to the low-pass filter 14, generating 25 a noise signal at its output.

To ensure reliable operation of the generator of the number of digits of the shift register 1, a slightly smaller number of the state of the reversing counter 7 can be selected. Then the pulse of setting the initial state from the bus 16 and the reversing counter 7 should record a number slightly larger than the number of logical records written to the shift register 1. in the case of malfunction of the shift register 1, resulting in a mismatch number of logical ^'1 1 ^1' in the register I and the state counter 7, the displacement of the mean value produced SLE aynogo voltage eliminates the coupling capacitor 12.

The use in the proposed device of the second modulo ⁴³ '' 2 '' adder, the reversible counter, the digital-analog converter and the buffer device allows replacing the operation of summing up the number of logical 'сд ¹ ' located in the shift register in the 50th register, which is implemented in digital form with the subsequent conversion of the result of summation to analog value. Due to this, the instability of the output levels of logic circuits does not affect the stability of the output voltage, which makes it possible (to improve the quality of the generated random signal by simply increasing the number of digits of the shift register.

In addition, the possibility of digital "processing of information from the shift register eliminates the need to use selectable weight resistors.

However, since in the proposed generator there is no need to remove information from each digit of the shift register, as the latter, dynamic-type microcircuits with a high degree of integration can be used.

Claims (1)

Claim A noise generator containing an AND-bit shift register with a modulo ¹¹ 2 ^G 'adder in the feedback circuit, the setup input of which is connected to the initial state bus, a clock generator whose output is connected to the shift register synchronization inputs, and a low-pass filter, output which is the output of the device, which is due to the fact that, in order to increase the degree of approximation of the noise amplitude distribution to: normal law, a second modulo “2”, the element And, the reversible counter, is entered into it, · Whose installation input is connected to the installation input of the shift register, digital-to-analog converter, capacitor and buffer ³³ device, and the output And - 1 digit of the shift register is connected to one of the inputs of the second modulo ¹ '2''adder and with the subtraction input of a reversible counter, слож the addition input of which is connected to the output of the first modulator' ¹ 2 '' and input the second adder modulo 2, the output of which is connected to one of the inputs of the element And, the other input of which is connected to the output of the clock generator, and the output is connected to the synchronization input of the reversible counter, the bit outputs of which are connected to the corresponding inputs of the digital-and-digital transducer whose output is through a capacitor and a buffer device is connected to the input of a low-pass filter.