JP2874875B2 - Analog signal delay circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog signal delay circuit.

[Prior Art] As a conventional analog signal delay circuit, an analog signal is written to a charge transfer element using a BBD (bucket brigade type element) or the like, and the output is read at a timing delayed by T time from the write, so that the T time is obtained. The system takes out the delayed analog signal.

[Problems to be Solved by the Invention] In this case, there are problems in frequency characteristics and S / N ratio, and in addition, it is difficult and expensive to implement a circuit as a MOS-LSI.

SUMMARY OF THE INVENTION An object of the present invention is to provide an analog delay circuit which can increase the dynamic range of an analog input signal, is less affected by noise, is suitable for MOS-LSI, and is inexpensive.

[Means for Solving the Problems] In order to achieve such an object, the present invention provides an analog signal having a frequency of several tens of times or more the frequency of the analog signal.
Δ サ ン プ リ ン グ -type AD converter means sampling at fs to form a 1-bit digital signal, and a series of 1-bit digital signals formed and output by the ΔΣ-type AD converter means are written to a memory at the same frequency as the frequency fs, A memory control means for temporarily holding and reading, and a two-bit digital signal of a series of one-bit digital signals read out.
Binarizing means for performing binarization, and filter means for removing a high-frequency component of an output from the binarizing means and extracting an analog signal delayed by a time difference between writing and reading in a memory control means for a 1-bit digital signal. It is characterized by having.

[Operation] According to the present invention, by using a ΔΣ AD converter, the circuit is less susceptible to noise and the entire circuit is MOS LS
It is also suitable for I.

[Example] Hereinafter, an example of a thick invention will be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, and FIGS. 2 (A) to 2 (D) show examples of signal waveforms at respective portions thereof.

In FIG. 1, reference numeral 10 denotes a ΔΣ AD converter which receives an analog input signal (A) as shown in FIG. 2 (A) and receives an analog input signal (A) as shown in FIG. 2 (B). A pulse signal (B) having a duty ratio proportional to the amplitude of (A) is obtained.

The ΔΣ AD converter 10 itself has a known configuration, where 11 and 12 are operational amplifiers, 13 and 14 are adders, 15
And 16 are feedback capacitors for the operational amplifiers 11 and 12, 17 is a comparator, 18 is a D-type flip-flop, 19
Is a 1-bit DA converter.

The adder 13 has an input analog signal (A) and a DA converter
19 and the output from the operational amplifier 11
To the negative input terminal of The adder 14 has an operational amplifier 11
And the output from the DA converter 19 are supplied, and the added output is supplied to the negative input terminal of the operational amplifier 12. The positive input terminals of the operational amplifiers 11 and 12 are connected to the analog ground potential. The comparator 17 compares the output from the operational amplifier 12 with the analog ground potential, and outputs “1” when the output is larger than the analog ground potential, and outputs “0” at other times. The binary input “0” or “1” from the comparator 17 is supplied to the data input terminal of the flip-flop 18,
Similarly, a clock pulse fs having a frequency of several tens of times or more the frequency of the input analog signal (A) is supplied to the clock input terminal, and a comparator 17 is provided at the rising edge of the clock pulse.
The data “0” or “1” from the The output of the flip-flop 18 is supplied to a 1-bit DA converter 19, where a predetermined voltage such as -1V for "1" and + 1V for "0" is generated. The analog output is fed back to the operational amplifiers 11 and 12 via adders 13 and 14 as differences, respectively. Thus, a new incoming analog signal is differentiated by an analog amount corresponding to the immediately preceding digital data, and then integrated.

In this manner, the first input analog signal (A) is sampled at high speed by the clock pulse fs, and as shown in FIG. 2 (B), the 1-bit digital output (B)
It is converted and taken out.

This digital signal (B) becomes a pulse train with a duty ratio proportional to the amplitude of the analog signal (A). However, since the flip-flop 18 operates with the clock pulse fs, the pulse width of such digital output is 1 / fs (second)
It takes only a value that is an integral multiple of, and is a digitally discrete quantity. That is, as shown in FIG.
The duty ratio changes according to the amplitude and polarity of the analog signal (A), and the duty ratio is lower when the input is in the negative direction than when the input is in the positive direction. When the amplitude is zero, that is, when there is no signal, the duty
The ratio is 50%.

As described above, the digital output obtained by converting the input analog signal into a 1-bit digital signal by the ΔΣ AD converter 10 is used in the present invention to control the ΔΣ AD converter 10 under the control of the control logic circuit 40. The address is changed at the same frequency as the sampling frequency fs, the data is written to the memory 41, temporarily stored, and then read at a timing delayed by T time from the write (see FIGS. 2B and 2C). ). Memory 41 is a normal RA
It can be composed of M, FIFO (first in first out) register or shift register.

When the RAM is used, the memory address is sequentially read from 0 to N−1, and when the memory is circulated so as to perform writing, the delay time T becomes T = N / fs.
Can be changed to obtain an arbitrary delay time.

When a FIFO register or a shift register is used, the delay time is determined by their depth and the sampling frequency fs.

The digital output read out at the timing delayed by the time T under the control of the control logic circuit 40 is binarized through the binarization circuit 20, and then passed through the low-pass filter 30 to remove high-frequency components (FIG. 2). D)
The first input analog signal can be reproduced as shown in FIG.

The low-pass filter 30 may be configured as a passive filter using CR or an active filter using CR and an operational amplifier.

Further, as a feature of the present invention, this low-pass filter can be directly constituted by a switched capacitor filter without inserting an anti-aliasing filter.

It switched capacitor filter, so that processing by sampling the input data by the sampling clock f _CLK, folded back (integral multiples of f _CLK) as pass band signal in the frequency band of ± (the passband of the filter) . Therefore, in the method using the conventional charge transfer device, the width of the output pulse is arbitrary, and the frequency spectrum may spread over the entire band, and the components of the entire band are folded. A low-pass filter for prevention is inserted before the switched-capacitor filter to cut off the higher band than the pass band. In contrast, in the present invention, set equal to the sampling clock f _CLK frequency fs and the switched capacitor filter of the sampling clock of the AD converter 10, and define sufficiently high the frequency for the passband. Frequency spectrum of the output (B) of the AD converter 10, because no frequency fs, i.e. energy in integer multiples vicinity of f _CLK, the present invention, there is no need to pre-folded filter.

[Effects of the Invention] As is clear from the above, the present invention uses a ΔΣ type AD converter, unlike the conventional method using a charge transfer element, is less susceptible to noise, and makes the entire circuit a MOS LSI. It is also suitable to be used, and is inexpensive.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a signal waveform diagram of each part for explaining the operation. 10 …… ΔΣ type AD converter, 11,12 …… Operational amplifier, 13,
14 Adder, 15, 16 Capacitor, 17 Comparator, 18 D-type flip-flop, 19 DA converter, 20 Binarization circuit, 30 Low-pass filter, 40
... control logic circuit, 41 ... memory.

Claims (1)

(57) [Claims] 1. An A / D converter means for sampling an analog signal at a frequency fs of several tens times or more of the frequency of the analog signal to form a 1-bit digital signal; The series of 1-bit digital signals to be output are written to a memory at the same frequency as the frequency fs, temporarily stored,
A memory control unit for performing reading; a binarizing unit for performing binarization of the series of the read 1-bit digital signals; removing a high-frequency component of an output from the binarizing unit; An analog signal delay circuit, comprising: a filter means for extracting the analog signal delayed by a time difference between writing and reading of a digital signal of bits in the memory control means.