JP3336823B2 - Sound signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an audio signal processing apparatus, and more particularly to a method for sampling an analog audio signal using a sampling signal having a sampling frequency exceeding twice the upper limit frequency of an audible frequency band. The code information of an N-bit digital audio signal obtained by converting the obtained sequential sample values into a digital signal with a resolution of 1 / N is converted into M-bit code information having a relationship of M> N. The present invention relates to an audio signal processing device configured to include a bit number conversion unit that performs conversion.

[0002]

2. Description of the Related Art When digitizing an audio signal, a digital signal having a predetermined number of bits is generated in accordance with a standard determined in consideration of the fidelity of transmission, recording and reproduction, the price of the apparatus, and various other conditions. As is well known, for example, a 16-bit digital signal is recorded on a compact disc. As described above, if the digital signal having a predetermined number of bits according to a specific standard is, for example, an N-bit digital signal, the digital signal is obtained by converting an analog signal into a digital signal with a resolution of 1 / N. Is converted to Therefore, it is natural that an N-bit digital signal cannot recover a minute signal portion with a resolution higher than the resolution of 1 / N.

[0003] However, attempts have been made to restore even a minute signal portion with a resolution higher than the resolution determined by the number of bits of the digital signal. That is, as an example of the above-mentioned attempt, for example, as disclosed in Japanese Patent Application Laid-Open No. 5-304474, N-bit code information is converted into M-bit code information in a relationship of M> N. Suggestions for doing so. Then, the above-mentioned Japanese Patent Application Laid-Open No.
The bit enlarging method disclosed in Japanese Patent Publication No. 74-7474 applies a digital low-pass filter to smooth the waveform of digital data corresponding to a square wave so that a small-level signal is subjected to D / A conversion with little distortion. In this way, data up to 1 LSB or less determined in correspondence with the original number of bits is output and D / A conversion is performed.

Incidentally, as a result of a long-term research on human hearing, the frequency range (audible frequency band) of air vibration that humans perceive as sound has conventionally been 20 Hz to 2 Hz.
It is said to be 0 KHz. Therefore, even when aiming at high-fidelity reproduction (or transmission) of an audio signal, various conditions are conventionally determined so that recording and reproduction (or transmission) of the audio signal in the audible frequency band can be performed well. It was common to configure the system by using For example, when converting an audio signal in the entire audio frequency band into a digital signal, the sampling frequency is the lowest frequency (twice the upper limit frequency of the audio frequency band) that can satisfy the conditions required by the sampling theorem. The frequency value is slightly higher than the frequency value. That is, for example, the standard value is a sampling frequency of 44.1 KHz for a compact disc and 48 KHz for a digital audio tape recorder (DAT).

However, in recent years, the presence of a frequency component of 20 KHz or more, which is the upper limit frequency of the audible frequency band, contributes to the development of α waves in brain waves, and the presence of a frequency component of 20 KHz or more further increases the frequency. Research results that sound signals with naturalness can be reproduced will be announced, and sound signals in the entire audible frequency band, as a sampling frequency when converting to digital signals, sampling of the above-mentioned standard value A sampling frequency having a frequency value higher than the frequency (for example, 88.2 KHz, 96 KHz) is adopted as a sampling frequency when a sound signal is converted into a digital signal, and is sampled (hereinafter, referred to as high sampling means). ), The sound digital signal obtained by sampling and quantizing by applying the high sampling means described above, It has also been reported that significance was observed above (AES Tokyo Convention '95
Proceedings pp. 166-169 Mr. Osu and 6 others "96KH"
Sound quality evaluation of z-sampling digital audio ").

[0006] As described above, the present invention aims at recording and reproducing the frequency component of 20 kHz or more, which is the upper limit frequency of the audible frequency band, so that a more natural sound signal can be reproduced. Intentionally, as a sampling signal for converting an audio signal in the entire audible frequency band into a digital signal, a sampling frequency having a frequency value higher than the above-described standard value sampling frequency (for example, 88.2 KH) is used.
z, 96 KHz), using a sampled signal having a sampled signal having an analog signal form.
That is, the code information of the N-bit digital audio signal obtained by converting the sequential sample values obtained by the high sampling means into a digital signal with a resolution of 1 / N is also expressed by the number of bits of the digital signal. Bit number conversion for converting the above-mentioned N-bit code information into M-bit code information in a relationship of M> N so that a minute signal portion can be restored with a resolution higher than the determined resolution. It is also conceivable to apply technology.

Further, when converting an acoustic signal in the form of an analog signal into a digital signal, the aforementioned high sampling means and the noise shaping technique are applied to dither into a frequency band higher than the audible frequency band, and To reduce the noise in the low-mid frequency band where the hearing is sharp and to increase the noise in the frequency band that cannot be perceived by human hearing, the quantization noise spectrum is changed, and the dynamic range in perception is expanded. As a result, attempts have been made to reproduce an audio signal with a resolution higher than the resolution determined by the number of bits of an N-bit digital signal.

[0008]

In the prior art described above, even a signal of a very small level has a small distortion in the DA.
In the case of digital data corresponding to a square wave so that conversion is performed, the waveform is smoothed by a digital low-pass filter, and 1L determined according to the original number of bits.
In the one in which data up to SB or less is output and DA conversion is performed, an analog signal is converted into a digital signal at a resolution of 1 / Nth power, and is converted into 1-LSB in N-bit code information obtained. The data value is smoothed using the N-bit code information described above. Therefore, in the prior art as described above, even though the effect of improving the linearity of the waveform itself is recognized, as is well known, the code information of N bits necessarily includes 0.5LSS.
According to the above-mentioned prior art, when the original analog signal is estimated based on N-bit code information, M>
It was not possible to convert N-bit code information having a relationship of N into high-quality M-bit code information.

Therefore, when converting an analog audio signal into a digital signal, the N-bit digital signal obtained by applying the above-described high sampling means is converted into a signal having a resolution higher than the resolution determined by the number of bits of the digital signal. In order to recover even a minute signal portion, the above-mentioned N-bit code information has a relationship of M> N
Even if the above-described conventional bit number conversion technique of converting into bit code information is applied, a reproduced sound signal of good sound quality cannot be obtained. Also, when converting an analog audio signal into a digital signal, the N signal obtained by applying the above-mentioned high sampling means and the noise shaping technique is obtained.
The N-bit code information is set to have a relationship of M> N so that a bit digital signal can be restored even with a resolution higher than the resolution determined by the number of bits of the digital signal and a minute signal portion. In the case where conversion into certain M-bit code information is performed, dither placed in a frequency band higher than the audible frequency band is also converted into M-bit code information having a relationship of M> N. This is a problem.

[0010]

SUMMARY OF THE INVENTION The present invention provides a sequential audio signal obtained by sampling an analog signal in the form of an analog signal using a sampled signal having a sampling frequency exceeding twice the upper limit frequency of the audio frequency band. Means for obtaining N-bit code information belonging to an audio frequency band from code information of an N-bit digital audio signal obtained by converting a sample value into a digital signal with a resolution of 1 / Nth power; The number of bits is converted into M-bit code information belonging to an audible frequency band having a relation of M> N by continuously adding (MN) bits of additional code information to the least significant digit of the N-bit code information belonging to the frequency band. (MN) -bit additional code information generating means for generating (MN) -bit additional code information required when performing the above-mentioned operation, and the least significant digit in the code information of the N-bit digital audio signal. To An audio signal processing device comprising: means for adding the (MN) -bit additional code information output from the (MN) -bit additional code information generating means, and an audible frequency band. 2 of the upper limit frequency of
N is obtained by converting a sequential sample value obtained by sampling an analog sound signal in the form of an analog signal using a sampling signal having a sampling frequency more than twice to a digital signal at a resolution of 1 / N. Means for obtaining N-bit code information belonging to the audio frequency band from the code information of the digital audio signal of bits, and adding (MN) bits to the least significant digit of the N-bit code information belonging to the audio frequency band. By continuing the code information, M belonging to an audible frequency band having a relation of M> N
An audio signal in the form of an analog signal in which the (MN) -bit additional code information required when performing the bit number conversion on the bit code information is N-bit code information belonging to the audible frequency band. And a resolution 1 LSB of 1 / Nth power of 2 which exists between an audio signal in the form of an analog signal belonging to the audio frequency band obtained by restoring the N-bit code information belonging to the audio frequency band and ± 0. .5LS
Within the error range of B, the integrated value of the analog signal waveform represented by the N-bit code information belonging to the audible frequency band and the integrated value of the analog signal waveform represented by the M-bit code information can be made equivalent. (MN) bits of additional code information generating means, which is (MN) bits of additional code information, and the above-mentioned lowest digit in the code information of the N-bit digital audio signal. Means for adding (MN) -bit additional code information output from (MN) -bit additional code information generating means.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific contents of an audio signal processing apparatus according to the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a block diagram showing an example configuration of an audio signal processing device according to the present invention. In FIG. 1, reference numeral 1 denotes an input terminal of an audio signal processing apparatus. The input terminal 1 is an N-bit digital audio signal (hereinafter referred to as N-bit code information) which is an object of signal processing in the audio signal processing apparatus. May be provided). The N-bit code information supplied to the input terminal 1 is supplied to the delay circuit 3 and the band division filter 60.

The N-bit digital audio signal (N-bit code information) supplied from the input terminal 1 to the delay circuit 3 is delayed for a predetermined time in the delay circuit 3, that is, a band division described later. The signal processing operation in the filter 60 and the additional code information generation unit ACG gives a time delay for compensating the time delay generated in the additional code information, and then gives the time delay to the addition circuit 4 of the bit number conversion unit BNC. The N-bit code information supplied from the input terminal 1 to the band division filter 60 is the N-bit code information belonging to the audible frequency band among the N-bit code information targeted for signal processing in the acoustic signal processing device. The code information is passed and supplied to the detection unit 5 in the change detection mode of the signal waveform of the bit number conversion unit BNC.

FIG. 14 shows the above-described band division filter 60.
FIG. 4 is a diagram illustrating an example of frequency response characteristics for explaining the pass band characteristics of FIG. The frequency fs is the frequency (sampling frequency) of the sampled signal used when generating the N-bit code information supplied from the input terminal 1 to the band division filter 60, for example, 48 KHz or 88. It is a frequency such as 2 KHz. Therefore, N
If the frequency (sampling frequency) of the sampled signal used to generate the bit code information is, for example, 48 KHz or 88.2 KHz, the cutoff frequency of the low-pass filter used as the band division filter 60 described above. Is 48/4 = 12 (KHz) or 88.2 / 4
= 22.05 (KHz). Then, the low-pass filter used as the band division filter 60 is:
The FIR filter has a transfer function of H (z).

Now, as described above, the band division filter 60
The N-bit code information belonging to the audible frequency band supplied to the bit number conversion unit BNC from the low-pass filter used as the coded signal belongs to the audible frequency band in the additional code information generation unit ACG in the bit number conversion unit BNC. It is used to generate (MN) -bit additional code information belonging to an audible frequency band having a relationship of M> N with N-bit code information. The additional code information of the (MN) bits belonging to the audible frequency band generated by the additional code information generation unit ACG in the bit number conversion unit BNC is described above in the addition circuit 4 of the bit number conversion unit BNC. The N-bit code information supplied from the input terminal 1 to the addition circuit 4 via the delay circuit 3 is added so as to be continuous with the lowest digit. From the adder circuit 4, a digital signal that is M-bit code information in the audio frequency band and N-bit code information in a frequency band higher than the audio frequency band is output to the output terminal 2. Sent out.

Next, as described above, the band division filter 60
(M) in the additional code information generation unit ACG of the bit number conversion unit BNC to which N-bit code information belonging to the audible frequency band is supplied from the low-pass filter used as
-N) Generation of additional code information of bits and conversion of the number of bits in the bit number conversion unit BNC will be described. FIG.
The number-of-bits conversion unit BNC shown therein includes a detection unit 5 for detecting a change state of a signal waveform and a (MN) bit signal generation unit 6.
, An additional code information generation unit ACG constituted by respective components of a variable delay unit 7 and a delay control signal generation unit 8.
And an adder 4.

The bit number conversion unit BNC includes:
An analog signal used to obtain N-bit code information obtained by converting an analog signal into a digital signal with a resolution of 1 / Nth power of 2 and the N-bit code information are restored. An integral value of the analog signal waveform indicated by the N-bit code information and an M-bit value within an error range of ± 0.5 LSB for a resolution 1 LSB of 1 / Nth power of 2 existing between the analog signal and the analog signal In order to convert the number of bits so that the integrated value of the analog signal waveform indicated by the code information is equivalent to that of the analog signal waveform, one adjacent sample of N-bit code information to be converted is sequentially sampled. (MN) bits set so as to correspond to a predetermined analog signal waveform based on the result of detection of information on the manner of change in the difference between the N-bit code information that separates the conversion period. Additional code information by continuously to the least significant digit of the code information of N bits mentioned above, and is configured as to perform operations such as to generate a code information of M bits.

First, the configuration principle and operation principle of the bit number conversion unit BNC will be described with reference to FIGS. 6 to 10. In FIG. 6, points indicated by a to n are represented by a → b → c → d → e → f → g → h → i → j → k → l.
A curve S connected by a thick solid line like → m → n
Is a digital value of a digital value obtained by sampling and quantizing an analog signal at a resolution of 1 / Nth power, that is, a resolution of 1 LSB of N bits at every specific sampling period Ts (reciprocal of the sampling frequency fs). This is an example of the state of change, and the analog signal of the original signal that generates the digital value as shown by the curve S exists in the area surrounded by the broken line in FIG. It is a thing.

Thus, an analog signal used to obtain N-bit code information obtained by converting the digital signal into a digital signal;
An analog signal obtained by restoring the N-bit code information contains an error within ± 0.5 LSB for a resolution 1 LSB of 1 / N. In FIG. 6, t1, t2, t3... Are the points at which the sequential sampling is performed, and the time between the adjacent sampling points at the above-mentioned sequential sampling points t1, t2, t3. Ts indicates a sampling period. In the additional code information generation unit ACG in the bit number conversion unit BNC, the bit number conversion is performed on the N-bit code information obtained by converting the analog signal into a digital signal with a resolution of 1 / N. Therefore, when obtaining M-bit code information in a relationship of M> N, the value of the N-bit code information changes in a manner of sequentially increasing or decreasing on the time axis. In this case, the length (indicated by the number of sampling periods) of a period (section) in which the value of N-bit code information for each successive sampling period continues in the same state is adjacent to the period. And N-bit code information that differs from the value of the N-bit code information in the above-described period by a resolution 1 LSB of 1 / Nth power is:
The length of a subsequent period (section) as N-bit code information for each successive sampling cycle is compared.

If the two adjacent sections have different period lengths, the two adjacent sections have a middle point having a shorter period length and a middle point having a longer period length. (MN) bits of additional code information that can represent a straight line connecting a half of the short period length and a point at a corresponding position from the boundary between the two sections are generated. When the two sections have the same period length, (MN) bits of additional code information that can represent a straight line connecting the midpoints of the two sections in the two sections are generated. As described above, the additional code information generated by the additional code information generation unit ACG in the bit number conversion unit BNC is added by the addition circuit 4 so as to be continuous with the least significant digit of the N-bit code information, and the M-bit code information is added. Generated.

If the value of the N-bit code information is N-bit code information in a section corresponding to the extreme value, the additional code information generation unit ACG in the bit number conversion unit BNC performs , And generates predetermined (MN) bits of additional code information corresponding to the period length of the section. Then, the predetermined (MN) -bit additional code information is added by the adding circuit 4 so as to be continuous with the least significant digit of the N-bit code information, and M-bit code information is generated.

FIG. 7A shows a case where M-bit code information is generated by connecting (MN) -bit additional code information to the least significant digit of N-bit code information as described above. FIG. In FIG. 7A, a curve Sn of a staircase waveform represented by a thick solid line indicates a change on the time axis of N-bit code information obtained by converting an analog signal into a digital signal with a resolution of 1 / N. Further, a thin solid line staircase waveform curve Sm illustrates a change on the time axis of the (MN) -bit additional code information obtained as described above.

In FIG. 7A, points a → b → c → d →
A curve Sn indicated by e → f indicates a manner of change on the time axis regarding N-bit code information. As described above, in the additional code information generation unit ACG in the bit number conversion unit BNC in FIG. 1, the value of the N-bit code information shows a tendency to increase or decrease sequentially on the time axis. , Then N for each successive sampling period
The length of the period (section) in which the value of the bit code information continues in the same state (for example, the period length of the section shown between points a → b, the period of the section shown between points c → d) Long, point e →
f) is compared for each of two adjacent sections, and when the two adjacent sections have the same period length, each of the two sections in the two sections is the same. (M−N) bits of additional code information indicated as a straight line connecting the midpoints of the sections a to b and c to d in FIG. Are shown in the two sections. That is, in the two sections of the section a → b and the section c → d, which exemplify a case where two sections having the same period length are continuous, the middle point of the section a → b Position h and section c
→ (MN) -bit additional code information indicated as a straight line connecting the midpoint position i of the section in d is generated.

Next, when the value of the N-bit code information changes and shows a tendency to sequentially increase or decrease on the time axis, the N-bit code information for each successive sampling period is changed. The length of a period (section) in which the value of continues in the same state is compared for each two adjacent sections, and when the two adjacent sections have different lengths from each other, The midpoint of the shorter section,
(MN) -bit additional code information that can represent a straight line connecting a half of the short period length and a point at a position corresponding to 1/2 of the short period length from the boundary between the two periods in the longer period period This state is shown in two sections of section c → d and section e → f in FIG. 7A. That is, the section c →
Since the period lengths of the two sections d and e → f are longer in the section e → f, the above two sections c
→ c, the shorter of the section period length in d, e → f
d at the middle point and the section e with the longer period length →
In (f), the addition of (MN) bits indicated as a straight line connecting the half of the short period length and the point 1 at the corresponding position from the boundary d between the two sections c → d and e → f. Code information is generated. FIG. 7B shows Sm
−Sn is indicated by S (mn).

Next, when a period (section) in which the value of the N-bit code information in each successive sampling cycle continues in the same state is an extreme value section, it corresponds to the period length of the section. The M-bit code information is generated by making the preset (M-N) -bit additional code information continuous with the least significant digit of the N-bit code information.
In each of the figures, corresponding to the period length of the section of the extreme value described above,
An example of (MN) -bit additional code information to be set in advance is shown. For the section of the extremum based on the value of the N-bit code information, the (MN) -bit additional code information to be set in advance includes one sampling period Ts based on the N-bit code information corresponding to the extremum. Is set as a region having substantially the same area as a rectangular area indicating a section of the period length, that is, a region surrounded by a staircase waveform in each drawing.

FIG. 8 shows the (MN) -bit additional code information set corresponding to the case where the period length of the section based on the N-bit code information corresponding to the extremum is one sampling period Ts. FIG. 9 is a diagram exemplifying up to (MN) -bit additional code information set corresponding to a case where the period length of an N-bit code information corresponding to an extreme value is 6 sampling periods 6Ts. FIG. 9 shows the case where the period length of the section based on the N-bit code information corresponding to the extremum is 7 (M−N) bits of additional code information set in correspondence with the case where the sampling period is 7Ts. FIG. 13 is a diagram exemplifying up to (MN) -bit additional code information set corresponding to a case where a period length of a section based on N-bit code information corresponding to a value is 13 sampling periods 13Ts. Further, FIG. 10 shows that the period length of the section based on the N-bit code information corresponding to the extreme value is 14 sampling periods 1
From the (MN) -bit additional code information set corresponding to the case of 4Ts, it corresponds to the case where the period length of the section by the N-bit code information corresponding to the extremum is 16 sampling periods 16Ts. FIG. 9 is a diagram exemplifying up to (MN) bits of additional code information set in advance.

The additional code information of (MN) bits shown in FIG. 8 to FIG. 10 is referred to as a (MN) bit signal generator described later with reference to FIG. 1 and FIG. 6 is stored in the waveform data generating ROM provided in the waveform data generating section 48 in the extreme value section, and the N-bit code information corresponding to the extreme value is stored in the waveform data generating ROM. When the period length of a section is supplied as address information, predetermined (MN) bits of additional code information corresponding to the period length are read out and used as described later.

The bit number conversion unit BNC shown in FIG.
, The N-bit code information belonging to the audible frequency band is supplied from the low-pass filter used as the band division filter 60 to the detection unit 5 of the change state of the signal waveform in the additional code information generation unit ACG. However, as described later with reference to FIG. 2, the signal waveform change mode detection unit 5 includes a signal waveform change information generation unit 51, a signal waveform change mode information generation unit 52, A signal waveform change interval information generating unit 53 is provided. The signal waveform change mode detection unit 5 detects signal waveform change mode information and signal waveform change interval information for an N-bit digital signal belonging to the audible frequency band supplied thereto, The detected information is supplied to the (MN) bit signal generator 6 and the variable delay unit 7.

In the (MN) -bit signal generating section 6, when the value of the N-bit code information changes and shows a tendency to increase or decrease sequentially on the time axis, The length (indicated by the number of sampling periods) of a period (section) in which the value of the N-bit code information in each successive sampling cycle continues in the same state is compared for adjacent sections, and If the period lengths of the two sections are different from each other, the midpoint of the shorter section length of the two adjacent sections and the boundary between the two sections in the section having the longer period length From 1 / of the short period length
2 can be represented by a line connecting the point at the corresponding position (M−
N) bits of additional code information are generated and supplied to the variable delay unit 7, and when the two adjacent sections have the same period length, the midpoint between the two sections in the two sections It generates (M-N) -bit additional code information that can represent a straight line connecting them and supplies it to the variable delay unit 7. Further, the value of the N-bit code information corresponds to the extreme value. If the information is N-bit code information in a section, the predetermined (M-
The N-bit additional code information is read from the waveform data generating ROM provided in the waveform data generating section 48 in the extremum section, and is supplied to the variable delay section 7.

In the variable delay unit 7 to which the (MN) -bit additional code information generated by the (MN) -bit signal generation unit 6 is supplied, the (MN) -bit additional code information is transmitted. In the adder circuit 4, a time delay necessary for generating M-bit code information continuously from the least significant digit of the predetermined N-bit code information is represented by (MN) -bit additional code information. Give to. The above-described time delay amount in the variable delay unit 7 is obtained by controlling the variable delay unit 7 by the delay control signal generated by the delay control signal generation unit 8. That is, the delay control signal generation unit 8 performs the delay control signal generation based on the signal waveform change information, the signal waveform change mode information, and the signal waveform change interval information supplied from the signal waveform change mode detection unit 5. And supplies it to the variable delay unit 7. So,
From the adder circuit 4 described above, (M-
An M-bit digital signal in which the (MN) -bit additional code information generated by the (N) -bit signal generator 6 is continuous is transmitted.

Next, with reference to FIG. 2, a specific configuration and operation of the detection section 5 for detecting a change in signal waveform will be described. In FIG. 2, the detection unit 5 of the change mode of the signal waveform
Signal waveform change information generating section 51, signal waveform change mode information generating section 52, and signal waveform change interval information generating section 5
3. Then, an N-bit digital signal which is an object of information signal processing is supplied to an input terminal 25 of the detection unit 5 of the change mode of the signal waveform, and a clock signal pulse Pfs is supplied to an input terminal 26. As the above-mentioned clock signal pulse Pfs, a pulse having the same repetition frequency as the sampling frequency fs used when generating the digital signal targeted for the information signal processing is used. If the target digital signal is an acoustic signal,
As the clock signal pulse Pfs, for example, 88.2
A pulse with a repetition frequency fs of KHz is used.

The N-bit digital signal supplied to the signal waveform change information generator 51 via the input terminal 25 of the signal waveform change detector 5 and subjected to the information signal processing is processed by the magnitude comparator 10. , And the data terminal of the D-type flip-flop 9, and the clock terminal of the D-type flip-flop 9 has a clock signal Pf via an input terminal 26.
s is given. The B input terminal of the magnitude comparator 10 is supplied with the Q terminal output of the D flip-flop 9 described above. Therefore, the D-type flip-flop 9 described above is
Each time a clock signal Pfs is sequentially supplied to the clock terminal of the D-type flip-flop 9 via the input terminal 26 for each sampling period, the D-type flip-flop 9 is switched from the Q terminal of the D-type flip-flop 9 one sampling period before. The digital data of N bits provided to the data terminal of the amplifier 9 is output and input to the B input terminal of the magnitude comparator 10.

The magnitude comparator 10 compares the magnitude of the N-bit digital data A supplied to its A input terminal with the magnitude of the N-bit digital data B supplied to its B input terminal. When the digital data A is larger than the digital data B, only the output terminal A> B is set to the output H at a high level, and both the other output terminals A <B and the output terminal A = B are output. Is a low level output L, and when the digital data A and the digital data B in the N-bit digital data supplied to the input terminals A and B are equal, only the output terminal A = B The output H is at a high level, the output terminal A> B and the output terminal A <B are both at a low level L, and further supplied to the input terminals A and B. When the digital data B of the N-bit digital data is larger than the digital data A, only the output terminal A <B is set to the high-level output H, and the other output terminals A> B and the output terminal A = B
Can be used as the magnitude comparator 74HC85 in an operation mode in which both are set to the output L in the low level state.

The output terminal A> B of the magnitude comparator 10 in the signal waveform change information generating section 51
And the output from the output terminal A <B are supplied to an exclusive OR circuit 11. The output from the output terminal A> B of the magnitude comparator 10 is also supplied to the data terminal of the D-type flip-flop 13 of the signal waveform change mode information generation unit 52. The output of the exclusive OR circuit 11 is
Output terminal A of the magnitude comparator 10
When one of the output from> B and the output from the output terminal A <B becomes the high level state H, the state becomes the high level state H. In FIG. 2, the output from the output terminal A> B of the magnitude comparator 10 and the output from the output terminal A <B are supplied to the exclusive OR circuit 11, but the exclusive OR circuit 11 is used. Even if an OR circuit is used in place of the circuit 11, the same operation is performed as when the exclusive OR circuit 11 is used (from the magnitude comparator 10 in FIG. 2 to the exclusive OR circuit 11).
This is because a state in which a high-level signal is simultaneously applied to the two input terminals does not occur).

The output signal from the exclusive OR circuit 11 is supplied to an AND circuit 12, and a Pfs bar is supplied to the AND circuit 12 as a gate pulse. The gate pulse Pfs is a pulse having the same repetition frequency as the above-described clock signal pulse Pfs and a phase difference of 180 degrees from the clock signal pulse Pfs. Therefore, from the AND circuit 12 described above,
When the values of digital data adjacent to each other on the time axis which are separated by one sampling period in the N-bit digital signal are different, the clock signal CLK is output at the timing of the gate pulse Pfs bar. Become.

In response to the change on the time axis of the N-bit digital signal supplied to the input terminal 25 of the detection section 5 of the change form of the signal waveform, the signal change state of the signal waveform in the detection section 5 is detected. The state of generation of the clock signal CLK output from the AND circuit 12 of the waveform change information generator 51 will be described below with reference to FIG. In FIG. 4, A, B, H,... Described above the figure are N bits of the information signal supplied to the input terminal 25 of the detection unit 5 of the change mode of the signal waveform, which are to be processed. Is a code indicating the signal level of the digital signal of
Pfs1, Pfs2, Pfs described at the bottom of FIG.
3 ... Pfs19 is a clock signal pulse Pfs supplied to the input terminal 26, and furthermore, Pfs1 bar, Pf
s2 bar, Pfs3 bar ... Pfs19 bar is AND circuit 1
2 is a gate pulse being supplied to the second gate.

The above-mentioned signal waveform change information generating section 51
The N-bit digital signal supplied via the input terminal 25 and subjected to the information signal processing is supplied to the A input terminal of the magnitude comparator 10 and the data terminal of the D-type flip-flop 9. The clock terminals of the D-type flip-flop 9 are supplied with the clock signals Pfs1, Pfs2, Pfs3,... From the Q terminal of
The N-bit code information (digital data) provided to the data terminal of the D-type flip-flop 9 one sampling cycle Ts before is output, and is input to the B input terminal of the magnitude comparator 10.

The signal level of the N-bit digital signal supplied via the input terminal 25 and subjected to the information signal processing is represented on the time axis as shown in FIG.
When the clock signal Pfs1 changes, digital data of the signal level "A" is input to the A input terminal of the magnitude comparator 10 and the data terminal of the D-type flip-flop 9 at the time of the clock signal Pfs1. And in this case the magnitude comparator 10
The digital data given from the Q input terminal of the D-type flip-flop 9 to the B input terminal in is undefined "?".
Therefore, at the time of the clock signal Pfs1, the output from the magnitude comparator 10 is undefined “?”.

Next, at a time one sampling period Ts after the clock signal Pfs1 described above, that is, at a clock signal Pfs2 time, the magnitude comparator 1
The digital data of the signal level “b” is given to the A input terminal at 0 and the data terminal of the D-type flip-flop 9, and the B input terminal of the magnitude comparator 10 receives the signal from the Q terminal of the D-type flip-flop 9. Digital data of level "A" is provided. So,
At the time of the clock signal Pfs2, only the output terminal A> B of the output from the magnitude comparator 10 is at a high level. Then, only the output terminal A> B of the magnitude comparator 10 is in the high level state because the digital signal tends to increase on the time axis (FIG. 5).
In the figure, the signs of ">" and "U" indicate that the digital signal tends to increase on the time axis. Also,
In FIG. 4, a display method such as “A> B (>, U)” is adopted).

As described above, at the time of the clock signal Pfs2, the output terminal A> B of the magnitude comparator 10
Is at a high level, the output of the exclusive OR circuit 11 is at a high level at the time of the clock signal Pfs2. The AND circuit 12 to which the output of the magnitude comparator 10 is given
Outputs a high-level clock signal CLK2 at the time when the gate pulse Pfs2 bar is given (see FIG. 4).

Next, the clock signal Pf after one sampling period Ts from the time of the clock signal Pfs2 described above.
At time s3, digital data of the signal level “b” is supplied to the A input terminal of the magnitude comparator 10 and the data terminal of the D-type flip-flop 9, and at this time, the B input terminal of the magnitude comparator 10 Since the digital data supplied from the Q terminal of the D-type flip-flop 9 is also at the signal level "low", only the output terminal A = B of the output from the magnitude comparator 10 at the time of the clock signal Pfs3 is at the high level. Therefore, the output of the exclusive OR circuit 11 becomes a low level at the time of the clock signal Pfs3, so that the AND circuit 12 to which the output of the low level from the magnitude comparator 10 is given, High level even when gate pulse Pfs bar is applied The clock signal CLK of the state is not outputted.

Next, the clock signal Pfs after one sampling period Ts from the time of the clock signal Pfs3
At time 4, digital data of signal level “C” is given to the A input terminal of the magnitude comparator 10 and the data terminal of the D-type flip-flop 9, and the D-type flip-flop is supplied to the B input terminal of the magnitude comparator 10. Digital data of a signal level "b" is supplied from the Q terminal of the loop 9. Therefore, at the time of the clock signal Pfs4, the magnitude comparator 1
As for the output from 0, only the output terminal A> B is at a high level. As described above, at the time of the clock signal Pfs4,
Since only the output terminal A> B of the magnitude comparator 10 is at a high level, the output of the exclusive OR circuit 11 is at a high level at the time of the clock signal Pfs4, and the output of the magnitude comparator 10 The AND circuit 12 to which the output is applied outputs the clock signal CLK3 at the high level at the time when the gate pulse Pfs4 is applied (see FIG. 4).

At the time of the clock signal Pfs5 after one sampling period Ts from the time of the clock signal Pfs4, the signal level "C" is applied to the A input terminal of the magnitude comparator 10 and the data terminal of the D-type flip-flop 9. At this time, the digital data supplied from the Q input terminal of the D-type flip-flop 9 to the B input terminal of the magnitude comparator 10 is also at the signal level “C”, so the magnitude at the clock signal Pfs5 As for the output from the comparator 10, only the output terminal A = B is at the high level, and the output of the exclusive OR circuit 11 is at the low level at the time of the clock signal Pfs5. , Even if the gate pulse Pfs bar is given, The clock signal CLK of the state is not output.

Next, the clock signal Pfs after one sampling period Ts from the time of the clock signal Pfs5 described above.
At time 6, digital data of signal level “d” is given to the A input terminal of the magnitude comparator 10 and the data terminal of the D-type flip-flop 9, and the D-type flip-flop is supplied to the B input terminal of the magnitude comparator 10. Digital data of the signal level “C” is supplied from the Q terminal of the loop 9. Therefore, at the time of the clock signal Pfs6, the magnitude comparator 1
In the output from 0, only the output terminal A> B is at a high level, so that the output of the exclusive OR circuit 11 is at a high level at the time of the clock signal Pfs6, and the output of the magnitude comparator 10 The AND circuit 12 to which the output is applied receives the high-level clock signal CLK4 at the time when the gate pulse Pfs6 is applied.
Is output (see FIG. 4).

Next, the clock signal Pf after one sampling period Ts from the time of the clock signal Pfs6 described above.
At time s7, digital data of the signal level “e” is given to the A input terminal of the magnitude comparator 10 and the data terminal of the D-type flip-flop 9,
To the B input terminal of the magnitude comparator 10, digital data of the signal level “d” is given from the Q terminal of the D-type flip-flop 9. Therefore, at the time of the clock signal Pfs7, only the output terminal A <B of the output from the magnitude comparator 10 is at a high level. And the magnitude comparator 10
Only the output terminal A <B of the
Digital signals tend to decrease on the time axis (in FIG. 5, the digital signals tend to decrease on the time axis are indicated by symbols “<” and “D.” A <B (<, D) ”is adopted). Then, the output of the exclusive OR circuit 11 goes to a high level at the time of the clock signal Pfs7, and the AND circuit 12 to which the output of the magnitude comparator 10 is applied receives the gate pulse Pfs7 at the time. Then, the clock signal CLK5 at a high level is output (see FIG. 4).

The clock signal Pfs8 shown in FIG.
The operation of each unit of the signal waveform change information generation unit 51 performed at each time from Pfs19 to Pfs19 is based on clock signals Pfs1 to Pfs7.
Since the operation of each unit of the signal waveform change information generation unit 51 performed at each time can be easily understood, detailed description thereof will be omitted. As can be understood from the above description, the sequential clock signal Pfsi (where i is 1, 2, 3,...) Given for each sampling period
Magnitude comparator 10 performed every time
The reason why only one of the output terminal A> B or the output terminal A <B of the comparison output from is in a high level state is to be processed by the information signal supplied via the input terminal 25. This is only when the signal level of the N-bit digital signal is increasing or decreasing on the time axis.

The clock signal CLKi (where i is
Are output when only one of the output terminal A> B or the output terminal A <B of the magnitude comparator 10 is at a high level, that is, via the input terminal 25. This is when the signal level of the supplied N-bit digital signal subjected to the information signal processing is increasing or decreasing on the time axis.

As described above, the clock signal CLKi (where i is 1, 2, 3, 4...) Transmitted from the AND circuit 12 of the signal waveform change information generating section 51 is the signal waveform change mode information. D-type flip-flop 1 of generator 52
The clock terminals 3 to 15 and the clock terminals of the D-type flip-flops 19 to 21 of the generation unit 53 of the interval information of the signal waveform change are supplied. The D-type flip-flops 13 to 15 of the signal waveform change mode information generating unit 52 convert the digital data supplied to the data terminals of the flip-flops 13 to 15 at the time when the clock signal CLK is applied. The D-type flip-flops 19 to
Reference numeral 21 reads the digital data supplied to the data terminals of the D-type flip-flops 19 to 21 when the clock signal CLK is applied.

The signal appearing at the output terminal A> B of the magnitude comparator 10 of the signal waveform change information generator 51 is provided to the data terminal of the D-type flip-flop 13 in the signal waveform change mode information generator 52. Since the D-type flip-flop 13 is supplied, the D-type flip-flop 13 supplies the sequential clock signal CLKi (where i is 1, 2, 3, 4...) Each time the sequential clock signal CLKi is supplied. CLKi (where i is 1,
When the occurrence of (2, 3, 4...) Occurs, the state (high-level state or low-level state) of the signal appearing at the output terminal A> B in the magnitude comparator 10 of the signal waveform change information generation unit 51 is changed. Will read.

At the time of generation of the above-mentioned sequential clock signal CLKi (where i is 1, 2, 3, 4...), It appears at the output terminal A> B of the magnitude comparator 10 of the signal waveform change information generating section 51. It is determined whether the state of the output signal becomes a high-level state or a low-level state in the sequential clock signal CLKi (where i
Are determined based on whether the digital signal at the time of occurrence of 1, 2, 3, 4... Has an increasing tendency on the time axis or a decreasing tendency on the time axis. The sequential clock signal CLKi
(Where i is 1, 2, 3, 4...), When the digital signal tends to increase on the time axis, the signal appearing at the output terminal A> B of the magnitude comparator 10 The state is a high level state, and conversely, the sequential clock signal C
If the digital signal at the time of occurrence of LKi (where i is 1, 2, 3, 4...) Is decreasing on the time axis, it appears at the output terminal A> B of the magnitude comparator 10. The state of the signal is low.

The above point will be described with reference to FIGS. 4 and 5. That is, the digital signal at the time of generation of the sequential clock signal CLKi (where i is 1, 2, 3, 4...) Tends to increase on the time axis, and the clock signal CLK (gate pulse Pfs bar) At the point of time, the signal in the high level state is the D-type flip-flop 1 in the signal waveform change mode information generation unit 52.
3, the numbers of the clock signals CLK shown in FIGS. 4 and 5 are 2-4,12-14,17,18,2.
1 to 27 (time of the clock signal CLK indicated by the upward arrow in FIG. 4), and the generation of the successive clock signals CLKi (where i is 1, 2, 3, 4...) The digital signal at the time point tends to decrease on the time axis, and at the time point of the clock signal CLK (gate pulse Pfs bar), the signal in the low level state is a D-type signal in the signal waveform change mode information generation unit 52. The number of the clock signal CLK shown in FIGS. 4 and 5 is 5 to 11, 15, 16, 1
9 and 20 (time of the clock signal CLK indicated by a downward arrow in FIG. 4).

As described above, the sequential clock signals CLKi
(Where i is 1, 2, 3, 4...)
A signal sequentially supplied to the data terminal of the D-type flip-flop 13 in the signal waveform change information generation unit 52, that is, appears at the output terminal A> B of the magnitude comparator 10 of the signal waveform change information generation unit 51. Are sequentially transferred to the data terminals of the D-type flip-flops 14 and 15 each time a sequential clock signal CLKi (where i is 1, 2, 3, 4...) Is supplied. The state is "input of DFF13" in FIG.
“Output of DFF13” “Output of DFF14” “DFF1
5 ". Note that “U” described in the above-described column indicates a high-level state, and “D” described in the column indicates a low-level state.

The output of the D-type flip-flop 13 and the output of the D-type flip-flop 14 of the signal waveform change mode information generating section 52 are supplied to an exclusive OR circuit 16. The output and the output of the D-type flip-flop 15 are supplied to an exclusive OR circuit 17, and the output of each of the exclusive OR circuits 16 and 17 is referred to as an “exclusive OR circuit” in FIG. 16 output ”and“ output of exclusive OR circuit 17 ”. Note that "1" in this column indicates a high level state, and "0" indicates a low level state. FIG.
In the column of “extremum position of signal waveform”, “d,” “le,” “ka,” “ta,” “so,” “ne,” etc. are indicated by the signals shown in the upper part of FIG. In the code indicating the signal level of the N-bit digital signal, which is supplied to the input terminal 25 of the detection unit 5 of the change mode of the waveform and is subjected to the information signal processing, the extreme value of the signal waveform is The position of the corresponding signal level is shown.

The digital data of the extreme position of the signal waveform in the N-bit digital signal supplied to the input terminal 25 of the detection unit 5 of the signal waveform change mode and subject to the information signal processing is: The output of the exclusive OR circuit 16 of the generator 52 in the signal waveform change mode information is
The clock signal C when the state becomes the high-level state “1”
It can be seen that the data has been read into the D-type flip-flop 13 by the clock signal CLK having the clock signal number smaller by 2 than the LK number. The digital data of the extreme position of the signal waveform in the N-bit digital signal supplied to the input terminal 25 of the detection unit 5 in the signal waveform change mode and targeted for the information signal processing is as described above. Generator 52 in signal waveform change mode information
Is output to the D-type flip-flop 13 by the clock signal CLK having the number of the clock signal CLK which is smaller by 3 than the number of the clock signal CLK when the output of the exclusive OR circuit 17 of the X Assuming that the value has been read, the position of the extreme value may be detected. Thus, the generator 52 in the signal waveform change mode information described above.
The output signals from the exclusive OR circuits 16 and 17 in the middle are used as extreme value position information of a signal waveform required for signal processing in a (MN) bit signal generator 6 described later. It can also be used as position information of an extremum of a signal waveform required for signal processing in the delay control signal generator 8 described later.

Next, the clock signal CLKi (where i is 1, 2, 3, 4...) Sent from the AND circuit 12 of the signal waveform change information generating section 51 is applied to the signal waveform supplied to the clock terminal. A data terminal of the D-type flip-flop 19 in the D-type flip-flops 19 to 21 of the change interval information generation unit 53 has an address counter performing a counting operation using a clock signal pulse Pfs having a sampling period as a counted pulse. The address value output from 18 is supplied. Therefore, the D-type flip-flop 19 of the generation unit 53 of the interval information of the signal waveform change,
The aforementioned clock signal CLKi (where i is 1, 2, 2,
3, 4...) Are read from the address counter 18 each time the clock value is supplied to the clock terminal.

The address value read into the D-type flip-flop 19 is based on the sequential clock signal CL transmitted from the AND circuit 12 of the signal waveform change information generating section 51.
Each time Ki (where i is 1, 2, 3, 4...) Is supplied to the clock terminals of the D-type flip-flops 19 to 21, they are transferred to the D-type flip-flops 20 and 21. . Each of the D-type flip-flops 19 described above
21 are sent to the respective output terminals 27, 30, and 31, and the address value output from the D-type flip-flop 19 and the address value output from the D-type flip-flop 20. The address value is supplied to a subtractor 22, and the address value output from the D-type flip-flop 20 and the address value output from the D-type flip-flop 21 are supplied to a subtractor 23.

The output value N from the subtracters 22 and 23
1, N2 is a difference between address values between clock signals CLK adjacent on the time axis. As described above, the address counter 18 uses the clock signal pulse Pfs having the sampling period as a pulse to be counted. Since the counting operation is being performed, the numerical values of the output values N1 and N2 from the subtracters 22 and 23 described above correspond to the clock signals C and C that are adjacent on the time axis.
This is a numerical value indicating how many times the interval between LKs is longer than the sampling period Ts. The output values N1 and N2 from the subtracters 22 and 23 are sent to output terminals 28 and 36, respectively, and are also supplied to a comparator 24. The comparator 24 compares the output values N1 and N2 from the two subtracters 22 and 23 to obtain the two numerical values N1 and N2.
The smaller value Ns of N2 (when N1 and N2 are the same, N1 is set to Ns) is sent to the output terminal 29. The address value output from each of the D-type flip-flops 19 to 21 of the signal waveform change interval information generation unit 53, the output value Ns from the comparator 24, and each subtractor 2
Output values from 2, 23 are described later (M-N).
It can be used as interval information of a signal waveform change required for signal processing in the bit signal generator 6 and can also be used as interval information of a signal waveform change in a delay control signal generator 8 described later. .

Next, the (MN) bit signal generator 6 shown in FIG. 3 will be described. (MN) bit signal generator 6
If the value of the N-bit code information to be subjected to the signal processing changes in a time-series manner with a sequentially increasing tendency or a successively decreasing tendency, the value of each of the successive sampling periods When the length (indicated by the number of sampling periods Ts) of the periods (sections) in which the values of the N-bit code information continue in the same state are different from each other in two adjacent sections, the adjacent two A middle point of the shorter section of the two sections is connected to a point at a position corresponding to 短 い of the shorter period from the boundary between the two sections in the section of the longer period. (M−N) bits of additional code information that can represent a straight line are generated. When the two adjacent sections have the same period length, the intermediate section between the two sections in the two sections is generated. (MN) -bit additional code information that can represent a connecting straight line Occurs, and if the value of the N-bit code information is N-bit code information in a section corresponding to the extreme value, the value is predetermined in correspondence with the period length of the section. An operation of reading (MN) bits of additional code information from the waveform data generating ROM and supplying the (MN) bits of additional code information generated as described above to the variable delay unit 7 can be performed. It is configured as follows.

In FIG. 3, reference numeral 48 denotes an extreme value section waveform data generator.
As described above with reference to FIG. 7B and FIGS. 8 to 10, the period length of the section corresponding to the extreme value based on the N-bit code information targeted for signal processing (M
-N) A ROM for generating waveform data in which bit code information is stored is provided. The reference numeral 49 designates a signal waveform change interval information generating unit 5 with the value of 1 LSB in N-bit code information to be processed as a dividend.
3, the value Ns transmitted from the comparator 24 via the output terminal 29, that is, the shorter period length of the lengths of two adjacent sections (when the period lengths of the two adjacent sections are the same) Is an "operation unit for generating a value for performing an operation of 1 LSB / Ns of N bits", which performs an operation of dividing a numerical value Ns representing the period length of one section in units of a sampling period Ts as a divisor.

Numeral 54 indicates that the value of N-bit code information to be subjected to signal processing tends to increase sequentially on the time axis.
Alternatively, in the case where the value of N-bit code information for each successive sampling period continues in the same state and the length of the period (section) is two adjacent sections, Are different or the same, and when the two adjacent sections do not include an extreme value section, the two sections described above are described with reference to FIG. A “waveform data generation unit other than the extremum section” that generates (M−N) bits of additional code information by applying such a method, and 55 is, for example, a random access memory (RAM) or a read only memory ( ROM),
This is a control circuit including a microprocessor and the like. 56 is an inverter, 57 and 58 are selectors, and 59 is an OR circuit.

The signals output from the output terminals 27 to 36 of the detecting section 5 having the above-mentioned change form of the signal waveform are supplied to the input terminals 37 to 46 of the (MN) bit signal generating section 6. However, the connection relationship between each of the input terminals 37 to 46 in the (MN) bit signal generation unit 6 and the output terminals 27 to 36 of the detection unit 5 for the change mode of the signal waveform is as follows. → input terminal 43, output terminal 28 → input terminal 37, output terminal 29 → input terminal 39, output terminal 30 → input terminal 44, output terminal 31 → input terminal 4.
5, output terminal 32 → input terminal 46, output terminal 33 → input terminal 38, output terminal 34 → input terminal 41, output terminal 35
→ input terminal 40, output terminal 36 → input terminal 42.

The waveform data generator 48 for the extreme value section operating under the control of the control circuit 55 has N bits of 1 LSB /
In the arithmetic unit 49 for generating the value for performing the operation of Ns and the waveform data generating unit 54 other than the extremum section, the above-described extremum section waveform data generating unit 48 is configured to change the signal waveform change mode with respect to the input terminal 37. Numerical value N1 (the output value N1 of the subtractor 22) supplied from the output terminal 28 of the detection unit 5 and an extreme value section supplied from the output terminal 33 of the detection unit 5 of the change form of the signal waveform to the input terminal 38 Is read out from the waveform data generating ROM by using the above-mentioned numerical value N1 as address information and predetermined (M-N) bits of additional code information corresponding to the period length of the extremum section. From the extreme value section waveform data generator 48 to the selector 57.

That is, when the signal indicating the extreme value section supplied from the output terminal 33 of the detection section 5 of the change state of the signal waveform to the input terminal 38 is "1", the input terminal 37 Is the period length of the extremum section (how many times the sampling period Ts) {see FIG. 11 (a)}.
Is used as the address information, the waveform of the extreme value section in which the waveform data of the predetermined extreme value section (a part of which is illustrated in FIGS. 8 to 10) is stored in advance for each period length of the extreme value section From the ROM for data generation, a predetermined (MN) -bit additional code information corresponding to the period length of the extremum section ｛the extremum section is shown in FIG.
(M) corresponding to the input data exemplified in FIG.
The −N) -bit additional code information can output｝ which is output data having a waveform as illustrated in FIG. 11C. Then, in the extremum section, since the signal “1” indicating the extremum section is supplied to the selector 57 via the input terminal 38, the selector 57 outputs the signal from the waveform data generator 48 in the extremum section. The (MN) -bit additional code information is transmitted to the output terminal 47 via the selector 57 and the OR circuit 59.

Next, a calculating unit 49 for generating a value for performing an operation of 1-LSB / Ns of N bits is supplied to an input terminal 39 by a numerical value Ns supplied from an output terminal 29 of the detecting unit 5 of the change mode of the signal waveform. Using the (output value Ns of the comparator 24), an operation of 1-bit LSB / Ns of N bits is performed, and the operation result is supplied to the waveform data generating unit 54 other than the extremum section. The above-mentioned numerical value Ns is also supplied to the waveform data generating unit 54 outside the extreme value section from the calculating unit 49 for generating a value for performing the calculation. The input terminal 4 is connected to the waveform data generator 54 other than the extreme value section.
0 output terminal 3
A> B signal supplied from 5 (“1” when the value of the N-bit code information is sequentially increasing on the time axis,
When the value of the N-bit code information is sequentially decreasing on the time axis, the signal is “0”. In FIGS. 4 and 5, “>”, “U”, “<”, and “D” are used. Is shown), and in the waveform data generator 54 other than the extremum section, the value of N-bit code information tends to increase sequentially on the time axis due to the A> B signal, or It is determined whether or not there is a decreasing tendency sequentially, and the mode of waveform data generation is changed.

FIG. 12 shows a state in which the signal of A> B signal “1” is supplied to the waveform data generating section 54 in the non-extreme section, that is, the value of the N-bit code information is on the time axis. FIG. 7 is a diagram illustrating a method of generating waveform data in a waveform data generation unit 54 in an area other than an extreme value section, taking an example of a case in which the waveform data is sequentially increasing. In addition, 2LSB
Even in the above-mentioned increase state, the increase for one LSB is extracted, so that it is the same as the increase of one LSB. FIG.
In (a) of FIG. 2, the section where the signal level is “「 ”has a period length of N1, and the section adjacent to the above section has a period length of“ N ”for the section where the signal level is“ Y ”. An example is shown in which the relationship between the period lengths N1 and N2 of the two adjacent sections is N1> N2. In this case, the numerical value Ns supplied from the comparator 24 to the input terminal 39 via the output terminal 29 of the detection section 5 of the change state of the signal waveform is N2. The numerical value Ns (= N2) illustrated in FIG. 12 is 16 (the clock signal pulse Pfs generated every sampling period Ts).
Are 16).

Further, the boundary position β between the section “ク” and the section “Y” in FIG. 12 is supplied to the input terminal 44 via the output terminal 30 of the detection section 5 of the signal waveform change mode. The end position γ of the section of “Y” is determined by the address value supplied to the input terminal 43 via the output terminal 27 of the detecting section 5 of the change mode of the signal waveform. In addition, the start position α of the “ク” section is indicated by an address value supplied to the input terminal 45 via the output terminal 31 of the detection unit 5 of the signal waveform change mode. Waveform data generator 5 other than extreme value section
4 is provided with a memory, an arithmetic circuit, and the like. From the boundary position β between the two adjacent sections “Y” and “K”,
Position 0 of Ns / 2 in the section "h" and N in the section "ya"
The additional code information having a value represented by the following formula is provided for each position of 0, 1, 2, 3,... Generate.

First, it is assumed that the value of the additional code information at the position of 0 set in the section "h" is 0. Next, the value of the additional code information at the position of 1 set in the section "h" is (1 LSB of N bits) / Ns (= N2). The value of the additional code information at the position 2 set in the section “h” is 2 × (1 LSB of N bits) / Ns (= N 2), and the additional code information at the position 3 set in the section “h” Is 3 × (1 LSB of N bits) / Ns (= N 2), and the value of the additional code information at the position 4 set in the section “G” is 4 × (1 LSB of N bits) / Ns (= N 2 ), The value of the additional code information at the position of 5 set in the section “h” is 5 × (1 LSB of N bits) / Ns (= N 2), and the addition at the position of 6 set in the section “h” The value of the code information is 6 × (1 LSB of N bits) / Ns (= N 2), and the value of the additional code information at the position 7 set in the section “G” is 7 × (1 LSB of N bits) / Ns ( = N2).

Next, the value of the additional code information at the boundary position β (the position of 8) between the section of “ク” and the section of “Y” in FIG. 12 is [Ｎ8 × (1 LSB of N bits) / Ns ( = N2)｝
−1 bit of N bits]. Hereinafter, the value of the additional code information at the position of 9 set in the section “Y” is [$ 9
× (1 LSB of N bits) / Ns (= N 2)｝ − 1 LSB of N bits], and the value of the additional code information at 10 positions set in the section “Y” is [｛10 × (1 L of N bits)
SB) / Ns (= N2)｝-N bits 1 LSB], and the value of the additional code information at 11 positions set in the section “Y” is [｛11 × (N bits 1 LSB) / Ns (= N
2) The value of the additional code information at twelve positions set in the section “Y” of｝ −N bits [1 LSB] is [｛12 ×
(1 LSB of N bits) / Ns (= N 2)｝ − 1 LSB of N bits], and the value of the additional code information at 13 positions set in the section “Y” is [｛13 × (1 LSB of N bits)
B) / Ns (= N2)｝-N bits 1 LSB], and the value of the additional code information at 14 positions set in the section “Y” is [｛14 × (N bits 1 LSB) / Ns (= N
2) The value of the additional code information at the fifteen positions set in the section “Y” of｝ −N bits [1 LSB] is [｛15 ×
(1 LSB of N bits) / Ns (= N 2)｝ − 1 LSB of N bits], the value of the additional code information at 16 positions set in the section “Y” is [｛16 × (1 LSB of N bits)
B) / Ns (= N2)｝ − 1 LSB of N bits].

By performing the above-described operation, the signal waveform based on the original N-bit code information in two adjacent sections “K” and “Y” is K 1 → K 2 → K 3 → K 4
The above-described operation is performed even though it is represented by → K5 → K6 → K7 → K8, and the least significant digit of the original N-bit digital signal is (M−N) bits of additional code information. , K1 → K2 → K3 → K5 → K7
The signal waveform as shown by K8, that is, the waveform between the position of δ and the position of ε in FIG. The result is as shown in FIG. FIG. 12B is a waveform when the portion from β to ε in the waveform shown in FIG. 12C is reduced by 1 LSB as described later.

The description so far made with reference to FIG. 12 is based on the case where the signal of which A> B signal is “1” is supplied to the waveform data generating section 54 other than the extreme value section, that is, This relates to the case where the value of the N-bit code information tends to increase sequentially on the time axis. However, a signal in which the signal A> B is “0” is supplied to the waveform data generation unit 54 outside the extreme value section. In other words, when the value of the N-bit code information is sequentially decreasing on the time axis, the above equation is simply changed (M−N).
Of course, the generation of the additional code information of the bit can be performed in the same manner as described above. Now, let us consider a case where the signal level is higher by 1 LSB of N bits in the section “C” shown in FIG. 12A than in the section “Y”.
From the boundary position β between two adjacent sections “Y” and “K”, 1 between the position 0 of Ns / 2 in the section “Y” and the position 16 of Ns / 2 in the section “Y” The following shows the additional code information to be generated for each position of 0, 1, 2, 3... 16 set for each sampling period.

First, the value of the additional code information at the position of 0 set in the section “h” is [｛16 × (N-bit 1
LSB) / Ns (= N2) {-1 bit LSB of N bits]. In addition, 1 set in
Is [{15 × (1 LSB of N bits) / Ns (= N2)} − 1LS of N bits
B], the value of the additional code information at the position of 2 set in the section “h” is [｛14 × (1 LS of N bits)
B) / Ns (= N2)｝-N bits 1 LSB], and the value of the additional code information at the position 3 set in the section “h” is [｛13 × (N bits 1 LSB) / Ns (= N
2) The value of the additional code information at the position of 4 set in the section “G” in｝ −N bits [1 LSB] is [｛12 × (N
1 LSB of bit) / Ns (= N 2)｝ − 1 L of N bit
SB], the value of the additional code information at the position of 5 set in the section “h” is [｛11 × (1 LSB of N bits) /
Ns (= N2)｝-N bits 1 LSB], the value of the additional code information at the position of 6 set in the section “ク” is [{10 × (1 LSB of N bits) / Ns (= N2)} −
The value of the additional code information at the position of 7 set in the section “h” is [{9 × (1 LSB of N bits) / Ns (= N 2)} − 1 LSB of N bits] In addition, the value of the additional code information at the boundary position β (position 8) between the section “G” and the section “Y” in FIG. 12 is [{8 × (1 LSB of N bits) / Ns (= N 2)}. -N
Bit 1 LSB].

Next, the value of the additional code information at the position of 9 set in the section “Y” is 7 × (N-bit 1LS).
B) / Ns (= N2), the value of the additional code information at 10 positions set in the section “Y” is 6 × (1 of N bits)
LSB) / Ns (= N2), 1 set in section "Y"
The value of the additional code information at the position 1 is 5 × (1 LSB of N bits) / Ns (= N 2), and the value of the additional code information at the 12 positions set in the section “Y” is 4 × (N The value of the additional code information at the thirteen positions set in the 1LSB of bits / Ns (= N2), section "Y" is 3 *
(1 LSB of N bits) / Ns (= N2), the value of the additional code information at the 14 positions set in the section “Y” is
The value of the additional code information at 2 × (N-bit 1 LSB) / Ns (= N 2) and 15 positions set in the section “Y” is (N-bit 1 LSB) / Ns (= N 2) and the section “ The value of the additional code information at the sixteen positions set in “Y” is 0.

Waveform data generator 5 other than the above extreme value section
In No. 4, after the additional code information obtained by performing the above operation is sequentially stored in the memory, the (MN) -bit additional code information read from the memory under the control operation of the control circuit 55 is This is given to the selector 58. Input terminal 3 described above
The output terminal 3 of the detection unit 5 of the change form of the signal waveform with respect to 8
When the signal indicating the extremum section supplied from No. 3 is “0”, the signal is given to the selector 58 as the signal of “1” by the inverter 56, so that the waveform data other than the extremum section is output. The (MN) -bit additional code information generated by the generator 54 is stored in the selector 5.
8 and the OR circuit 59, and is sent to the output terminal 47 of the (MN) bit signal generator 6.

As described above, the value of the N-bit code information to be subjected to the signal processing is changing on the time axis in such a manner as to sequentially increase or decrease.
When the length of a period (section) in which the value of the N-bit code information in each successive sampling cycle continues in the same state is different or the same for two adjacent sections, When the two sections do not include the extremum section, the waveform data generation unit 54 for the two sections other than the extremum section employs the method described above with reference to FIG. By applying (M−N) bits of additional code information, and for the section corresponding to the extremum based on the N-bit code information to be processed, the period length of the extremum section The (MN) -bit additional code information having a predetermined waveform is generated by the waveform data generating section 48 in the extreme value section.
If one of the two sections is an extremum section, the control signal generated by the control circuit 55 based on the information indicating the extremum section supplied to the control circuit 55 via the input terminal 38 is: By being provided to the waveform data generator 54 other than the extreme value section, the waveform data generator 54 other than the extreme value section prevents the calculation result for two sections including the extreme value section from being provided to the selector 58.

As described above, the (MN) -bit additional code information generated by the (MN) -bit signal generator 6 is output via the variable delay unit 7 to the output signal of the additional code information generator ACG. In the variable delay unit 7, the (M−M−) is added to the least significant digit of the N-bit code information in a state where the delay circuit 3 has received a certain time delay.
In a state where the N) -bit additional code information is continuous, it is added by the adder circuit 4 to add a time delay necessary to make the whole M-bit code information by adding (MN) bits. Give to the sign information. The variable delay unit 7 uses a random access memory to control write timing and read timing,
A predetermined time delay can be given to the (MN) -bit additional code information, and a predetermined time delay amount to be given to the (MN) -bit additional code information in the variable delay unit 7 Is determined by the delay control signal generated by the delay control signal generator 8.

FIG. 13 shows N-bit code information supplied to the input terminal 1 (indicated by an input waveform S at the left end of FIG. 13).
In response to this, N-bit code information with a predetermined time delay given by the delay circuit 3 (waveform S
d) and the N-bit code information belonging to the audible frequency band in the N-bit code information supplied to the input terminal 1 (indicated by the input waveform S at the left end of FIG. 13) through the band division filter. The signal is supplied to the detection section 5 for detecting the change of the signal waveform and the (MN) bit signal generation section 6
A signal obtained by delaying the (MN) bits of additional code information generated by
3 is indicated by the waveform Sa at the lower part near the center of the N-bit code information, as shown in the output at the right end of FIG.
The state where the (MN) -bit additional code information is added by the adder circuit 4 in a continuous state and the whole is M-bit code information is illustrated and described. The symbols a to h shown in the waveforms in FIG. 13 are for clarifying the correspondence between the waveforms. Note that the floor waveform Sa ′ indicated by a dotted line in the lower part near the center of FIG. 13 is generated in correspondence with one of the sections from the position of the boundary between two adjacent sections as described above with reference to FIG. The figure shows the calculated value of Sa before subtracting the value of 1-LSB of N bits when obtaining the value of the additional code information to be made.

That is, in the arithmetic circuit 4, the N-bit code information and the (M−N) -bit additional code information are added in an appropriate time relation, and the M-bit code information output from the addition circuit 4 is added. In order to obtain a waveform as illustrated in the right end of FIG. 13, the N-bit code information supplied to the input terminal 1 (indicated by the input waveform S at the left end of FIG. 13) With respect to the time position of the additional code information for each successive sampling period in the N-bit code information (shown by the waveform Sd in the upper part near the center in FIG. 13) in a state where a fixed time delay is given by the delay circuit 3 Input terminal 1
And a (MN) -bit signal generation unit 6 based on the N-bit code information (indicated by the input waveform S at the left end of FIG. 13) supplied to. (M-N) bits of the additional code information delayed by a predetermined time in the variable delay unit 7 (shown by a waveform Sa in the lower part near the center of FIG. 13). The delay time given to the (MN) -bit additional code information by the variable delay unit 7 is determined by the delay control signal generation time so that the time position of the information is correctly supplied to the addition circuit 4 in a state where the information is correctly corresponded. It needs to be controlled by a delay control signal generated by the unit 8. The same applies to the (MN) -bit additional code information generated corresponding to the extreme value section (see FIG. 11).

In the delay control signal generator 8, the clock signal CLK sent from the output terminal 34 and the output terminal out of the signals output from the output terminals 27 to 36 of the signal waveform change mode detector 5 are output. 29, the address value of the boundary position between the two sections sent from the output terminal 30, information on the period length of the extremum section sent from the output terminal 28, and the pole sent from the output terminal 33. Using the information indicating the value section, the address value of the start position of the section sent from the terminal 31, the clock signal Pfs, and the like, the sampling period Ts from the position of the boundary between two adjacent sections or the start position of the extreme value section Exist at a distance from each other (M-N)
Calculate the delay time to be given to the bit additional code information,
The variable delay unit 7 generates a delay control signal as given to the (MN) -bit additional code information,
It is supplied to the variable delay unit 7.

As described above, in the bit number conversion unit BNC,
N-bit code information delayed from input terminal 1 by a predetermined time by delay circuit 3 and N belonging to the audible frequency band supplied from band division filter 60
The (M−N) -bit additional code information created based on the bit-code information (N-bit digital signal) is added to the adder circuit 4 by the adder circuit 4 in the N-bit code information (N-bit digital signal). It is added to a state in which (MN) bits of additional code information continue in the lower digit and output.

In implementing the acoustic signal processing device of the present invention,
The upper limit frequency of the audible frequency band is set to, for example, 12 KHz, and 48 KHz is adopted as the sampling frequency exceeding twice the upper limit frequency of the audible frequency band. When the signal processing is performed on the code information of an N-bit digital audio signal obtained by converting the sequential sample values obtained as described above into a digital signal at a resolution of 1 / N, a cutoff frequency of 12 KHz is divided. It is possible to use a filter or a band division filter having a cutoff frequency of 20 KHz by setting the upper limit frequency of the audible frequency band to 20 KHz, for example, as shown in FIG. , Sampling frequency fs
It is not necessary to set fs / 4 for fs / 4. Further, 88.2 kHz is adopted as the sampling frequency exceeding twice the upper limit frequency of the audible frequency band.
A sequential sampled value obtained by sampling an analog sound signal in the form of an analog signal using a 2 kHz sampled signal is expressed as 1 / Nth power.
When performing signal processing on the code information of an N-bit digital acoustic signal converted into a digital signal with a resolution of, the cutoff frequency can be implemented using a band division filter having a cutoff frequency of 22.05 KHz.

As described in the above example, the upper limit frequency of the audible frequency band, the sampling frequency exceeding twice the upper limit frequency of the audible frequency band, and the acoustic signal in the form of an analog signal using the sampled signal. The sequential sample values obtained by sampling are
The cutoff frequency of a band division filter for obtaining N-bit code information belonging to an audible frequency band is audible by converting the code information of an N-bit digital sound signal converted into a digital signal with a resolution of 1 / N. When the acoustic signal processing device of the present invention is implemented by setting it to 1/4 of the sampling frequency exceeding twice the upper limit frequency of the frequency band, the frequency of the upper limit of the audible frequency band in each example is set. The frequency value of the second harmonic is a frequency value that is at least twice the cutoff frequency of the band division filter in each example, and the frequency value of the second harmonic of the upper limit frequency of the audible frequency band in each example described above is: Since the frequency value is 1/2 or more of the sampling frequency of the sampled signal in each example,
The second harmonic of the upper limit frequency of the audible frequency band in each of the above-described examples is removed by the low-pass filter provided in the DA converter, and does not cause distortion. Note that, in the embodiments described above,
The band division filter 60 is used as means for obtaining N-bit code information belonging to the audio frequency band. However, N-bit code information belonging to the audio frequency band is supplied from the input terminal 1 to the additional code information generation unit ACG. In such a case, it goes without saying that the above-described band division filter 60 is unnecessary.

[0081]

As is apparent from the above description, the acoustic signal processing apparatus of the present invention uses a sampled signal having a sampling frequency exceeding twice the upper limit frequency of the audible frequency band. From the code information of an N-bit digital sound signal obtained by converting a sequential sampled value obtained by sampling the sound signal in the form of an analog signal into a digital signal with a resolution of 1 / N, it is converted to an audible frequency band. Means for obtaining N-bit code information belonging thereto, and (M−N) -bit additional code information in the least significant digit of the N-bit code information belonging to the audible frequency band, so that M> N. (MN) -bit additional code information generating means for generating (MN) -bit additional code information required when performing bit number conversion on M-bit code information belonging to an audio frequency band; N Means for adding the (MN) -bit additional code information output from the (MN) -bit additional code information generating means in succession to the lowest digit in the code information of the digital audio signal In the audio signal processing device comprising: and the above-described audio signal processing device, (M−N) bits of additional code information are successively arranged at the least significant digit of N bits of code information belonging to the audio frequency band,
It is required when converting the number of bits to M-bit code information belonging to an audio frequency band having a relationship of M> N (M
-N) restores an audio signal in the form of an analog signal in which N-bit additional code information has generated N-bit code information belonging to the audio frequency band, and N-bit code information belonging to the audio frequency band. Within an error range of ± 0.5 LSB for a resolution 1 LSB of 1 / Nth power of 2 which is present between the obtained analog audio signal belonging to the audio frequency band and N bits belonging to the audio frequency band described above. (M−N) bits of additional code information that can make the integrated value of the analog signal waveform indicated by the sign information equal to the integrated value of the analog signal waveform indicated by the M-bit sign information. (N) -bit additional code information generating means, and the (M-N) bits in succession to the lowest digit in the code information of the N-bit digital audio signal.
Output from the bit additional code information generating means (M-
By generating the N) -bit additional code information, the sound signal processing apparatus of the present invention can use the above-described high sampling means when converting an analog sound signal into a digital signal according to the related art. The N-bit digital signal obtained by applying the noise shaping technique can be restored to a fine signal portion with a resolution higher than the resolution determined by the number of bits of the digital signal. Even if the code information is converted into M-bit code information having a relation of M> N, the dither placed in a frequency band higher than the audible frequency band has M> N with a relation of M> N. Since it is not converted to bit code information, the drawbacks mentioned as a problem with the prior art, that is, whether a reproduced sound signal of good sound quality can be obtained. Such a disadvantage does not occur in the audio signal processing device of the present invention, and in the audio signal processing device of the present invention, even when a digital signal encoded by the above-described noise shaping technique is reproduced, it is special. There is no problem, and the expected effect can be obtained by applying the noise shaping technology. Further, since the audio signal processing device of the present invention employs a special bit number conversion technology, the conventional method described above is used. As a result, compared with the case where the bit is enlarged, a high-quality sound signal can be restored with a higher resolution, and all the problems of the prior art described above can be satisfactorily solved by the present invention.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of an audio signal processing device according to the present invention.

FIG. 2 is a block diagram illustrating a specific configuration example of components of the acoustic signal processing device.

FIG. 3 is a block diagram illustrating a specific configuration example of components of the acoustic signal processing device.

FIG. 4 is a diagram illustrating a part of the operation of the acoustic signal processing device.

FIG. 5 is a diagram illustrating an operation of a part of the acoustic signal processing device.

FIG. 6 is a waveform chart for explaining a configuration principle and an operation principle of the acoustic signal processing device of the present invention.

FIG. 7 is a waveform chart for explaining a configuration principle and an operation principle of the acoustic signal processing device of the present invention.

FIG. 8 is a waveform diagram for explaining the configuration principle and operation principle of the acoustic signal processing device of the present invention.

FIG. 9 is a waveform chart for explaining the configuration principle and operation principle of the acoustic signal processing device of the present invention.

FIG. 10 is a waveform chart for explaining the configuration principle and operation principle of the acoustic signal processing device of the present invention.

FIG. 11 is a waveform chart for explaining a configuration principle and an operation principle of the acoustic signal processing device of the present invention.

FIG. 12 is a waveform chart for explaining the configuration principle and operation principle of the acoustic signal processing device of the present invention.

FIG. 13 is a block diagram and a waveform diagram of a part of components for explaining a configuration principle and an operation principle of the acoustic signal processing device of the present invention.

FIG. 14 is a frequency response characteristic diagram of the band division filter.

[Explanation of symbols]

1 ... N-bit digital signal input terminal, 2 ... M-bit digital signal output terminal, 3 ... delay circuit having fixed delay time, 4 ... addition circuit, 5 ... detection section of signal waveform change mode, 6 ... (MN) bit signal generator, 7 ... variable delay unit, 8 ... delay control signal generator, 9,13-15,19
-21, a D-type flip-flop, 10 ... a magnitude comparator, 11, 16, 17 ... an exclusive OR circuit,
12: AND circuit, 18: Address counter, 22, 2
3, a subtractor, 24, a comparator, 48, a waveform data generator for an extremum section, 49, a calculator for generating an N-bit 1LSB / Ns calculation value, 51, a signal waveform change information generator, 52 ... Signal waveform change mode information generating unit 53 ...
Signal waveform change interval information generation unit, 54: waveform data generation unit other than extreme value section, 55: control circuit, 56: inverter, 57, 58 ... selector, 59: OR circuit, 60: band division filter, BNC ... Bit number conversion unit, ACG ... additional code information generation unit,

Continuation of the front page (56) References JP-A-1-202029 (JP, A) JP-A-4-313386 (JP, A) JP-A-7-283794 (JP, A) Patent 2903996 (JP, B2) ( 58) Surveyed field (Int.Cl. ⁷ , DB name) H03M 7/14 G10L 19/00 G11B 20/10 321

Claims (4)

(57) [Claims] 1. Using a sampled signal having a sampling frequency exceeding twice the upper limit frequency of the audio frequency band, a sample value obtained by sampling an analog audio signal is represented by 2N Means for obtaining N-bit code information belonging to an audio frequency band from code information of an N-bit digital audio signal converted into a digital signal at a resolution of a power of 1; By adding (MN) bits of additional code information to the least significant digit of the code information, M bits belonging to an audible frequency band in a relationship of M> N
(M−N) bits of additional code information required when performing bit number conversion on bit code information are generated (M
-N) -bit additional code information generating means, and the (MN) -bit additional code information generating means, which is output from the (MN) -bit additional code information generating means consecutively with the lowest digit of the code information of the N-bit digital audio signal. Means for adding (MN) -bit additional code information. 2. A sequential sampled value obtained by sampling an analog audio signal in the form of an analog signal using a sampled signal having a sampling frequency more than twice as high as the upper limit frequency of the audio frequency band. Means for obtaining N-bit code information belonging to an audible frequency band from code information of an N-bit digital acoustic signal converted into a digital signal with a resolution of 1 /
By adding (MN) bits of additional code information to the least significant digit of the N-bit code information belonging to the audible frequency band, the M-bit code information belonging to the audible frequency band having a relation of M> N is obtained. The (MN) -bit additional code information required for performing the bit number conversion is an analog audio signal in which N-bit code information belonging to the audible frequency band is generated, and the audible signal. An error range of ± 0.5 LSB for a resolution 1 LSB of 1 / N 2 which exists between an analog audio signal and an audio signal belonging to an audible frequency band obtained by restoring N-bit code information belonging to the frequency band. Within, the integral value of the analog signal waveform indicated by the N-bit code information belonging to the audible frequency band and the integrated value of the analog signal waveform indicated by the M-bit code information (MN) -bit additional code information generating means which is equivalent to (M-N) -bit additional code information, and the last digit in the code information of the N-bit digital audio signal. And (M-
(M) output from the N-bit additional code information generating means.
-N) means for adding bit additional code information. 3. The frequency value of a sampled signal having a sampling frequency exceeding twice the upper limit frequency of the audio frequency band is set to 8
3. The acoustic signal processing device according to claim 1, wherein the frequency is set to 8.2 KHz, and the division into an audible frequency band and a frequency band higher than the audible frequency band is performed at a frequency value of 20 KHz. 4. The frequency value of a sampled signal having a sampling frequency exceeding twice the upper limit frequency of the audio frequency band is set to 4
3. The acoustic signal processing device according to claim 1, wherein the frequency is set to 8 KHz, and the division into an audible frequency band and a frequency band higher than the audible frequency band is performed at a frequency value of 15 KHz.