JPH07123214B2 - D / A converter - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of SN ratio and distortion particularly at a minute level when used for digital-analog conversion such as digital audio.

[0002]

2. Description of the Related Art Conventionally, in an analog signal that is digitally transmitted or recorded / reproduced through an AD and then DA converted, a sample data string having a limited bit length can be used at the digital stage. A so-called dither or the like that adds a small amount of high-frequency noise at the time of AD is used for this improvement accompanied by a quantization distortion commensurate with the length, but there is a drawback that the noise increases.

[0003]

In the AD and DA systems at the above-mentioned minute level, even if the noise before AD is the least bit (LSB) or less, each LS of AD is
If there is noise near the B threshold, it will appear as 1 LSB noise, and with dither added, there is almost always a high frequency noise of 1 LSB or more and there is a problem at a minute level. , S / N is good reproduction.

[0004]

According to the present invention, a change point of input sample data is detected in order to form a digital low-pass filter which acts on a minute level for reducing these minute levels of noise and distortion, and perform DA extension for DA conversion. Then, at this change point, data below the LSB is generated before and after the change sample, and in addition to the input data, it is realized by making the change point a gentle change.

[0005]

EXAMPLE An example of the present invention will be described. A block diagram showing the whole is shown in FIG. First, the input data is delayed by one sample in the shift register 1-1 and the comparator 1-2
The difference between samples is output as data including the direction of change such that the change is 1 LSB change or 1 to 2 LSB change which is the target minute level, or +1 in the positive direction when it is 1 LSB or more and -1 in the negative direction. This comparator 1-2
Is widely known and will be omitted.

On the basis of the data corresponding to this change point, the data generation circuit 2 generates data for moderating the slight level change. FIG. 2 shows this embodiment. In this embodiment, as shown in the waveform diagram of FIG. 2B, an example is shown in which when the input data Din changes in 1 LSB step, it changes over two samples like Dout. In this case, the input in Fig. 2 (a) is +
When 1 appears, shift registers 2-1 and 2-2 are shifted for each sample, and at this time, +1 corresponds to shift register 2
When +1 appears at the output of -1, it becomes the value of K, and when it appears next at the output of 2-2, it becomes -K. These are added by the data in the sample by the adder 2-5 to generate the added output. Use as data.

The value of K for this data generation is shown in FIG.
In the case of, if K becomes 1/2 cycle of the sine wave over 4 samples, K becomes 1/4 of LSB. In the case of input -1, the output is in the order of -K, + K as shown in b-3. +1 or -1 is used as the change point signal by the OR circuit 2-7,
On the other hand, +1 at this time is taken as a code. That is, +1 and-
Since 1 is not the same time, if the change point is +1 then a positive change,
If it is -1, the change point and 0, that is, a negative value is entered in the shift register and taken out as K from the outputs 2-1 and 2-2 of the D flip-flop.

At this time, the Sign output becomes the inverted data when the output of 2-2 is passed through the inverter 2-6. This data K is an absolute value, and Sign represents polarity. That is, it becomes a sine magnitude code, and if the addition input is +
If K and -K, the output is 0. As shown in FIG. 2B, when the value of K is ¼, it is sufficient to output a value that is 2 bits smaller than LSB, and it is sufficient to simply wire 001 (1 LSB level).

The addition output by these is a sine magnitude, and is code-converted into a general binary code by the code conversion 2-8 in order to be aligned with the input data of the upper bits. As is generally known, when the polarity bit is 0 (negative), the lower bit is inverted and 1 (minimum bit of generated data) is added. This data output is used as the upper input data and the shift register 1-
At 3, the target data out is obtained by adjusting the timing as shown in FIG. FIG. 3 is a diagram showing an improved state of the output. The noise in the conventional LSB is removed and the output becomes smooth with a solid line.
The reproduction does not change at all, and the noise is removed where the S / N at the time of reproducing a very small level becomes a problem.

In FIG. 2, the data is generated over two samples, but as shown in FIG. 4, the shift register is increased and the data is generated over four samples, so that the low frequency is removed. In this case, instead of K, the data of K1 and K2 are output and added. As described above, the noise in the minute level change region such as the LSB change is removed, and the staircase distortion becomes smooth, and the effect of improving the distortion is great. Further, in a general use state, since the data generation output is about LSB, the high frequency band is not greatly affected by the filter at the normal output signal level. Also, when the comparator output changes slightly (1LSB
.About.2 LSB) does not change in the large level area.

[0011]

According to the present invention, the sample data is set as the upper bit before and after the change point where the sample data changes in the minute level change region, and the lower bit by the minute level data string is added to this to lower the high frequency level. As described above, since the waveform after the DA conversion is changed smoothly, the high frequency noise is removed, the stepwise distortion is smoothed, and the minute distortion can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram (a) and a waveform diagram (b) of a data generation circuit.

FIG. 3 is a diagram for explaining a waveform.

FIG. 4 is a block diagram (a) and a waveform diagram (b) showing another embodiment of the present invention.

[Explanation of symbols]

 1-1 Register 1-2 Comparator 1-3 Register 1-4 Addition 2 Data Generation Circuit

Continuation of front page (56) Reference JP-A-5-304474 (JP, A) JP-A-4-354208 (JP, A) JP-A-6-6217 (JP, A) JP-A-62-287717 (JP , A) JP-A-1-164128 (JP, A) JP 60-17183 (JP, B2)

Claims (1)

[Claims] 1. A device for D / A converting sample data having a predetermined word length, means for detecting a change point at which a difference between sample data changes by a predetermined minute level, and at least one sample before and after the change point. Means for generating a predetermined minute level data sequence for reducing the data change rate over the above, and the sample length is used as an upper bit, and the generated minute level data sequence is added as a lower bit before and after the detected change point. D / A conversion , characterized by comprising means for expanding
Exchange device .