JPH0773187B2 - Bit length expansion device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in reproduction distortion when used for digital-to-analog conversion such as digital audio, especially at a minute level.

[0002]

2. Description of the Related Art Conventionally, in the case of digitally transmitting or recording / reproducing an analog signal through AD and DA, one sample data having a limited bit length is used at the digital stage, so that the bit length is Accompanied by appropriate quantization distortion.

[0003]

In particular, in the reproduction of a minute level, the distortion increases as it approaches the least significant bit (LSB), so that the distortion of a sine wave signal approaches a square wave.

[0004]

According to the present invention, a means for detecting a minute level change by obtaining a difference between sample data of digital data having a predetermined bit length inputted, and a minute level change detected by the detecting means. A means for generating a minute level data of a predetermined pattern over several samples before and after, and the generated minute level data for each minute level change is added to the upper sample data, and a change smaller than the minute level change is made during one sample. The bit length expanding device is provided with a means for making the bit number larger than the number of bits of the digital data input so that Therefore, the present invention provides a device capable of reducing these minute levels of quantization distortion, increasing the bit length, and performing DA conversion. In order to realize this, by extracting the difference between the respective sample data of the reproduced digital signal, there is no data change between samples, 1 LSB.
1 LSB with no change over a few samples by extracting large amplitude changes, etc., where only changes occur or more
Only the minute level portion where only the change or no change is extracted, and the data below the LSB is generated so that the level change output is gentle over several samples before and after this 1LSB change. Even if the LSB change point is close by outputting this generated output corresponding to 1 LSB change point, by adding these generated outputs, an extended bit that gives a smooth data change as the entire waveform is obtained, and this is an analog signal. Can be converted to.

[0005]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A block diagram will be described below. A block diagram showing the whole is shown in FIG. 1, and its waveform diagram is shown in FIG. The data Din for each sample, which is a reproduced word of finite length bits, is detected by the difference extraction circuit 1 as a change in data between sample data.

Provided are shift registers 1-1 and 1-2 which move data at every sample clock fs shown in FIG.
The data between these 1 samples are compared by the comparator 1-3, and the same data between these 1 samples is output 0 without change, change of +1 LSB, change of -1 LSB or less, or change of large amplitude H or more. Difference extraction is performed. Next, these difference data are input to the shift register 2 and also input to the shift register 2 so as to be shifted by the sample clock in order to detect these change patterns over several to several tens samples according to the purpose.

Based on the data in the shift register 2, a minute level section or a change interval (frequency) thereof is extracted, that is, a pattern is extracted to determine data generation corresponding to one LSB change which is a minute level change.

As shown in FIG. 2, the pattern extracting section 3 generates lower extension data according to the LSB change according to the sample distance from the LSB change point. Now, data generation F1 corresponding to a relatively gentle low frequency component,
Two means for generating high frequency component F2 will be described.

From the 1LSB change point in the positive direction, a section of χ in which an intermediate sample changes to -1LSB without data change, or conversely, a section of χ'from -1 to +1 is indicated by d (i ) Or more, and if the interval of the same polarity is (y) is (ii) or more, the output of F1 is output from the pattern extraction unit 3 corresponding to the 1LSB change point, and as shown in e. If χ is less than (i) and greater than (i '), F2 is output. (Here (ii) is not used and F1 F
No output when both outputs are H inputs. )

Based on this pattern output data, the data of F1 and F2 are shifted to the shift register 4,
During this process, d1 or d corresponding to F1 for each sample
Data corresponding to 1'and F2 are generated as shown in d2 or d2 ', respectively. By adding these, extended data is generated, and DA conversion is performed as bit-extended data in addition to upper data. Here, the phase of the upper data is adjusted by the shift register 6 so as to be in the same position as the data generation output.

The pattern extraction data at each LSB change point is shown in FIG. 2 according to the upper data of the input data a in FIG.
The solid line generated output is obtained by adding these lines as shown by the broken line indicated by c, and the overall output added with the upper data can obtain a smooth waveform without distortion as shown in b of FIG. it can.

Further, each part will be described in detail. Figure 4
The pattern extractor 3 will be described. The output of F1 is
The above (i) is shown with 17 samples or more and (ii) with 5 samples or more. The OR circuits a24 and a8 take OR's of + 1LSB and H from the outputs of the registers 2-24 and 2-8 to clear the counter a12, and also the OR's of -1 and H to clear the counter b13. The counters 12 and 13 count 16 samples, and output from the 17th sample. When the output of the register 2-8 is +1 or -1, the output of the counter b13 or the output of the counter a12 which is cleared with the opposite polarity and the AND gate G1 or G2 is taken to be true. 16 changes of ± 1LSB to 8 points
There is no LSB change and H signal before and after the sample, and the condition (i) is detected.

Further, these outputs are sandwiched by the register 2-8, the OR gates C4 to C12 of the outputs of the ± 4 sample registers 2-4 to 2-12 are detected by the OR gate G3, and are respectively detected by the AND gate G4 and the AND gate G4 '. Take the AND gate. This is the condition (ii). Where C4 to C12
In case of inputting other than the same polarity, G1 or G2 is not established if there is an opposite polarity or H signal, and only condition (ii) is established. These outputs are put in the shift register 4.
Regarding F2, similarly, the take-out position of the shift register 2 and the counter value may be set. F2
If the condition of (i ') of 5 is more than 5 samples, the register 2-4 corresponds to the register 2-8 of F1 and the register 2-12 corresponds to the output of the register 2-24. 8 samples are recommended. Also, here, the one corresponding to the OR gate G3 is unnecessary. One here one
If there is an output of F1 corresponding to the change of LSB, the condition of F2 is satisfied, so that F1 is used and F2 is not output. Therefore, take an OR gate of ± F1 and latch 1 for each data change.
If there is F1 at the gate G5 or G5 'through the inverter 15 which latches the flag of F1 at 4, the F2 is prohibited. As a result, the long cycle has only F1 and the short cycle has only F2, which are not output identically.

As a result, one of the outputs of F1F1 'and F2F2' appears corresponding to a predetermined 1LSB change point and is input to the shift register 4 and shifted. Here, the shift register 4 is used for data generation, and the input timing of F1 and F2 is 4 samples corresponding to the registers 2-8 and 2-4, so that F2 is output later and the input is delayed by 4 samples. The timing will match. Above F1
The state of F2 is shown in FIG. For the convenience of the output from the shift register 4, + F1 and -F1 are ORed, and ± F1 signal (± 1 LSB) and + F1 or ± 1 LSB F1 changes the sign by + F1 to indicate the polarity. It can be a bit (Sign), and similarly ± F2 and the sign bit are put in the shift register 4.

Next, FIG. 6 shows a block diagram of the data generating circuit 5 by the output of the register. Each register 4-8 ~ 4
--8 is divided into left and right from the center, the sign bit output on the left side is unchanged, and the sign bit is inverted via the inverter I on the right side. In addition, the left and right data are the same data with the center sandwiched. As shown in FIG. 7, there are 8 kinds of data for F1 and it is preferable to use 1/4 cycle of sine wave from D11 to D18 as shown in the figure. This data changes ± 1LSB for each register, that is, F
Output from the register that outputs 1 or F2.
For example, if the register 4-8 has F1 and the register 4--4 has F2, these data are output from two places. Of course, the Sign bit having these polarities is also output here at the same time. If it is 4-bit data, Si
Except for gn, it is represented by 3 bits.

In FIG. 8, these data outputs are performed by the full adder Σ. Data addition is omitted because it is publicly known. Each data can be generated only by wiring corresponding to a required data value as shown in FIG. Here, as for the data, 1/4 part of the sine wave is D18-D as shown in FIG.
Positive data rises with respect to + LSB change input such as 11 or D24 to D21, and it becomes negative data across the center and reverses and decreases to 0. -In 1LSB change,
Since the Sign bit is 0, the opposite data change occurs, the negative data increases, and the positive value is obtained by sandwiching the center and becoming positive.

As a result, data corresponding to d1 or d2 shown in FIG. 2 is obtained. With the addition output of FIG.
It becomes one generation output like the data of C and is added to the upper data to obtain data with bit-extended smooth and less distortion.

In the embodiment, two types of data generation have been described, but it is of course possible to increase the number to correspond to a wide frequency range, and to cope with a change of 2 LSB or the like. Even if only one piece of data is generated, the output data at the change points are fully added one after another, so the connection of the final data is smooth as shown in the figure, and a wide frequency change waveform can be accommodated.

[0019]

As described above, according to the present invention, by detecting a slight change in the signal level, the output signal is smoothly extended in the bit length to the small signal level region. The change can be made smoothly, and the noise generation due to the pulse distortion generation in the high frequency band can be eliminated.

[Brief description of drawings]

FIG. 1 is a block diagram of the present invention.

FIG. 2 is a diagram for explaining a waveform.

FIG. 3 is a block diagram showing difference extraction.

FIG. 4 is a block diagram illustrating a pattern extractor.

FIG. 5 is a diagram showing timing.

FIG. 6 is a block diagram of a data generation circuit.

FIG. 7 is a diagram for explaining a data-generated signal.

FIG. 8 is a block diagram showing addition.

[Explanation of symbols]

 1 Difference Extraction Circuit 2-1 to n Shift Register 3 Pattern Extraction Section 4 Shift Register 5 Data Generation Circuit 6 Shift Register 7 Addition Circuit

Claims (1)

[Claims] 1. A means for detecting a minute level change by obtaining a difference between sample data of digital data having a predetermined bit length inputted, and a predetermined number of samples before and after the minute level change detected by said detecting means. Means for generating the minute level data of the pattern, and adding the generated minute level data for each of the minute level changes to the upper sample data so that the change is smaller than the minute level change in one sample. A bit length expansion device comprising means for making a bit number larger than the number of bits of the input digital data.