JP2637259B2 - Signal transmission path - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is configured such that, when reproducing a signal source output of a digital signal, an output terminal is connected to a final stage of signal processing for a minimum necessary time. It relates to a signal transmission path.

[Conventional technology]

In a signal transmission path for transmitting a signal source output, such as audio equipment, the output signal itself of the signal source was amplified, and at the same time, the noise included in the signal and the noise generated in the amplification / reproduction system were all amplified. . The S / N ratio is the ratio of the noise level generated by the amplification / reproduction system when there is no signal source output to the signal level at the time of amplification / reproduction receiving the signal source output.
This SN ratio is one of the values indicating the performance of the audio equipment, and is affected by all the wiring inside and outside the equipment and the amplifying elements inside the equipment. In a digital device, a signal is converted into an analog signal by a D / A converter, and the signal is amplified and reproduced. The noise during the conversion is large enough to affect the SN ratio of the reproducing system.
Therefore, a gate circuit is inserted after the D / A converter, the gate circuit is always closed, and the signal transmission path is disabled. It has been proposed to open a gate circuit only when a signal to be amplified arrives.

[Problems to be solved by the invention]

When a signal to be amplified arrives, the noise generated inside is smaller in level than the signal to be amplified, so that the output from the speaker often does not matter.

On the other hand, when a signal to be amplified does not arrive at the input terminal, there is a problem because only noise is constantly amplified.

Further, the gate circuit control means already proposed has a drawback that it is complicated when adjusting the timing of opening the gate circuit.

An object of the present invention is to improve the above-mentioned drawbacks, and when the signal to be amplified is not input, of course, even if it is input, the time related to the frequency of the signal is cut off the signal transmission path, and the SN
It is an object of the present invention to provide a signal transmission path having the same effect as the improvement of the ratio.

[Means for solving the problem]

FIG. 1 is a diagram showing the principle configuration of the present invention. In FIG. 1, 1 is a signal source of a digital signal, 2 is D / A conversion means which is the next stage of the signal source, 3 is a signal output terminal, 4 is a gate means, and signal transmission from the signal source 1 to the terminal 3 is performed. Forming a road. Reference numeral 5 denotes signal state detecting means, and 6 denotes time setting means.

The present invention has the following configuration in a signal transmission path for outputting to a signal output terminal 3 via a D / A conversion means 2 for converting an output of a digital signal source 1 into an analog signal and a signal gate means 4. I have. That is, the time setting means 6 and the output of the time setting means 6 are applied to receive the output signal of the signal source of the digital signal, detect the state of the signal, and change the output signal of the signal source of the digital signal to a predetermined state. And a signal state detecting means 5 for generating a detection signal after a time set by the time setting means 6 from the time when the time becomes.

[Action]

The output of the digital signal source 1 in FIG.
The signal is converted into an analog signal by the A conversion means 2 and reaches the gate means 4. Since the gate means 4 is always closed, the analog signal does not reach the signal output terminal 3 immediately. The output of the digital signal source 1 is applied to the signal state detecting means 5 to detect the state of the digital signal. That is, each state is detected that the digital signal has been applied to the signal state detecting means 5, that the digital signal has been applied, that the application has been continued, and that the application has been completed. Then, a signal detecting that the voltage is continuously applied is sent to the gate means 4, and is opened. Therefore, the converted analog signal reaches the signal output terminal 3. The signal state detection means 5 sends a detection signal to the gate means 4 after a lapse of the time set by the time setting means 6 from the start time of the digital signal application, for example. The gate means 4 is open up to that signal, and after the detection signal arrives, the gate means 4 is closed. Therefore, the analog signal arrives at the output terminal 3 for a time irrespective of the time during which the digital signal is output from the signal source 1.

〔Example〕

FIG. 2 shows a signal state detection circuit 5 and a time setting circuit 6 as an embodiment of the present invention. FIG. 2 shows a block configuration in which the time from the start of the application of the digital signal to the start of the gate operation can be set to a predetermined value. In FIG. 2, reference numeral 1 denotes a signal source of a digital signal;
Denotes a non-zero detector, 54 denotes an n-stage counter, 55 denotes a D-type flip-flop, and 58 and 59 denote AND circuits. Reference numeral 60 denotes a central processing unit such as a microcomputer, 61 denotes a data bus, 62 denotes a data matching circuit, and 63 denotes a time data latch. The central processing unit 60 shows an example of a time setting circuit. FIG. 3 is an operation waveform diagram for FIG. In FIG. 3, both the serial data and the shift lock are applied from the digital signal source 1 to the non-zero detector. The time data for starting the gate operation by the central processing unit 60 is transmitted to the time data latch 63 via the data bus 61. The counter 54 is cleared when the clear terminal CLR is “H”, and counts up when the terminal CLK to which the latch clock is applied rises when CLR is “L”. Since the output of the non-zero detector 53 is applied to the clear terminal CLR of the counter 54, the counter 54 starts transmitting the detection signal "L" as shown in FIG.
Starts counting up. The data match detection circuit 62 compares the data of the time data latch 63 with the counter value of the counter 54, and when the value of the counter 54 matches,
The output "H" is sent to the D-type flip-flop 55 as data. The D-type flip-flop 55 is cleared when the output of the non-zero detector 53 is "H", and the next data terminal D and clock terminal
Operates on the input signal to CK. Since the data D is taken in at the rising edge of the clock terminal CK, the output of the data coincidence detection circuit 62 is supplied to the D terminal, and the clock obtained by inverting the latch clock by the inverter 58 and the logical operation performed by the AND circuit 59 are applied to the CK terminal. Therefore, the output of the data coincidence detection circuit 62 is latched as shown in FIG. Therefore, it becomes “L”. The gate circuit 4 can start the gate operation by this signal. The central processing unit performs processing from the start of counting of the counter 54 to the detection of the data match detection circuit 62.
Can be set arbitrarily with data from 60.

Here, as the number n of stages of the counter 54, the cycle time of the latch clock supplied from the digital signal source 1 × 2 ⁽ⁿ⁻¹⁾
Is set in advance so as to be slightly longer than the maximum time during which all the data becomes “L” in the digital data. For example, if it corresponds to the half-wave of the minimum value of the generated analog frequency of 20 Hz, 25 m
It is set in advance to be slightly longer than seconds.

FIG. 4 shows a digital signal source D / A as another embodiment.
A case where the signal state detection circuit and the gate circuit are provided in each set, and two sets are provided as a plurality of sets of converters will be described. Signal state detection circuits 50 and 51 are circuits for detecting that all signals from a plurality of digital signal sources have become “0”;
For example, it is assumed that an OR gate is inserted on the input side.
It is desirable to connect a delay time setting circuit. According to this configuration, the signal can be guided to a smaller number of signal output terminals than the data signals of the plurality of signal sources.

FIG. 5 is a block diagram when an electronic musical instrument is configured as an application example of the present invention. In FIG. 5, the keyboard section 20 is composed of a keyboard including a plurality of keys for controlling musical tone generation, and may be composed of a plurality of keys. The panel unit 21 includes a switch for setting a tone of a musical tone, a display device for indicating a state, a tablet switch for selecting a tone, and the like. The ROM 22 is composed of a program and a data section, controls the operation of the central processing unit 60, and the data is related to various processes. RAM23 is keyboard part 2
The panel unit 21 has an area for temporarily storing data for performing a process related to the signal source 1 of the digital signal. Therefore, the central processing unit 60 scans the key switch included in the keyboard unit 20 according to the program in the ROM 22 and assigns and stores the state to the RAM 23, and scans the state of the switch of the panel unit 21 to change the state. Store in RAM23. Also, based on the information stored in the RAM 23, the ROM 22
The data is transmitted to the signal source 1 of the digital signal so as to generate desired digital data (musical sound waveform data) in accordance with the data. It also sends data for controlling the gate time (time of the control signal to the gate circuit 4) to the signal state detection circuit 5.

〔The invention's effect〕

As described above, according to the present invention, since so-called noise during silence is effectively blocked, when viewed before and after silence, the signal-to-noise ratio after passing through the gate means in the signal transmission path is equal to the gate means. Compared to the previous signal-to-noise ratio, it has been significantly improved. Therefore, it is effective when applied to loudspeakers and audio equipment. In addition, since the signal state detecting means can be easily formed into a digital circuit, the configuration can be integrated with a signal source to obtain a smaller signal transmission path. Furthermore, since the control when the operation control time of the gate means is arbitrarily set can be easily performed, the cutoff time is set in relation to the frequency of the signal input to the signal transmission line, and the input signal is more than necessary. It is possible to set an optimal shut-off time without a long time.

[Brief description of the drawings]

 FIG. 1 is a diagram showing a principle configuration of the present invention, FIG. 2 is a diagram showing a configuration of an embodiment of the present invention, FIG. 3 is an operation waveform diagram of FIG. 2, and FIG. FIG. 5 is a diagram showing an example configuration, and FIG. 5 is a diagram showing an application example of the present invention. DESCRIPTION OF SYMBOLS 1 ... Digital signal source 2 ... D / A conversion means 3 ... Signal output terminal 4 ... Gate means 5 ... Signal state detection means 6 ... Time setting means

Claims (3)

(57) [Claims] 1. A signal transmission path for outputting to a signal output terminal via D / A conversion means for converting an output signal of a signal source of a digital signal into an analog signal, and a signal gate means, wherein a period of the analog signal is Time setting means for outputting data for setting a time relating to the digital signal; receiving the output signal of the signal source of the digital signal, detecting the state of the signal; A signal state detection means for generating a detection signal after a time set by the time setting means from a time when the output signal of the source is in a predetermined state, and a gate operation of the signal gating means by an output of the signal state detection means A signal transmission path characterized by controlling 2. The signal transmission line according to claim 1, wherein the signal state detection means is configured to process a parallel signal, and at least a signal source of the digital signal is formed on a common substrate. Road. 3. A signal output through D / A conversion means for converting output signals of a plurality of digital signal sources into analog signals, respectively, and signal gate means having a smaller number of signal sources than the plurality of digital signal sources. A signal transmission path for outputting to a terminal is formed, and the signal gate means and the same number of time setting means each outputting data for setting a time related to the cycle of the analog signal, and the outputs of the time setting means are applied. And a signal state detecting means for generating a detection signal after a time set by the time setting means from a time when an output signal of the signal source of the digital signal is in a predetermined state. A signal transmission path for controlling a gate operation of a corresponding signal gate means.