JP2668854B2 - DA converter - Google Patents
DA converterInfo
- Publication number
- JP2668854B2 JP2668854B2 JP34739293A JP34739293A JP2668854B2 JP 2668854 B2 JP2668854 B2 JP 2668854B2 JP 34739293 A JP34739293 A JP 34739293A JP 34739293 A JP34739293 A JP 34739293A JP 2668854 B2 JP2668854 B2 JP 2668854B2
- Authority
- JP
- Japan
- Prior art keywords
- data
- output
- level
- noise
- detected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Analogue/Digital Conversion (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は、CDプレーヤ等のディ
ジタルアナログ変換の改良に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of digital-analog conversion of a CD player or the like.
【0002】[0002]
【従来の技術】CDプレーヤ等のアナログ信号をディジ
タル信号に変換しアナログ信号に戻す場合、ディジタル
信号の段階で所定のビット数しか扱えない。CDシステ
ムでは16ビットであるが、これより微少な信号は丸め
られてしまう。このためにアナログ信号よりディジタル
信号に変換する段階でアナログ信号に高域ノイズを加え
るディザーを用いたり、最近では所定のビット数より多
い20bit 等のAD変換を用い、20bit でディジタル
信号に変換し、ノイズシェーピングの手法によって16
bit に減らし誤差を帰還することで中低域の通常周波数
領域の誤差を減少させている。2. Description of the Related Art When an analog signal from a CD player or the like is converted into a digital signal and returned to an analog signal, only a predetermined number of bits can be handled at the stage of the digital signal. The CD system has 16 bits, but a signal smaller than this is rounded. Therefore, at the stage of converting an analog signal to a digital signal, a dither that adds high frequency noise to the analog signal is used, or recently, an AD conversion of 20 bits or more, which is larger than a predetermined number of bits, is used to convert the digital signal to 20 bits. 16 depending on the noise shaping method
By reducing the error to bits and feeding back the error, the error in the normal frequency region in the middle and low frequencies is reduced.
【0003】[0003]
【発明が解決しようとする課題】これらによってディジ
タル化されたものではサンプリング周波数fs の1/2
の周波数の近くでノイズが上昇してしまう欠点があっ
た。このためこれらの高域ノイズを減少させ、かつ通常
の音楽の高域成分をおとさないようにし、伝送ビットの
最少ビット(LSB)以下のレベルまで高精度に再生する
ことを目的とするものである。In the case of digitized data by these, 1/2 of the sampling frequency fs is used.
There was a drawback that the noise increased near the frequency of. Therefore, it is an object of the present invention to reduce these high-frequency noises and prevent the high-frequency components of normal music from being affected, and to reproduce with high precision up to the level of the least significant bit (LSB) of transmission bits. .
【0004】[0004]
【課題を解決するための手段】本発明はサンプル毎のデ
ータが前サンプル値との変化が交互に変化することを検
出し、所定レベル以下の変化の場合、高域信号を減衰さ
せ最少ビット以下のデータを生成しビット数を入力デー
タより拡大してDA変換するようにする。According to the present invention, it is detected that the data of each sample changes alternately with the previous sample value, and when the change is less than a predetermined level, the high frequency signal is attenuated and less than the minimum number of bits. Data is generated, the number of bits is expanded from the input data, and DA conversion is performed.
【0005】[0005]
【作用】これによって高域ノイズが減少し歪の少ないア
ナログ信号が再生できると共に一般の再生信号では高域
減衰のない再生が可能となり、再生品質が向上する。As a result, it is possible to reproduce an analog signal with reduced high-frequency noise and less distortion, and to reproduce a general reproduced signal without high-frequency attenuation, thereby improving reproduction quality.
【0006】[0006]
【実施例】図1に本発明の実施例のブロック図を示し説
明する。所定ビット数nのサンプルデータ列が入力さ
れ、サンプル周波数fs のクロックCKでシフトレジス
ター1,2に順次データをシフトする。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A block diagram of an embodiment of the present invention will be described with reference to FIG. A sample data sequence having a predetermined number of bits n is input, and data is sequentially shifted to the shift registers 1 and 2 by a clock CK having a sample frequency fs.
【0007】これによりシフトレジスター2の出力と1
の出力は1サンプルずれたデータが出力されており、こ
の両出力のデータを引算器3で引算し、差に対応したデ
ータを出力する。この差の出力をパターン検出器4によ
ってノイズシェーピング等高域ノイズが多い微少信号レ
ベル領域の信号を判別し、その場合の差データをゲート
6により通過させ、パターン検出されない通常レベルの
信号データ等は通さない。As a result, the output of the shift register 2 and 1
Is output as data shifted by one sample, and the data of both outputs is subtracted by the subtractor 3 to output data corresponding to the difference. The output of this difference is used by the pattern detector 4 to discriminate a signal in a small signal level region in which high-frequency noise such as noise shaping is large, and the difference data in that case is passed through the gate 6 so that normal level signal data or the like in which no pattern is detected is detected. Do not pass.
【0008】ここでパターン検出の遅れなどを補償する
ゲート6のタイミングを合わせるための必要段数のレジ
スター5を引算器3の出力に設ける。この微少領域の高
域ノイズ検出された差分データはシフトレジスター7に
入れ順次シフトし、その各段のレジスターよりデータ値
に対応したデータ発生部を介しデータを得る。Here, the output of the subtracter 3 is provided with a register 5 having a required number of stages for adjusting the timing of the gate 6 for compensating for the delay in pattern detection. The difference data in which the high-frequency noise is detected in the minute area is put into the shift register 7 and sequentially shifted, and the data is obtained from the register of each stage via the data generating section corresponding to the data value.
【0009】ここでデータ発生部はROM8よりなり、
シフトレジスター7のデータに対応したあらかじめ計算
されたデータをROM8のデータとして入れておき、デ
ータの値をアドレスとしデータを読み出すことで容易に
得ることができる。各レジスター7から対応して得られ
たROM8よりの各データを加算器9で加算し、さらに
入力のnビットのデータに加算しnビット以下までのデ
ータまで拡大して出力しDA変換する。ここで加算器9
よりの出力は入力データのノイズの逆のデータとなり加
算することでノイズを打ち消すように作用する。Here, the data generating section comprises a ROM 8,
This can be easily obtained by previously storing data calculated in the ROM 8 as the data in the ROM 8 corresponding to the data in the shift register 7, and using the data value as an address to read the data. The respective data from the ROM 8 obtained correspondingly from the respective registers 7 are added by the adder 9, further added to the input n-bit data, expanded to the data up to n bits or less, output and DA-converted. Adder 9 here
The output of becomes a data opposite to the noise of the input data, and acts to cancel the noise by adding.
【0010】入力より加算器9までに到る遅延時間と丁
度入力データの時間を合わせるためシフトレジスター1
0を設ける。ここでROM8のデータについては加算器
9の出力データと入力データをシフトレジスター10を
介し加えると、高域の減衰したデータとなるように作用
するデータを発生させる。The shift register 1 is used to make the delay time from the input to the adder 9 exactly equal to the time of the input data.
0 is provided. Here, regarding the data of the ROM 8, when the output data of the adder 9 and the input data are added through the shift register 10, data that acts so as to become high frequency attenuated data is generated.
【0011】このデータについて図3(a)に示す。今、
入力のデータ(i)のようにステップ状に変化した場合、
引算器3より変化点でデータ(ii)の差分出力Pが得られ
る。これらは次のサンプルまで保持されるが図示しやす
いよう点で示す。このPのデータがシフトレジスター7
により順次送られ各レジスターを通過する毎にROM8
によりデータを生成するが、ここではa,b,c,dの
4段のレジスターで説明する。FIG. 3A shows this data. now,
When the input data (i) changes stepwise,
The difference output P of the data (ii) is obtained from the subtracter 3 at the change point. These are retained until the next sample, but are indicated by dots for ease of illustration. This P data is stored in the shift register 7
ROM8 each time it passes through each register
The data is generated by the following, but here, the description will be given with the four-stage registers a, b, c, and d.
【0012】例えばPのデータがシフトレジスター7−
aに入るとROM8−aより(iii)の8aの出力データ
を発し、順次シフトレジスター7−dまでにROM8−
aより8dのデータまで出力する。この出力データは加
算器9を通ってもPのデータは一ケ所のため(iii) のま
まのデータとなるこのデータ列と入力データを遅らせた
データ(i)’と加算すると(iv)の実線のようにステップ
状の波形をゆるやかな変化、すなわち高域レベルが低下
した波形となるようになる。For example, if the data of P is stored in the shift register 7-
a, the output data of (iii) 8a is issued from the ROM 8-a, and the ROM 8-a is sequentially output to the shift register 7-d.
Outputs data from a to 8d. Even if this output data passes through the adder 9, since there is only one P data, this data string that remains as (iii) and the input data with delayed data (i) 'are added, the solid line of (iv). As described above, the step-like waveform becomes a gentle change, that is, a waveform in which the high frequency level is lowered.
【0013】逆に目的の高域を落としたゆるやかな変化
のデータより入力のステップ状データを差し引いたデー
タを発生するようにROM8に入れておくことで満足す
る。(このデータは入力のデータのLSBより下位のビ
ットまで生成するようにする。)ここでPの値が2倍に
なればROM8の出力のデータも2倍に対応したデータ
を入れておき、Pの値に対応するだけのデータとしてお
く。ここでレジスター7、ROM8は4段で説明した
が、2段のみでも良くもちろん多くても良い。On the contrary, it is sufficient to store the data in the ROM 8 so as to generate the data in which the input step data is subtracted from the data of the gradual change in which the target high range is dropped. (This data is generated up to the bits lower than the LSB of the input data.) Here, if the value of P is doubled, the data of the output of the ROM 8 is also doubled, and P Data corresponding to the value of. Here, the register 7 and the ROM 8 have been described in four stages, but may be only two stages or may be many.
【0014】図3(b)のように変化が続く場合を示す
が、各変化点に対応した差分データP1〜P3が順次レジ
スター7に入り、各レジスターに対応したROM8より
のデータが同一サンプル時間に複数発生する。例えば図
のROM8OUTのようにP1のデータがdの時、P1に対
しP1d,P2はCにありP2C,P3はbにありP3bの
ようにROM8より各々出力され、加算データは加算器
9より得られ、この時(iii)はxのようにこれらの加算
データを得る。The case where the change continues as shown in FIG. 3B is shown. The difference data P1 to P3 corresponding to each change point are sequentially entered into the register 7, and the data from the ROM 8 corresponding to each register have the same sample time. Occurs more than once. For example, when the data of P1 is d like ROM8OUT in the figure, P1d and P2 are in C with respect to P1, P2C and P3 are in b, and each is output from ROM8 like P3b, and the addition data is obtained from the adder 9. At this time, (iii) obtains these addition data like x.
【0015】このように順次加算されたデータ(iii) は
入力のタイミングを合わされたデータ(i)’とを加算す
ると(iv)のように出力され変化がある点もなめらかな
ノイズの無いデータとなる。図4(b)のP1,P2を2L
SB,P3 を3LSBステップとすれば(ROM8の出
力がLSB以下まで出力されているため)、(iv)の出力
ではLSB以下のレベルにわたりなめらかになっている
ことがわかる。次にノイズシェーピング等の領域を判別
するパターン検出器4について説明する。このブロック
図の例を図2に示す。引算器3の出力をディザー等の最
高レベルに設定したリファレンスデータ(4−1)とコン
パレータ(4−3)と比較し、リファレンスレベル以下の
レベル変化を出力する。The data (iii) sequentially added in this manner is obtained by adding the data (i) ′ whose input timing has been adjusted, to output data (iv) as shown in (iv). Become. P1 and P2 in FIG.
If SB and P3 are set to 3 LSB steps (because the output of the ROM 8 is output up to the LSB), it can be seen that the output of (iv) is smooth over the LSB level. Next, the pattern detector 4 for discriminating an area such as noise shaping will be described. FIG. 2 shows an example of this block diagram. The output of the subtractor 3 is compared with the reference data (4-1) set to the highest level such as dither and the comparator (4-3), and the level change below the reference level is output.
【0016】一般には数LSBから十数LSBのノイズ
もあるが±8LSB程度以下で良い。又、差のデータは
2LSB以上の正,負の変化をレベルに関係なく変化デ
ータとし出力し、さらにLSBの変化をレジスター4−
2で別々に受け出力する。この2LSB以上の変化出力
をゲート4−4,4−5でゲートし各出力をシフトレジ
スター4−6に入れる。シフトレジスター4−6より各
レジスター段の正負の出力を互い違いにアンドゲート4
−7及びその逆の互い違いを検出するゲート4−8に入
れ、これらをオア回路4−9を経て信号を得る。Generally, there is a noise of several LSB to several tens LSB, but it may be about ± 8 LSB or less. As for the difference data, positive and negative changes of 2 LSB or more are output as change data irrespective of the level.
2 to receive and output separately. The change outputs of 2 LSB or more are gated by the gates 4-4 and 4-5 and the respective outputs are put in the shift register 4-6. The AND gate 4 alternates the positive and negative outputs of each register stage from the shift register 4-6.
-7 and vice versa are input to a gate 4-8 for detecting the alternation, and these are passed through an OR circuit 4-9 to obtain a signal.
【0017】ここでの出力は、サンプル間の変化がリフ
ァレンスの設定レベル以下であり、サンプル間で変化が
逆な部分を抽出している。この検出があればノイズシェ
ーピングを行った図4(a)のような波形領域をとらえる
ことができる。このアンドゲートの数は実施例では5サ
ンプル間を示したがもちろん前後しても良い。この波形
をとらえると、カウンター4−10をセットし検出出力
がなくなってもノイズシェーピングによるノイズの多い
領域の可能性が多く、データ変化のない所などや同一極
性変化点であり、しばらく保持する。カウンターはクロ
ックで作動し、所定サンプルあらためて4−9の出力が
あればセットしなおしさらに続く。このカウンターのカ
ウント数は数サンプルより数10サンプルなど比較的広
範囲で良い。オア回路4−9の出力がとだえカウンター
が成立すると、カウンター4−10の出力は無くなるよ
うにLレベルとなしゲート出力6はなくなり、ノイズ除
去動作を止める。In the output, a portion where the change between samples is equal to or less than the reference set level and where the change between samples is reversed is extracted. With this detection, it is possible to capture a waveform region as shown in FIG. 4A in which noise shaping has been performed. In the embodiment, the number of AND gates is set to 5 samples, but of course it may be changed. When this waveform is captured, even if the counter 4-10 is set and there is no detected output, there is a high possibility of a noisy region due to noise shaping, where there is no data change or at the same polarity change point, and it is held for a while. The counter is clocked and resets if there are 4-9 outputs for a given sample again, and so on. The number of counts of this counter may be in a relatively wide range such as several tens of samples rather than several samples. When the output of the OR circuit 4-9 is satisfied and the counter is established, the output of the counter 4-10 becomes L level and the gate output 6 disappears, and the noise removing operation is stopped.
【0018】一方±1LSB変化点は、図4(b)のよう
な±1/2LSBのディザーを行ったものなどで相互に
極性の異なった変化の数が少ない場合が多い。このため
4−2より独立に分離しシフトレジスター4−11を別
に設け、互いに隣合ったデータのみをゲート4−12,
13で検出する。これをオア回路4−9に入力しても良
いが、ここではカウンター出力4−10とオアを取り検
出出力としている。又カウンター4−10が保持され出
力がLとなる前に入力が大きく変化した場合、すなわち
設定レベル変化を越えた場合、立上りのなまりを防止す
るためタイミング合わせのレジスター4−15を経てカ
ウンター4−10をリセットする。On the other hand, the ± 1 LSB change point is often the case where the dither of ± 1/2 LSB as shown in FIG. 4B is performed and the number of changes having mutually different polarities is small. For this reason, a shift register 4-11 is separately provided separately from 4-2, and only data adjacent to each other is gated 4-12,
Detect at 13. Although this may be input to the OR circuit 4-9, the OR output is taken as the counter output 4-10 here as a detection output. If the input changes significantly before the output is set to L and the counter 4-10 is held, that is, if the set level change is exceeded, the counter 4-through the timing adjustment register 4-15 to prevent the rising of the counter. Reset 10.
【0019】このため検出出力を止める。図5に他の検
出例を示す。4−6のシフトレジスターの段数を増や
し、アンドゲート4−7,4−8をさらに増大させ、1
0サンプル以上を検出する。すなわちノイズシェーピン
グによるノイズはサンプル周波数fs 毎に変化が反転す
る確率が非常に高い。一方信号の高域信号はサンプル周
波数の1/2以下であり、さらにAD,DAのローパス
フィルタのため一般には1/2.2 程度の高域周波数以
下である。このために11サンプルや12サンプルなど
で必ず同一極性の変化点が表れる。Therefore, the detection output is stopped. FIG. 5 shows another detection example. The number of stages of the shift register 4-6 is increased, and the AND gates 4-7 and 4-8 are further increased, and 1
0 or more samples are detected. That is, the noise due to noise shaping has a very high probability that the change is inverted at each sampling frequency fs. On the other hand, the high frequency signal of the signal is less than 1/2 of the sampling frequency, and is generally less than the high frequency of about 1 / 2.2 due to the low pass filter of AD and DA. For this reason, the same polarity change points always appear in 11 samples and 12 samples.
【0020】このため、アンド回路4−7’,4−8’
をこの値以上に設定すると、ディザー等の入らない高域
データの場合は検出しない。一方微少レベルのノイズシ
ェーピングデータが約10サンプル以上の交互データが
必ず続くとは限らず、少ないことや変化のないこともあ
る。このため一度検出したら少ない反転でも検出とする
よう、カウンターの出力よりゲート4−16を設け、少
ないアンドゲート4−17を設け、これらが成立すると
パターン検出を成立とする。Therefore, AND circuits 4-7 'and 4-8'.
If is set to more than this value, high frequency data without dither etc. will not be detected. On the other hand, the minute level noise shaping data is not always followed by alternate data of about 10 samples or more, and may be small or unchanged. Therefore, the gate 4-16 is provided and the AND gates 4-17 are provided less than the output of the counter so that even a small inversion can be detected once detected, and if these are established, the pattern detection is established.
【0021】パターン検出成立は図2又は図5のような
アンド条件が成立した時のため検出が引算器3の出力よ
り遅れる。この分だけ差分データを遅らせゲート6に入
れるようレジスター5の段数を設定する。ここで検出条
件より先にノイズ領域として検出されない時が想定され
る場合にはレジスター5をさらに段数を増やし、検出よ
り少なく前より微少レベル領域ではフィルター効果を与
えることもできる。Since the detection of the pattern is established when the AND condition as shown in FIG. 2 or FIG. 5 is established, the detection is delayed from the output of the subtracter 3. The number of stages of the register 5 is set so that the difference data is delayed by this amount and is input to the gate 6. If it is assumed that a noise region is not detected earlier than the detection condition, the number of stages of the register 5 may be further increased, and a filter effect may be applied in a finer level region that is less than the detection level.
【0022】以上説明のように微少レベル領域でノイズ
シェーピング等の高域ノイズがあるディジタル信号を確
実にノイズを減少でき、ノイズシェーピングの効果は保
たれLSB以下まで再生できる。一般のレベルやノイズ
の無い一般データでは高域の減衰の無い再生が可能とな
る。これらの構成はロジック回路以外にDSPによるプ
ログラムによっても達成でき、又、生成データのROM
もレベルに対応して設定し、レベルにより乗算するなど
でも良い。As described above, it is possible to reliably reduce the noise of a digital signal having high-frequency noise such as noise shaping in the minute level region, the effect of noise shaping is maintained, and the signal can be reproduced up to LSB or lower. It is possible to perform reproduction without attenuation in the high range with general data having no general level or noise. These configurations can be achieved not only by the logic circuit but also by the program by the DSP, and the generated data ROM
May be set corresponding to the level and multiplied by the level.
【0023】[0023]
【発明の効果】本発明によると、高域ノイズを減少させ
ると共にLSB以下まで再生することができ、一般デー
タでは高域の減衰の無い再生ができる。According to the present invention, high frequency noise can be reduced and reproduction up to LSB or lower can be performed, and general data can be reproduced without high frequency attenuation.
【図1】本発明の一実施例のブロック図。FIG. 1 is a block diagram of one embodiment of the present invention.
【図2】パターン検出回路の一実施例の図。FIG. 2 is a diagram of an embodiment of a pattern detection circuit.
【図3】波形を示す図。FIG. 3 is a diagram showing a waveform.
【図4】ノイズを説明するための図。FIG. 4 is a diagram for explaining noise.
【図5】パターン検出回路の他の実施例の図。FIG. 5 is a diagram of another embodiment of the pattern detection circuit.
1,2,7,10
シフトレジスター 3
引算器 4
検出器 5
レジスター 6
ゲート 8
ROM 9
加算器 4−1
リファレンスデータ 4−2,4−15
レジスター 4−3
コンパレータ 4−4,4−5,4−8,4−12,4−13,4−16
ゲート 4−6,4−11
シフトレジスター 4−7,4−17
アンドゲート 4−9
オア回路 4−10
カウンター1, 2, 7, 10
Shift register 3
Subtractor 4
Detector 5
Register 6
Gate 8
ROM 9
Adder 4-1
Reference data 4-2, 4-15
Register 4-3
Comparators 4-4, 4-5, 4-8, 4-12, 4-13, 4-16
Gate 4-6, 4-11
Shift register 4-7, 4-17
AND GATE 4-9
OR circuit 4-10
counter
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H03M 1/66 H03M 1/66 A 3/00 9382−5K 3/00 (56)参考文献 特開 平6−6217(JP,A) 特開 平4−354208(JP,A) 特開 平5−304474(JP,A) 特開 昭56−131239(JP,A) 特開 平2−124622(JP,A) 特許2507285(JP,B2)─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Office reference number FI technical display location H03M 1/66 H03M 1/66 A 3/00 9382-5K 3/00 (56) References JP-A-6-6217 (JP, A) JP-A-4-354208 (JP, A) JP-A-5-304474 (JP, A) JP-A-56-131239 (JP, A) JP-A-2-124622 (JP , A) Patent 2507285 (JP, B2)
Claims (4)
ータのレベル差を検出し、所定レベル以下のレベル変化
の極性が所定回数以上の反転を検出する検出手段を有
し、該検出出力によって高域レベルを減衰し、入力最少
ビット以下まで拡大しDA変換するようにしたことを特
徴とするDA変換装置。1. A DA converter, comprising detection means for detecting a level difference of data for each sample and detecting inversion in which a polarity of level change of a predetermined level or less is detected a predetermined number of times or more, and a high range is detected by the detection output. A DA converter characterized in that the level is attenuated, enlarged to the input minimum bit or less, and D / A conversion is performed.
としたことを特徴とする請求項1記載のDA変換装置。2. The DA converter according to claim 1, wherein the number of inversions of the detection means is set to about 10 samples or more.
衰のためのデータ生成手段を有し、サンプルデータと加
算するようになした請求項1記載のDA変換装置。3. The DA converter according to claim 1, further comprising data generating means for high-frequency attenuation corresponding to a level difference between samples, and adding the sample data.
によって作動する検出手段を有する請求項2記載のDA
変換装置。4. The DA according to claim 2, further comprising detection means that operates by detecting a smaller number of reversals after obtaining the detection output.
Conversion device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP34739293A JP2668854B2 (en) | 1993-12-25 | 1993-12-25 | DA converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP34739293A JP2668854B2 (en) | 1993-12-25 | 1993-12-25 | DA converter |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH07193501A JPH07193501A (en) | 1995-07-28 |
JP2668854B2 true JP2668854B2 (en) | 1997-10-27 |
Family
ID=18389920
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP34739293A Expired - Lifetime JP2668854B2 (en) | 1993-12-25 | 1993-12-25 | DA converter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2668854B2 (en) |
-
1993
- 1993-12-25 JP JP34739293A patent/JP2668854B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH07193501A (en) | 1995-07-28 |
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