JP2668854B2 - DA converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of digital-analog conversion of a CD player or the like.

[0002]

2. Description of the Related Art When an analog signal from a CD player or the like is converted into a digital signal and returned to an analog signal, only a predetermined number of bits can be handled at the stage of the digital signal. The CD system has 16 bits, but a signal smaller than this is rounded. Therefore, at the stage of converting an analog signal to a digital signal, a dither that adds high frequency noise to the analog signal is used, or recently, an AD conversion of 20 bits or more, which is larger than a predetermined number of bits, is used to convert the digital signal to 20 bits. 16 depending on the noise shaping method
By reducing the error to bits and feeding back the error, the error in the normal frequency region in the middle and low frequencies is reduced.

[0003]

In the case of digitized data by these, 1/2 of the sampling frequency fs is used.
There was a drawback that the noise increased near the frequency of. Therefore, it is an object of the present invention to reduce these high-frequency noises and prevent the high-frequency components of normal music from being affected, and to reproduce with high precision up to the level of the least significant bit (LSB) of transmission bits. .

[0004]

According to the present invention, it is detected that the data of each sample changes alternately with the previous sample value, and when the change is less than a predetermined level, the high frequency signal is attenuated and less than the minimum number of bits. Data is generated, the number of bits is expanded from the input data, and DA conversion is performed.

[0005]

As a result, it is possible to reproduce an analog signal with reduced high-frequency noise and less distortion, and to reproduce a general reproduced signal without high-frequency attenuation, thereby improving reproduction quality.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A block diagram of an embodiment of the present invention will be described with reference to FIG. A sample data sequence having a predetermined number of bits n is input, and data is sequentially shifted to the shift registers 1 and 2 by a clock CK having a sample frequency fs.

As a result, the output of the shift register 2 and 1
Is output as data shifted by one sample, and the data of both outputs is subtracted by the subtractor 3 to output data corresponding to the difference. The output of this difference is used by the pattern detector 4 to discriminate a signal in a small signal level region in which high-frequency noise such as noise shaping is large, and the difference data in that case is passed through the gate 6 so that normal level signal data or the like in which no pattern is detected is detected. Do not pass.

Here, the output of the subtracter 3 is provided with a register 5 having a required number of stages for adjusting the timing of the gate 6 for compensating for the delay in pattern detection. The difference data in which the high-frequency noise is detected in the minute area is put into the shift register 7 and sequentially shifted, and the data is obtained from the register of each stage via the data generating section corresponding to the data value.

Here, the data generating section comprises a ROM 8,
This can be easily obtained by previously storing data calculated in the ROM 8 as the data in the ROM 8 corresponding to the data in the shift register 7, and using the data value as an address to read the data. The respective data from the ROM 8 obtained correspondingly from the respective registers 7 are added by the adder 9, further added to the input n-bit data, expanded to the data up to n bits or less, output and DA-converted. Adder 9 here
The output of becomes a data opposite to the noise of the input data, and acts to cancel the noise by adding.

The shift register 1 is used to make the delay time from the input to the adder 9 exactly equal to the time of the input data.
0 is provided. Here, regarding the data of the ROM 8, when the output data of the adder 9 and the input data are added through the shift register 10, data that acts so as to become high frequency attenuated data is generated.

FIG. 3A shows this data. now,
When the input data (i) changes stepwise,
The difference output P of the data (ii) is obtained from the subtracter 3 at the change point. These are retained until the next sample, but are indicated by dots for ease of illustration. This P data is stored in the shift register 7
ROM8 each time it passes through each register
The data is generated by the following, but here, the description will be given with the four-stage registers a, b, c, and d.

For example, if the data of P is stored in the shift register 7-
a, the output data of (iii) 8a is issued from the ROM 8-a, and the ROM 8-a is sequentially output to the shift register 7-d.
Outputs data from a to 8d. Even if this output data passes through the adder 9, since there is only one P data, this data string that remains as (iii) and the input data with delayed data (i) 'are added, the solid line of (iv). As described above, the step-like waveform becomes a gentle change, that is, a waveform in which the high frequency level is lowered.

On the contrary, it is sufficient to store the data in the ROM 8 so as to generate the data in which the input step data is subtracted from the data of the gradual change in which the target high range is dropped. (This data is generated up to the bits lower than the LSB of the input data.) Here, if the value of P is doubled, the data of the output of the ROM 8 is also doubled, and P Data corresponding to the value of. Here, the register 7 and the ROM 8 have been described in four stages, but may be only two stages or may be many.

The case where the change continues as shown in FIG. 3B is shown. The difference data P1 to P3 corresponding to each change point are sequentially entered into the register 7, and the data from the ROM 8 corresponding to each register have the same sample time. Occurs more than once. For example, when the data of P1 is d like ROM8OUT in the figure, P1d and P2 are in C with respect to P1, P2C and P3 are in b, and each is output from ROM8 like P3b, and the addition data is obtained from the adder 9. At this time, (iii) obtains these addition data like x.

The data (iii) sequentially added in this manner is obtained by adding the data (i) ′ whose input timing has been adjusted, to output data (iv) as shown in (iv). Become. P1 and P2 in FIG.
If SB and P3 are set to 3 LSB steps (because the output of the ROM 8 is output up to the LSB), it can be seen that the output of (iv) is smooth over the LSB level. Next, the pattern detector 4 for discriminating an area such as noise shaping will be described. FIG. 2 shows an example of this block diagram. The output of the subtractor 3 is compared with the reference data (4-1) set to the highest level such as dither and the comparator (4-3), and the level change below the reference level is output.

Generally, there is a noise of several LSB to several tens LSB, but it may be about ± 8 LSB or less. As for the difference data, positive and negative changes of 2 LSB or more are output as change data irrespective of the level.
2 to receive and output separately. The change outputs of 2 LSB or more are gated by the gates 4-4 and 4-5 and the respective outputs are put in the shift register 4-6. The AND gate 4 alternates the positive and negative outputs of each register stage from the shift register 4-6.
-7 and vice versa are input to a gate 4-8 for detecting the alternation, and these are passed through an OR circuit 4-9 to obtain a signal.

In the output, a portion where the change between samples is equal to or less than the reference set level and where the change between samples is reversed is extracted. With this detection, it is possible to capture a waveform region as shown in FIG. 4A in which noise shaping has been performed. In the embodiment, the number of AND gates is set to 5 samples, but of course it may be changed. When this waveform is captured, even if the counter 4-10 is set and there is no detected output, there is a high possibility of a noisy region due to noise shaping, where there is no data change or at the same polarity change point, and it is held for a while. The counter is clocked and resets if there are 4-9 outputs for a given sample again, and so on. The number of counts of this counter may be in a relatively wide range such as several tens of samples rather than several samples. When the output of the OR circuit 4-9 is satisfied and the counter is established, the output of the counter 4-10 becomes L level and the gate output 6 disappears, and the noise removing operation is stopped.

On the other hand, the ± 1 LSB change point is often the case where the dither of ± 1/2 LSB as shown in FIG. 4B is performed and the number of changes having mutually different polarities is small. For this reason, a shift register 4-11 is separately provided separately from 4-2, and only data adjacent to each other is gated 4-12,
Detect at 13. Although this may be input to the OR circuit 4-9, the OR output is taken as the counter output 4-10 here as a detection output. If the input changes significantly before the output is set to L and the counter 4-10 is held, that is, if the set level change is exceeded, the counter 4-through the timing adjustment register 4-15 to prevent the rising of the counter. Reset 10.

Therefore, the detection output is stopped. FIG. 5 shows another detection example. The number of stages of the shift register 4-6 is increased, and the AND gates 4-7 and 4-8 are further increased, and 1
0 or more samples are detected. That is, the noise due to noise shaping has a very high probability that the change is inverted at each sampling frequency fs. On the other hand, the high frequency signal of the signal is less than 1/2 of the sampling frequency, and is generally less than the high frequency of about 1 / 2.2 due to the low pass filter of AD and DA. For this reason, the same polarity change points always appear in 11 samples and 12 samples.

Therefore, AND circuits 4-7 'and 4-8'.
If is set to more than this value, high frequency data without dither etc. will not be detected. On the other hand, the minute level noise shaping data is not always followed by alternate data of about 10 samples or more, and may be small or unchanged. Therefore, the gate 4-16 is provided and the AND gates 4-17 are provided less than the output of the counter so that even a small inversion can be detected once detected, and if these are established, the pattern detection is established.

Since the detection of the pattern is established when the AND condition as shown in FIG. 2 or FIG. 5 is established, the detection is delayed from the output of the subtracter 3. The number of stages of the register 5 is set so that the difference data is delayed by this amount and is input to the gate 6. If it is assumed that a noise region is not detected earlier than the detection condition, the number of stages of the register 5 may be further increased, and a filter effect may be applied in a finer level region that is less than the detection level.

As described above, it is possible to reliably reduce the noise of a digital signal having high-frequency noise such as noise shaping in the minute level region, the effect of noise shaping is maintained, and the signal can be reproduced up to LSB or lower. It is possible to perform reproduction without attenuation in the high range with general data having no general level or noise. These configurations can be achieved not only by the logic circuit but also by the program by the DSP, and the generated data ROM
May be set corresponding to the level and multiplied by the level.

[0023]

According to the present invention, high frequency noise can be reduced and reproduction up to LSB or lower can be performed, and general data can be reproduced without high frequency attenuation.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a diagram of an embodiment of a pattern detection circuit.

FIG. 3 is a diagram showing a waveform.

FIG. 4 is a diagram for explaining noise.

FIG. 5 is a diagram of another embodiment of the pattern detection circuit.

[Explanation of symbols]

1, 2, 7, 10
Shift register 3
Subtractor 4
Detector 5
Register 6
Gate 8
ROM 9
Adder 4-1
Reference data 4-2, 4-15
Register 4-3
Comparators 4-4, 4-5, 4-8, 4-12, 4-13, 4-16
Gate 4-6, 4-11
Shift register 4-7, 4-17
AND GATE 4-9
OR circuit 4-10
counter

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H03M 1/66 H03M 1/66 A 3/00 9382-5K 3/00 (56) References JP-A-6-6217 (JP, A) JP-A-4-354208 (JP, A) JP-A-5-304474 (JP, A) JP-A-56-131239 (JP, A) JP-A-2-124622 (JP , A) Patent 2507285 (JP, B2)

Claims (4)

(57) [Claims] 1. A DA converter, comprising detection means for detecting a level difference of data for each sample and detecting inversion in which a polarity of level change of a predetermined level or less is detected a predetermined number of times or more, and a high range is detected by the detection output. A DA converter characterized in that the level is attenuated, enlarged to the input minimum bit or less, and D / A conversion is performed. 2. The DA converter according to claim 1, wherein the number of inversions of the detection means is set to about 10 samples or more. 3. The DA converter according to claim 1, further comprising data generating means for high-frequency attenuation corresponding to a level difference between samples, and adding the sample data. 4. The DA according to claim 2, further comprising detection means that operates by detecting a smaller number of reversals after obtaining the detection output.
Conversion device.