JPH066217A - Bit length expanding device - Google Patents

Abstract

PURPOSE:To improve distortions and noises which are generated in the case of a minute level reproduction. CONSTITUTION:As for the sample data of a prescribed bit, the data differences such as 'least bit change', 'no change', 'large amplitude change' are extracted through a data change detecting part 1. Then the sample data are inputted to a shift register 2. The minute level change is extracted out of the register 2 and the changing rate of the minute level of the sample data is extracted by a pattern extracting part 3. When the changing rate is large, the data corresponding to a small changing rate are inputted to a shift register 4. Based on these data, the data of a bit less than LSB are generated by a data generating circuit 5 and matched with the timing of the input data by a shift register 6. Then the more and less significant data are added together by an adder 7. The bit is extended for all these added data so that the smooth change is secured for the original data. Thus a smooth analog output free from distortions can be acquired.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of reproduction distortion S / N particularly when used for digital-to-analog conversion of digital audio and the like at a minute level.

[0002]

2. Description of the Related Art Conventionally, an apparatus for transmitting or recording / reproducing an analog signal as a digital signal through an AD converter and reproducing the analog signal by a DA converter has a limited bit length at the digital stage. Since one sample data is used, there is a drawback that it is accompanied by quantization distortion corresponding to the bit length, and that noise is increased in the case where dither or the like is used to improve this distortion.

[0003]

Particularly, in the reproduction of a minute level, the distortion increases as it approaches the least significant bit (LSB), so that even a sine wave signal approaches a staircase wave or a rectangular wave and the distortion increases, and a minute analog noise is generated. However, it becomes LSB-level noise, which increases the noise.

[0004]

Therefore, the present invention provides an apparatus capable of reducing these minute levels of quantization distortion and noise, increasing the bit length, and performing DA conversion. Therefore, by extracting the difference between each sample data of the reproduced digital signal, 1LSB of this difference data is extracted.
An interval of increase (+ change) or decrease (-change) of change is detected, information corresponding to the change rate of 1LSB change at a minute level is generated, and lower bits are generated so that a smooth change occurs between 1LSB changes. Increase the number of bits, D / A
Realizes smooth playback without distortion by converting.

[0005]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A block diagram will be described below. A block diagram showing the whole is shown in FIG. Data Din for each sample, which is a word consisting of reproduced finite length bits
Is a small level of data (LS
B)) is detected. The data change detection unit 1 is shown in FIG.
An example will be shown. The waveform diagram is shown in FIG. A shift register 1-1 for shifting every sample clock fS is provided, and data from one sample is compared by this with a comparator 1-2, which is the same data between these one samples, no change 0, +1 LSB change, -1 LSB. Of the change of +, and the change of + H, -H, and the like of the change more than that are extracted.

Next, the ORs 1-3 of +1 and + H and the ORs of -1 and -H are taken by 1-4, and they are delayed by one clock by the shift register 1-5, and input to the set / reset flip-flop FF1-6. + 1LS from the output Q, Q
By taking the AND of B and -1LSB at 1-7 and 1-8, 1LS is added to + LSB and -LSB as shown in FIG.
The repeats of the data in B can be removed and only one sample can be output only when the next 1LSB increases or decreases. By this + LSB or -LSB, if the data of the minute level is changing slowly, the interval is long and the frequency is high, and if the level is large, the interval is narrow.
As shown in, it is possible to reliably extract the rate of change of data even for digital data containing minute noise.

FIG. 4 shows a block diagram for extracting the rate of change from the data flow of + LSB and -LSB.
The output data D from the data change detector 1 is input to the shift register 2 and shifted at the clock fs. The shift register length needs to be at least twice the target interval of the + LSB or -LSB pulse interval, and the register 2-n for the interval sample required before and after the center register 2-0 is the center.
Place ~ 0 ~ + n.

The pattern extracting section 3 selectively outputs a plurality of outputs corresponding to the rate of change of data. In this embodiment,
Two types of examples are shown: an interval F1 of ± 3 samples or more and an interval F2 of ± 6 samples or more. From shift register 2-0,
By the OR circuit 3-4, ± 1 ± H is taken out and used as a latch clock, and when there is data of this change,
If + LSB and + LSB, -LSB and -LSB are set in the D flip-flop DFF3-9 or 3-10 over the target interval, they are established and latched.

At the center 2-0 of the shift register 2, -LSB
If there is -LSB from shift register 2-(-2) to 2-2, gate 3-6 is established via OR gate 3-5 and is not latched by DFF 3-9 via gate 3-3. Similarly, + LSB is also gate 3 through gates 3-7 and 3-8
-3 is not latched as well. Also, even if there is ± H between these registers, it is not regarded as a minute level change area, and all ORs of ± H in this range are obtained by the gate 3-2, and DF
F3-9 does not hold. DFF3-9 is established when the LSB changed interval of the same polarity is 3 samples or more.

Similarly, + LS from 2-(-5) to 2-5
When the number of B and -LSB having the same polarity is not 2-0 in the center, the number of samples is 6 or more, and the number of DF of 3 or more is DF.
As with F3-9, DFF3-10 latches and detects. When this detection output appears, the DFF 3-9 also appears. In this case, since the DFF 3-10 has priority, the DFF 3-9 passes through the inverter 3-13 and the gate 3-12 causes the DFF 3-9.
Output only 3-10.

When a + 1LSB or -1LSB change signal comes in a section where DFF3-9 or 3-10 is established, AND gates 3-14 to 3-17 change rate of 3 samples or more per 1LSB change (1 sample As the F1 signal in the output area of 1/3 LSB per change, the rate of change of 6 samples or more (1
Outputs as positive and negative polarity outputs as an output region F2 of 1/6 LSB per sample).

Next, FIG. 5 shows the shift register 4 and the data generator 5. From ± F1 ± F2 of the pattern detector output,
By the OR circuit 4-6, the OR of + F1, -F1, that is, ±
It is divided into F1 (± 1LSB change data corresponding to the filter characteristic of F1) and polarity (1 for positive and 0 for negative), and ± F
Input to register 4 as 2 types of data, total of 2 and polarity. Here, F1 and F2 do not occur at the same time.

As the data is shifted to each of the registers 4-(-5) to 4-5, the correction data corresponding to the 1LSB change point is the value of D1-1 to D1-2 in the case of F1. The positive and negative data of, and in the case of F2, D2-1 to D2-5
The positive / negative of the value of is output, and every time one sample is shifted, the entire represented data is added by the full adder 5-1 to obtain total correction data. This correction data is shown in FIG. When + F2 is input to 4, the output appears at 4-(-5) and D25 of FIG. 6 appears at the data generation circuit D2-5.

As shown in the figure, this data generator can generate the required number of data by wiring only predetermined bits. Since F2 is positive, the sign bit is 1 as shown in FIG. 6, and D is up to register 4-(-1).
It gives a positive value of 25 to D21.

This data outputs D21 again when the register 4-1 generates 1 in F2, and after this time, the sign bit is output through the inverter until reaching the register 4-5 and becomes a negative 0. As shown in Df2 in FIG. 6, the value is decreased from a large negative value to a small value of D25 for each sample.

This data can be conveniently generated by using 1/4 cycle of the sine wave corresponding to the detection change rate and summing the positive and negative values and 1/2 cycle. At this time, the level of the data is ± LSB with a peak of 1 LSB. Similarly, in the case of F1 input, it corresponds to a filter with a high cut-off, data is generated with a fast rise, and a small number of samples are generated. Similarly, the positive values of D12-D11 increase and register 4-1 registers. When it comes, it reverses and becomes -D11 -D21, and becomes a data generation output.
All data generation between samples is added by the adder 5-1.
Since the data output here is the data indicating the polarity and the level, that is, the data of sine magnitude, it is converted into a general straight binary code by the code converter 5-2. The description of this conversion is well known and will be omitted.

As shown in FIG. 6, the data thus obtained determines the stage of the register 6 so that the change point of the high-order bit is at the timing when the F1 or F2 data appears in the shift register 4-1. The lower data to be corrected is added by the adder 7. Here, if the lower generation data is limited to 1 LSB or less, it may be simply added to the LSB or less.

FIG. 7 shows an actually obtained data generation circuit 5
2 and an example of the output waveform of the total output adder 7. When the upper bit data which is the input data Din is 7-3, +1 or -1LS obtained from each 1LSB change part
Compensation data is generated from B information, and 7-1 from each change part.
As shown in, each correction data is obtained and added by full addition 5-1 to obtain a data generation output like the solid line 7-2, and by adding it to the upper bit data 7-3, the total data 7 It is possible to obtain the target extended data having the information of 1 LSB or less smoothly as shown in -4.

Here, in the embodiment, the data change interval has been described as two kinds of F1 and F2, but the discrimination can be increased, the wide band range can be optimally smoothed, and even one can be simplified. good. Further, it is preferable to always provide the filter characteristic of about ± 1 sample at the ± 1LSB change point without detecting the one for the shortest interval. (FIG. 6, fH) With these, noise such as dither in the 1LSB range can be removed, and a staircase reproduction signal can be reproduced as a smooth analog signal, and distortion can be significantly improved, and the effect is great. . In this description, the minute level is 1LS.
Although described in B, it is of course possible to detect data such as 2LSB and generate data similarly.

[0020]

As described above, according to the present invention, it is possible to detect a change in LSB, extend the bit length, smoothly shape an output signal, and improve distortion and noise.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a data change detection unit 1.

FIG. 3 is a diagram for explaining a waveform.

FIG. 4 is a block diagram showing a shift register 2 and a pattern extraction unit 3.

FIG. 5 is a block diagram showing a shift register 4.

FIG. 6 is a diagram illustrating a data generation waveform.

FIG. 7 is a diagram illustrating an output waveform.

[Explanation of symbols]

 1 Data Change Detection Unit 2, 4, 6 Shift Register 3 Pattern Extraction Unit 5 Data Generation Circuit 7 Adder

Claims (2)

[Claims] 1. An apparatus for DA converting sample data having a predetermined word bit length, the data change detecting means corresponding to a rate of change of the level of the sample data,
A bit length expansion device comprising a means for generating data of LSB or less over one or more samples of a minute level change of a data string, and performing a smooth level change before and after the minute level change. 2. The bit length extension device according to claim 1, further comprising a data change detection unit that removes repetitiveness within a minute level.