JP2656024B2 - Modulation circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a modulation circuit for a digital signal recorded on a compact disk or the like.

2. Description of the Related Art Compact discs use EFM modulation that converts 8-bit data into 14-bit data. Also, part 14
Between the bit-converted data, three merging bits are inserted to suppress low frequency components. The output after the modulation is determined such that the number of 0s is 2 or more and 10 or less in the data before the NRZI modulation. Also, the merging bit is selected so as to satisfy the above-mentioned standard, not to have the same format as the frame synchronization signal, and to have a small digital sum value.

Conventionally, a flowchart has been proposed to determine this merging bit. (For example, see JP-A-59-5754.
No. 9) Problems to be Solved by the Invention However, if a microcomputer or the like is used to calculate the merging bits based on the above-mentioned flowchart, the processing speed is slow, and a computer is required, resulting in a large-scale device. Had problems.

Means for Solving the Problems A modulation circuit according to the present invention is provided with a data converter for inputting h-bit data, converting the h bits into d bits, and outputting a digital sum value and a polarity of the converted data. Circuit, and holds the previous conversion data and the previous merging bit. From these data and the current conversion data output from the data conversion circuit, a merging bit is stored before the current conversion data. A standard violation detection circuit that outputs a violation signal for multiple merging bits to determine whether it violates the modulation standard when inserted into the Digital sum value and polarity, the digital sum value of the current conversion data output from the data conversion circuit Liu,
Using the standard violation signal output from the standard violation detection circuit, calculate the digital sum value of the merging bit that does not violate the standard and has the smallest digital sum value after inserting the merging bit for each merging bit. A merging bit selection circuit that outputs the data by referring to a preset table, and outputs the merging bits output from the data conversion circuit by adding the merging bits before the current conversion data output from the data conversion circuit. The digital sum value and the polarity of the converted data output from the data conversion circuit and the merging bit output from the selection circuit, and before the insertion of the merging bit stored in the circuit. Digital sum value list up to It is obtained by a digital sum value calculating circuit for obtaining a new digital sum value and polarity with the polarity.

Further, the modulation circuit according to another invention receives h-bit data, converts the h-beat into d-bits,
A data conversion circuit for outputting a digital sum value and a polarity of the conversion data, a digital sum value and a polarity before insertion of a merging bit output from the digital sum value calculation circuit, and a current conversion output from the data conversion circuit Using the digital sum value of data, merging to output a merging bit with the smallest digital sum value by referring to a preset table without calculating a digital sum value after insertion of merging bits for each merging bit A bit selection circuit, a merging bit addition circuit that adds a merging bit output from the merging bit selection circuit before current conversion data output from the data conversion circuit, and outputs the result. Inputting the digital sum value and the polarity of the converted data to be converted, and using the merging bit output from the selection circuit and the digital sum value and the polarity stored in the circuit before the insertion of the merging bit, a new digital sum is used. And a digital sum value calculation circuit for obtaining a value and a polarity.

Operation In the present invention, the processing speed is greatly improved by the above-described configuration.

Embodiment A modulation circuit according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the modulation circuit of the present invention. 1 is a data conversion circuit, 11 is data input, 12
Is an output of converted data, 13 is a data output for detecting a violation of the standard, and 14 is an output indicating the digital sum value and polarity of the data. 2 is a merging bit addition circuit, and 3 is a standard violation detection circuit, which outputs 31 standard violation signals. A merging bit selection circuit 4 outputs the merging bit selected from 41. A digital sum value calculation circuit 5 outputs a digital sum value at 51 and a polarity at 52.

With respect to the modulation circuit configured as described above, the first
The operation will be described with reference to FIGS.

The h-bit data input from 11 is converted to d-bits by 1 and k-merging bits are added before it by 2 and output from 21. The output after modulation is 0
Must meet the standard of not less than m and not more than n, which is the number of leading zeros and the trailing zero of the data.
, It is possible to detect whether or not each of the selectable merging bits violates the standard. Whether or not a synchronization signal is formed by selecting the merging bit is determined by the number of leading zeros and the number of trailing zeros of the data, the immediately preceding data, the current data, and the immediately preceding data. If the merging bit is known, it can be detected. Therefore, when the data is converted by 1, the number of leading zeros and the number of trailing zeros of the data are simultaneously reduced by 13
Then, 13, 12, and 41 are input to 3 to detect whether each of the merging bits that can be selected violates the standard, and the presence or absence of the violation is output from 31.

FIG. 3 is a calculation example of the digital sum value. now,
Consider modulation of a signal on a compact disc. The standard states that
Since 0 must be continuous for 2 or more and 10 or less,
Possible three merging bits are "000", "0"
There are only four types, 01 "," 010 ", and" 100 ", and since NRZI modulation is adopted, the digital sum value changes according to the current polarity (High or Low). The digital sum value of the merging bit whose polarity is High and the digital sum value is 2 is as shown in the figure.
Then, it is assumed that it was 6. The merging bit is "00"
If a value other than "0" is selected, the data is inverted, so that the digital sum value of the data changes to -6. When the above three digital sum values are added, the result becomes as shown in the digital sum value after the addition. When the absolute value of the digital sum value is ranked in ascending order, the result is as shown in the figure: the digital sum value at the time of inserting the merging bit, the polarity and the digital sum value of the current data after the merging bit, Thus, the order of decreasing the absolute value of the next digital sum value can be uniquely determined, and the merging bit selection circuit 4 uses the above-described method to determine the digital sum value 5 at the time of inserting the merging bit.
The digital sum value 14 of the data after the 1, the polarity 52 and the merging bit, and the standard violation signal 31 are inputted, and the merging bit whose absolute value of the digital sum value is the smallest and does not violate the standard is output from 41. The digital sum value calculation circuit 5 inputs the selected merging bit and the digital sum value and polarity of the current data, and calculates a new digital sum value and polarity.

As described above, according to the present embodiment, selection of a merging bit can be realized with a simple circuit, and high-speed operation can be performed.

In the first embodiment, a standard violation detection circuit is provided,
A modulation standard violation was detected. However, depending on the modulation method, it is not necessary to detect violation of the standard. FIG. 2 shows a second embodiment, in which the merging bit selection circuit 4 is replaced by the digital sum value and polarity up to the merging bit, and the digital sum value of the converted data, except for the standard violation detection circuit shown in FIG. Among them, the merging bit that minimizes the absolute value of the digital sum value is selected by using all or a part of the merging bit.

Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 4 is a configuration diagram of a modulation circuit showing a third embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a data conversion circuit which is constituted by a ROM. Reference numeral 2 denotes a circuit for adding a merging bit, which is configured by a parallel-serial conversion circuit. Reference numeral 3 denotes a standard violation detection circuit which includes 32 PLAs and 33 and 34 registers. Numeral 4 denotes a merging bit selection circuit which is composed of a ROM. 5 is a digital sum value calculation circuit, 53,54 digital sum value and polarity registers, 55,56 full adders, 57,58 PL
Consists of A.

The input data is converted by the ROM 1, parallel-to-serial converted in 2 with the merging bit added before, and output from 21. In addition, in the ROM of 1, the number of leading zeros and the number of trailing zeros of the data, the digital sum value, and a flag indicating whether or not a signal is inverted when the data is output are coded. The standard violation detection circuit 2 inputs the number of leading zeros and the number of trailing zeros, the previous data latched in the registers 33 and 34, the previous merging bit, and the current data to the PLA 32. Then, it detects whether or not each merging bit violates the standard, and outputs the presence / absence of the violation to 31. The merging bit selection ROM 4 has a digital sum value 51, polarity at the time of inserting the merging bit.
52 and the digital sum value 14 of the data after the merging bit and the output 31 of the standard violation detecting circuit are input, and the merging bit whose digital sum value absolute value is the smallest and does not violate the standard is output from 41. The digital sum value calculation circuit 5 first obtains the digital sum value expressed by the two's complement of the merging bit from the polarity and the selected merging bit before the merging bit in the 57 PLA, Is obtained and output from 59. The PLA 58 corrects the digital sum value of the current data by the polarity 59 after the merging bit, and outputs a correct digital sum value in 2's complement format. The above two digital sum values and the previous digital sum value are added at 55,56 to form a new digital sum value. On the other hand, the polarity is
Obtain a digital sum value with 58 PLAs and obtain a new polarity from the current data polarity.

FIG. 5 is a configuration diagram of a modulation circuit showing a fourth embodiment of the present invention.

In the figure, 1, 2, 3, and 5 are exactly the same as in the second embodiment. The merging bit selection circuit of 4
ROM, 43 magnitude comparison circuits, and 44 decoders.

With respect to the modulation circuit configured as described above, only the merging bit selection circuit 4 will be described.

In the ROM 42, the digital sum value 51 at the time of inserting the merging bit, the polarity 52 and the digital sum value 14 of the data after the merging bit are input,
The order in which the absolute value of the digital sum value decreases for each merging bit is output. This is input to the magnitude comparison circuit 43 together with the output 31 of the violation detection circuit. In 43, the merging bits are compared in magnitude, but those that violate the standard are input as 1 in the MSB and are treated as large, so that the merging bit is not selected. Accordingly, the number of the merging bit that does not violate the standard and minimizes the absolute value of the digital sum value is output, and the number is converted to the actual merging bit by the 44 decoder.

By configuring the merging bit selection circuit as described above, it is possible to reduce the capacity of the ROM as compared with the case where the ROM is configured as a single ROM as in the second example. It can be smaller.

In the above embodiment, the absolute value of the digital sum value at point A in FIG. 3 is minimized.
The absolute value of the digital sum value at a point can be minimized. In this case, the merging bit selection circuit 4
By using only the digital sum value and the polarity before the merging bit, the merging bit selection ROM may be rewritten so as to select the merging bit that minimizes the digital sum value at point B.

As described above, the present invention provides a circuit for converting h-bit data to d-bits, a circuit for adding and outputting k-bit merging bits before the converted d-bit data, By inserting the merging bit,
A standard violation detection circuit that detects whether or not the modulation standard is violated and outputs the result for each merging bit;
A circuit for obtaining a new digital sum value and polarity from the digital sum value and polarity before the merging bit, the selected merging bit, the digital sum value and polarity of the converted data, and a digital sum value and polarity before the merging bit. By providing a circuit that selects the merging bit that does not violate the standard from the polarity and the digital sum value of the converted data and the output of the standard violation detection circuit and that has the smallest digital sum value, High-speed operation can be performed with a simple circuit configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram of a modulation circuit in a first embodiment of the present invention, FIG. 2 is a block diagram of a modulation circuit in a second embodiment of the present invention, and FIG. 3 is a block diagram of the first embodiment. Explanatory diagram,
FIG. 4 is a configuration diagram of a modulation circuit according to a third embodiment of the present invention, and FIG. 5 is a configuration diagram of a modulation circuit according to a fourth embodiment of the present invention. 1 Data conversion circuit, 2 Merging bit addition circuit, 3 Violation detection circuit, 4 Merging bit selection circuit, 5 Digital sum value calculation circuit.

Claims (2)

(57) [Claims] 1. A data conversion circuit which receives h-bit data, converts h-bits into d-bits, and outputs a digital sum value and a polarity of the conversion data, and the conversion data immediately before the conversion data When the merging bit is inserted before the current conversion data from these data and the current conversion data outputted from the data conversion circuit, the modulation standard is violated. A standard violation detection circuit that outputs a standard violation signal as a result of obtaining a plurality of merging bits, a digital sum value and polarity output from a digital sum value calculation circuit before insertion of the merging bit, and the data conversion circuit The digital sum value of the current conversion data output from the Using the standard violation signal,
A merging bit selection circuit that outputs the merging bit that does not violate the standard and has the smallest digital sum value by referring to a preset table without calculating the digital sum value after the merging bit is inserted for each merging bit And a merging bit addition circuit that adds and outputs a merging bit output from the merging bit selection circuit before the current conversion data output from the data conversion circuit, and a conversion data output from the data conversion circuit. The digital sum value and the polarity are input, and the new digital sum value and the polarity are obtained by using the merging bit output from the selection circuit and the digital sum value and the polarity before insertion of the merging bit stored in the circuit. Desi Modulation circuit characterized by comprising a Le sum value calculating circuit. 2. A data conversion circuit which receives h-bit data, converts the h-bits into d-bits, outputs a digital sum value and a polarity of the converted data, and outputs the data from a digital sum-value calculation circuit. Using the digital sum value and the polarity before the insertion of the merging bit, and the digital sum value of the current conversion data output from the data conversion circuit, the merging bit with the smallest digital sum value is calculated for each merging bit. A merging bit selection circuit that outputs by referring to a preset table without calculating the digital sum value after insertion of the merging bit, and a merging bit output by the merging bit selection circuit are output from the data conversion circuit. Current conversion data A merging bit adding circuit that adds and outputs the digital sum value and the polarity of the conversion data output from the data conversion circuit, and outputs the merging bit output from the selection circuit; A digital sum value calculation circuit for obtaining a new digital sum value and a new polarity using the digital sum value and the polarity before the insertion of the merging bit stored in the modulation circuit.