JPS6116110B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a digital signal processing circuit, and the present invention relates to a digital signal processing circuit in which an overflow of the input digital signal occurs when performing signal processing to change the level or frequency characteristics of an input digital signal that is digitally pulse modulated (such as a pulse code modulated signal). It is an object of the present invention to provide a digital signal processing circuit that can prevent noise generation due to overflow by occasionally performing a level clip operation. FIG. 1 shows a block system diagram of an example of a conventional digital signal processing circuit used, for example, in a recording/playback device of a digital audio system.
In the figure, a digital pulse-modulated digital signal, for example, an n-bit pulse code modulated signal (PCM signal), which enters the input terminal 1, is applied to the holding circuit 2 as (n+m) bits, where it is applied. After being held, it is applied to the multiplier 3 and multiplied by the m-bit coefficient from the coefficient multiplier 4. This multiplier 3
An (n+m)-bit digital signal is taken out and applied to the adder 5, and after being sequentially added to the (n+m)-bit output digital signal from the holding circuit 6, it is further applied to the holding circuit 6. An (n+m) bit digital signal is taken out from the holding circuit 6, fed back to the holding circuit 2 and adder 5, respectively, and outputted from the output terminal 7 as n bits. Note that the operations of the holding circuits 2 and 6, the multiplier 3, and the coefficient multiplier 4 are controlled by respective control signals. A digital signal processing circuit with such a configuration has a transfer function H(z) expressed in a discrete system (where z=
e ^sT , s: Laplace operator, T: sampling time), and normally the output digital signal y from the multiplier 3 is equal to the input digital signal x at the input terminal 1.
analog conversion level (hereinafter simply referred to as level)
It is designed not to exceed the maximum value of That is, it is usually designed so that the level of the input digital signal x and the level of the output digital signal y are in a one-to-one relationship, as shown by y=x{x≦1} in FIG. However, in reality, digital signal processing circuits
As shown in Figure 2 by y=2x {x≦1}, y=nx,
It may be used so that the level of the output digital signal y is higher than the level of the input digital signal x, or when used as a digital equalizer as shown in Figure 3, _one frequency component as shown by L may be amplified. In such cases, the input digital signal x is normalized by bit shifting (for example, if y = nx in Figure 2, the signal x is normalized to 1/n, and in the case of Figure ₃ , the signal Multiplier 3 (which normalizes constants (digital filter coefficients) for changing characteristics)
is applied. However, even in this case, there were cases where the level of the input digital signal was extremely high or overflow occurred when the amplification amount L at frequency ₁ in FIG. 3 was applied. For example, if we display each digital signal in two's complement format below, and also display it using a decimal point, such as 0.5 as "0.1000000" and -0.5 as "1.1000000," the input PCM signal x will be 8 bits. When the output coefficient of the coefficient multiplier 4 is 4 bits and is "01.11", the result of the operation of the multiplier 3 is "001.101111001", and the top 8 bits are calculated based on the decimal point position of the input PCM signal x. In this case, the output digital signal y of multiplier 3 is expressed as "1.1011110" (i.e., the input
Since the decimal point position of the PCM signal x is between the most significant bit (MSB) and the next bit of the MSB, the decimal point position of the above output digital signal y is also between the MSB and the next bit position of the MSB. is retrieved). The output digital signal y of this multiplier 3 shows a negative level such as "1.1011110" despite the multiplication of the positive digital signal x by a positive coefficient, and this is because an overflow has occurred. When sign inversion of the output signal due to this overflow occurs in a signal processing process such as an infinite impulse response (IIR) digital filter (digital equalizer) that changes the frequency characteristics of a digital signal, the IIR digital filter becomes a positive feedback loop. , which caused limit cycles due to oscillation and generated noise. The present invention eliminates the above-mentioned drawbacks, and an embodiment thereof will be described below with reference to FIGS. 4 to 6. FIG. 4 shows a block system diagram of an embodiment of the digital signal processing circuit according to the present invention. In the figure, the same components as those in FIG. 1 are given the same numbers, and their explanations will be omitted. The coefficient unit 8 supplies the multiplier 3 with a coefficient having a lower level, for example, than the original value. This is done by setting the reference level in the multiplier 3 corresponding to the average level of the input digital signal to a value as close as possible to the maximum value of the overall dynamic range _DL , as shown in FIG. 6, and setting it to prevent overflow. This is to make the margin area indicated by diagonal lines in the figure as small as possible. On the other hand, 9 is a signal processing section which outputs the output digital signal of the holding circuit 6.
A comparator 10 to which a predetermined p-bit (p is an integer greater than or equal to) signal including the MSB (described later) is applied, and the MSB is removed from the output digital signal of the holding circuit 6 according to the output value of the comparator 10 ( The switch circuit 12 selectively outputs a signal obtained by inverting the n-1) bit signal or its MSB signal by an inverter 11. (n-1)
The bit is taken out from the switch circuit 12 (n
-1) A digital signal as a bit signal is output. Note that the n-bit output digital signal output to the output terminal 7 is also fed back to the holding circuit 2. As a result, the circuit of this embodiment is
Configure IIR digital filter. The comparator 10 described above is provided to detect whether the output digital signal of the holding circuit 6 is an overflow signal. That is, for example, the input PCM signal x _k of input terminal 1 at time kT (T is sampling time) is a signal that is displayed as "0.1111000", and the original value "0111.0000" is shifted by 2 bits from the coefficient unit 8. Assuming that the attenuated coefficient a expressed as "000111.00" is applied to multiplier 3, a・x from multiplier 3
_k , a x _k-1 , the output digital signal of the adder 5 which adds these signals, and the output digital signal y of the 8-bit holding circuit 6.
_k is expressed as shown in the following table. however,
For convenience, x _k =x _k-1 .

[Table] As can be seen from this _table , while displaying the input PCM signal Since the shift has been performed, the actual decimal point position is the position indicated by the x mark of the output of adder 5 in the table. Here, in the case of a digital signal in two's complement representation,
The bits above the decimal point position up to the MSB must always have the same sign (same logical value), otherwise there will be an overflow.
Therefore, in this example, the output digital signal of the adder 5 is, as shown in the table above, from the MSB to the bit above the cross mark (one bit higher than the bit constituting the second bit of the final output digital signal (on the MSB side)). Since the total 5 bits up to bit ) do not have the same sign,
This means that there is an overflow. In view of the above points, the comparator 10 of this embodiment uses the MSB "0" in the output digital signal of the holding circuit 6.
and "0011" from the bit one bit above the second bit of the final output to the next bit of the MSB (as will be described later, it is also possible to use only the second bit of the final output). A comparison is made to determine whether or not the codes are the same, thereby detecting whether an overflow has occurred. The output signal of the comparator 10 is applied to the switch circuit 12, and when an overflow occurs, the output signal of the inverter 11 is outputted so that all (n-1) bit signals of the switch circuit 12 have the opposite sign to the MSB. In other words, when an overflow occurs, the output terminal 7 is
A digital signal is output in which the MSB and the bit groups below it have opposite signs, but this represents the maximum positive value or the maximum negative value in two's complement representation, and the MSB is always in the holding circuit 6. MSB of the output of
Since this is maintained, sign inversion does not occur, and as a result, a digital signal with a clipped level is output. Next, to explain the more specific operation of the signal processing section 9, FIG. 5 shows a circuit diagram of one embodiment of the signal processing section 9. As shown in FIG. In the figure, according to the display method, the output digital signal of the holding circuit 6 is as follows.
Assuming that it is a digital signal indicated by a display in which the decimal point is located between the second and third bits from the MSB, the MSB signal is a two-input exclusive logic signal corresponding to the comparator 10 described above. Applied to one input terminal of circuit 13, the MSB
The signal of the second bit from the second bit (that is, the signal of the bit one bit higher than the second bit of the final output) is applied to the other input terminal of the circuit 13. Further, the MSB output of the holding circuit 6 is transmitted via the inverter 11 to the input terminals A ₁ , A ₂ , . . . of the data selector 14 corresponding to the switch circuit 12.
..., A _o-1, and at the same time, it is directly output as the MSB of the final output. In addition, the input terminals B ₁ of the data selector 14,
B ₂ , ......, B _o-1 contain a predetermined sum (n-1) of the holding circuit 6, which is a total of (n-1) bits from the MSB to the second bit to the LSB of the final output digital signal. 1) Each bit signal is applied separately. Data selector 14 is exclusive OR circuit 1
The output signal of 3 is applied as a switching signal, and when this signal is logic “0”, the input terminal
The input signals of B ₁ , B ₂ , ......, B _o-1 are output as they are from the output terminals C ₁ , C ₂ , ......, C _o-1 , and on the other hand, the output signal of the exclusive OR circuit 13 When is logic "1", input terminals A ₁ , A ₂ , ......, A _o-
The configuration is such that _one input signal is output from output terminals C ₁ , C ₂ , . . . , Co _-1 . Data selector 1
The output signals of the output terminals C ₁ , C ₂ , ......, Co _-1 of 4 are the signals of the second, third, ... nth (LSB) bits from the MSB of the final output digital signal. becomes. Therefore, the output digital signal of the holding circuit 6
When the MSB signal and the second bit signal, which is one bit higher than the second bit of the final output, have the same sign, no overflow has occurred, and in this case, the data selector 1
4 is applied to the input terminals B ₁ to _{B o-1} .
A predetermined (n-1) bit signal excluding the MSB is passed through and output, thereby outputting an n-bit digital signal which has been subjected to arithmetic processing similar to the conventional one. Therefore, the output digital signal of the holding circuit 6
When the MSB signal and the signal of the second bit, which is one bit higher than the bit that constitutes the second bit of the final output, have different signs, an overflow has occurred, and the exclusive logic at this time is Since the logic of the output signal of the sum circuit 13 becomes "0", the data selector 14 switches and outputs a signal having a sign opposite to the MSB from the inverter 11 applied to the input terminals A ₁ to _{A o-1} . Therefore, when an overflow occurs, the overflow is reliably detected, and the output digital signal of the holding circuit 6 is
The MSB is the MSB of the final output digital signal.
Since all other bits of the final output have a different sign from the MSB, an n-bit digital signal of the level clipped to the maximum value is extracted without having its sign inverted. As a result, when the circuit of the present invention is applied to a digital filter, clipping can be performed without level fluctuation, noise generation due to overflow can be prevented, and limit cycles due to oscillation can be prevented in the case of an IIR digital filter. . In the above embodiment, the case of an IIR digital filter has been described, but the present invention can also be applied to a finite impulse response (FIR) digital filter or other digital signal processing. The signal to be compared with the MSB in the comparator 10 may be any signal from the bit above the second bit of the final output to the bit below the MSB. If there is movement (in the case of floating point system), it is necessary to compare at least one bit above the decimal point. ]. As described above, the digital signal processing circuit according to the present invention configures the sign of the MSB of the (m+n)-bit digital signal from the holding circuit and the second bit of the final output digital signal among the (m+n)-bit digital signals. One MSB from the bit
A comparator that compares and detects the difference in sign of the bits above the decimal point from the bit on the side to the bit below the MSB, and a comparator that switches depending on the output signal of this comparator to ensure that the signs compared by the comparators are all the same. , the LSB from the 2nd bit of the final output digital signal of the output digital signal of the holding circuit
If the compared signs are different, a signal of the opposite sign to the MSB of the output digital signal of the holding circuit is outputted to each bit forming the 2nd bit to LSB. A final output digital signal in which the MSB of the output digital signal of the switch circuit and the holding circuit that outputs each as a signal constitutes the MSB, and each output signal of the switch circuit constitutes each bit from the 2nd bit to the LSB. Since overflow can be reliably detected with a simple circuit configuration, it can be prevented by clipping it to the maximum value, and when applied to a digital filter, it can be used to detect overflow without level fluctuation. It can be clipped to prevent noise from occurring.
Furthermore, when applied to IIR digital filters, limit cycles due to oscillation can be prevented, and it can also be applied to digital signal processing (digital addition, subtraction, multiplication and division), and can be used to configure digital clippers, among other features. It is something.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an example of a conventional circuit, Figure 2 is a diagram showing examples of the level relationship between the input and output digital signals of the digital signal processing circuit, and Figure 3 is the frequency diagram of the digital signal processing circuit. 4 is a block system diagram showing an example of the circuit of the present invention, FIG. 5 is a circuit system diagram showing an example of the main part of FIG. 4, and FIG. It is a figure which shows the relationship between the dynamic range of a figure, and a reference level. 1... Digital signal input terminal, 2, 6... Holding circuit, 3... Multiplier, 4, 8... Coefficient unit, 5...
...Adder, 7...Digital signal output terminal, 9...
...Signal processing unit, 10...Comparator, 12...Switch circuit, 14...Data selector.

Claims (1)

[Claims] 1 Multiply the digital pulse modulated n-bit (n is an integer) input digital signal by the m-bit (m is an integer) coefficient from the coefficient multiplier, respectively,
In a digital signal processing circuit, a signal obtained by sequentially adding the digital signals obtained by the multiplication by an adder is supplied to a holding circuit, and a final output digital signal having a bit number smaller than (m+n) is obtained from the output of the holding circuit. The sign of the MSB of the (m+n)-bit digital signal from the above holding circuit and the (m+n)
One of the bits that constitutes the second bit of the final output digital signal.
A comparator that compares and detects the difference in sign of the bits above the decimal point from the bit on the MSB side to the bit one below the MSB, and the sign compared by the comparator is switched by the output signal of the comparator. are all the same, output the signals of each bit constituting the final output digital signal from the 2nd bit to the LSB among the output digital signals of the holding circuit, and when the signs compared by the comparator are different. is a switch circuit that outputs a signal having a different sign from the MSB of the output digital signal of the holding circuit as a signal of each bit constituting the above-mentioned 2nd bit to LSB, and a switch circuit of the output digital signal of the holding circuit.
A digital signal processing circuit comprising an output means for obtaining a final output digital signal in which the MSB constitutes the MSB and each output signal of the switch circuit constitutes each bit from the second bit to the LSB. .