JPH0879083A - D/a converter - Google Patents

Abstract

PURPOSE: To provide the D/A converter preventing switching noise in the D/A converter selecting an output of a D/A conversion device amplified by a multiple of β or an output of the D/A conversion device depending on input data so as to extend a switching dynamic range. CONSTITUTION: The D/A converter is provided with a data division processing unit selecting an output in response to the input data, an offset arithmetic operation device (1) 115 applying digital offset data so as to make an output offset of the D/A converter (1)113 amplified by a multiple of β at zero input zero, an offset arithmetic unit (2) 119 applying digital offset data so as to make an output offset of the D/A converter (2)118 zero, and an offset arithmetic unit (3)121 multiplying gain data with data of the D/A converter (2)118 so as to make an offset of the analog adder 120 zero caused when the data not being zero are received so that the result of addition of signals from the DAC(1)113 and the DAC(2)118 is zero on the design.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A converter which can be used for professional digital AV equipments requiring a wide dynamic range for output signals.

[0002]

2. Description of the Related Art In order to expand the dynamic range of an output signal, a conventional D / A converter has two D / A converters depending on whether the input signal data is smaller or larger than a predetermined value. Is distributed to two high-level and low-level D / A converters and added to obtain an analog output signal. For example, Radio Technical Journal December 1990, p. 170-
There was a D / A converter described on page 173.

The basic operation of a conventional D / A device will be described below with reference to the drawings. FIG. 8 is a block diagram of a conventional D / A converter. In FIG. 8, 810 is an input terminal and 8
11 is a processor, 812 is a first D / A converter, 81
Reference numeral 3 is a second D / A converter, 814 is an attenuator, 815 is an analog adder, and 816 is an output terminal. Processor 8
Reference numeral 11 determines the size of the input data D from the input terminal 810, and when a large signal exceeding the value K which is 1 / β times the full scale is input, as shown in FIG. A low-level signal B is output from the second output terminal of the output signal A, and the signal added by the analog adder 815 is output from the output terminal 816. On the other hand, when a signal smaller than the value K is input, the signal B is output from the second output terminal, zero is output from the first output terminal, and the signal added by the analog adder 815 is output from the output terminal 816. By thus distributing and outputting the plurality of D / A converters according to the size of the input data, a wider dynamic range can be obtained by using the D / A converters with a small number of bits.

[0004]

However, in the conventional D / A conversion apparatus, if there is a gain error or an offset caused by an error of an analog element, a discontinuity occurs when the input level exceeds the value K, and noise is generated. However, there is a problem that the performance is deteriorated due to the occurrence of the phenomenon.

For example, the attenuation amount of the attenuator 814 is exactly 1
If it is not / β times, the output of each D / A converter is shown in FIG.
As shown in (3), the characteristics are not uniform and noise occurs when the level is switched.

The present invention has been made in view of the above problems. Even if the analog output has an offset or the gain deviates from the calculated value due to an error in the element, the present invention corrects it with digital data. It is an object of the present invention to provide a D / A conversion device that smoothly switches the levels of two D / A converters and does not generate noise during switching.

[0007]

In order to achieve the above object, the D / A conversion apparatus of the present invention determines the size of the input digital data D and determines 1 / β times (β) of full scale.
When a signal larger than the value K of> 1) is input, the upper M bits are output from the first output terminal, and when a signal smaller than the value K is input, the value K is maximum from the second output terminal. A data division processing device for outputting the lower M bits of a value, a first adder having one input terminal connected to the first output terminal of the data division processing device, and the first addition A first D / A converter that converts the output data of the converter into an analog signal, an amplifier that gives a gain of approximately β to the output of the first D / A converter, and the input signal of the amplifier, A first offset arithmetic unit for outputting offset removal data, a multiplier having one input terminal connected to the second output terminal of the data division processing unit, and one input terminal for the output terminal of the multiplier. Second adder connected A second D / A converter that converts the output data of the second adder into an analog signal and an output signal of the second D / A converter that outputs offset removal data An offset arithmetic unit, an analog adder for adding the output signal of the amplifier and the output signal of the second D / A converter, and an output signal of the analog adder for inputting offset removal data. And an output of the first offset remover is connected to the other input terminal of the first adder, and an output of the second offset remover is added to the second adder. Is connected to the other input terminal of the multiplier, the output of the third offset removing device is connected to the other input terminal of the multiplier, and an analog output is taken out from the output terminal of the analog adder (first Configuration of )are doing.

Further, the D / A converter of the present invention judges the size of the input digital data D and inputs a signal larger than the value K which is 1 / β times (β> 1) of the full scale. Data division that sometimes outputs higher M bits from the first output terminal, and outputs lower M bits such that the value K becomes the maximum value from the second output terminal when a signal smaller than the value K is input. A processing device, a first adder having one input terminal connected to the first output terminal of the data division processing device, and a first D for converting output data of the first adder into an analog signal. / A converter, and the first
An amplifier that gives a gain of approximately β to the output of the D / A converter of the above, and a second of the data division processing device at one input terminal.
A multiplier to which the output terminal of is connected, a second adder whose one input terminal is connected to the output terminal of the multiplier, and a second converter which converts the output data of the second adder into an analog signal. D / A converter, the output signal of the amplifier and the second signal
An analog adder for adding output signals of the D / A converter, an analog switch for selecting and outputting any one of the amplifier, the second D / A converter, and the analog adder; An offset calculation device that inputs the output signal of the analog switch and outputs the offset removal data,
A first, a second and a third register for storing output data of the offset computing device, the output of the first register being connected to the other input terminal of the first adder, The output of the register is connected to the other input terminal of the second adder, the output of the third register is connected to the other input terminal of the multiplier, and the analog output is output from the output terminal of the analog adder. Is configured to be taken out (second configuration).

Further, the offset operation device in the D / A conversion device of the present invention compares the code F (n) of the current input signal with the code F (n-1) of the input signal one operation time before,
When (n) = F (n-1), the data C (n-1) one operation time before is output, and when F (n) ≠ F (n-1), the data -C (n-1) / A data updater that outputs 2 and an integrator that accumulates the output of the data updater are provided, and the output of the integrator is taken out from the output terminal.

[0010]

With the above-described first configuration, first, zero data is output from the data division processing device, and the first D / A
The data given to the first adder by the first offset arithmetic unit is adjusted so that the output signal offset of the amplifier having the gain of β times through the converter becomes zero. Similarly second
The data such that the output signal offset of the D / A converter of 1 is given to the second adder by the second offset computing device. Next, the direct current data (D), which is the maximum output of the second D / A converter, is output from the data division processing device to the second D / A converter.
Data is given to the converter side, and data (-) is given to the first D / A converter side.
D / β) is given. The gain on the first D / A converter side and the second
Since the difference in gain on the D / A converter side of the above appears at the output terminal of the analog adder as an offset output, the data provided to the multiplier is adjusted by the third offset computing device so that the offset of the analog adder becomes zero. To do. As described above, the characteristics of the first D / A converter side and the second D / A converter side
After matching the characteristics on the converter side, give normal input data, and drive the first D / A converter side when the input signal exceeds 1 / β times full scale, Sometimes the second D / A converter side is driven to obtain an output.

Further, in the above-described second configuration, the signal input to the offset computing device is switched by the analog switch, and the first to third offset computing devices in the first configuration are configured by one piece of hardware. ing. Each update data is stored in the three added registers.

[0012]

Embodiments of the D / A converter of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a D / A converter according to the first embodiment of the present invention.

In FIG. 1, 110 is an input terminal for digital data, 111 is a data division processing device, 112 is a first adder, 113 is a first D / A converter, 114 is an amplifier, and 115 is a first. Offset calculator, 116 is a multiplier, 117 is a second adder, 118 is a second D / A converter, 119 is a second offset calculator, 120 is an analog adder, 121 is a third offset calculator Device, 1
22 is an output terminal.

When the calibration is started, data zero is output from the data division processing device 111 to both the first output terminal and the second output terminal, and the first offset computing device 115 outputs the data OFST (0) = 0. Output. Since one input of the first adder 112 is zero, the data OFST (0) is given to the first D / A converter 113. First D
The analog signal converted and obtained by the A / A converter 113 is amplified by the amplifier 114 by about β times. The first offset arithmetic unit 115 outputs the code F of the amplified signal A.
After detecting (0), the next data OFST (1) = OFST (0) + Δ (1) = O
FST (0) + Δ is given to the first adder 112. Here, the data change amount Δ has an absolute value corresponding to the expected maximum value in the output of the amplifier 114 generated when the digital data is zero, and the sign is a sign opposite to the first detection code F (0). Is a value with.

At this time, the amplifier 114 outputs an analog signal corresponding to the data OFST (1) given to the first D / A converter 113, and the first offset computing device 115 outputs the code F ( 1) is detected and compared with the code F (0) one operation time before, and if F (1) = F (0), then (Formula 1) is used as the next data, and F (1) ≠ F ( If it is 0, then (Equation 2) is output as the next data and given to the first adder 112. After that, the calculation of OFST (i) = OFST (i-1) + Δ (i) is repeated according to the above procedure.

[0017]

[Equation 1]

[0018]

[Equation 2]

In this way, the data OFST (n) with which the offset of the signal A becomes zero is obtained.

Since the word length of the data to be given is actually limited, the update is terminated when the absolute value of the data change amount Δ (n) becomes less than or equal to the LSB of the data word length.

FIG. 3 shows changes in the output signal A of the amplifier 114 based on the above operation. Data OFST
When (0) = 0 is given, the signal A is positive, and at this time, the first offset arithmetic unit 115 uses (Equation 3) as update data.
give.

[0022]

(Equation 3)

Since the first data change amount Δ corresponds to the expected maximum value of the offset output of the amplifier 114 generated when the digital data is zero, the signal A becomes negative. Since the sign of the signal A is inverted, it becomes (Equation 4), and (Equation 5) is given as the update data.

[0024]

[Equation 4]

[0025]

(Equation 5)

When the update data OFST (2) is given, since the sign of the signal A remains negative, (Equation 6) is obtained, and (Equation 7) is given as the update data.

[0027]

(Equation 6)

[0028]

(Equation 7)

Here, the sign of the signal A changes positively (Equation 8), and (Equation 9) is given as update data.

[0030]

[Equation 8]

[0031]

[Equation 9]

After that, by repeating the above operation, the offset of the signal A approaches zero, and as a result, the first offset is obtained.
The input / output characteristics on the D / A converter 113 side of FIG.

FIG. 4 is a block diagram of the first offset computing device 115. In FIG. 4, reference numeral 410 denotes an input terminal, 42
0 is a data updater, 421 is a comparator, 422 is a first data holder, 423 is an exclusive OR gate, 424 is a second data holder, 425 is a multiplier, 426 is a selector, 430 is an integrator. 431 is an adder, 432 is a third data holder, and 440 is an output terminal.

The first data holder 422 is the comparator 42.
The second data holder 42 has the same logical data as the output of 1
4 is an amplifier 1 which is generated when digital data is zero
14 has an absolute value corresponding to the expected maximum value in the output, the code is initialized to a value Δ having a sign opposite to the first detection code F (0), and the third data holder 432 is initialized to zero. Be converted. The multiplication coefficient of the multiplier 425 is -1/2.

The signal input from the input terminal 410 is input to the positive input terminal of the comparator 421. On the other hand, the comparator 42
The negative input terminal of 1 is grounded, and outputs a logic 1 when the input signal is positive, and outputs a logic 0 when the input signal is negative.

When the signal input from the input terminal 410 is positive in the initial state, the comparator 421 outputs logic 1. At this time, since the first data holder 422 is initialized by the logic 1, the exclusive OR gate 423 to which the output signal of the comparator 421 and the output signal of the first data holder 422 are input is Outputs a logical 0. Selector 426
The output of the exclusive OR gate 423 is connected to the control terminal of the above, and since the logic 0 is being input now, the output signal of the second data holder 424 is selected.

The output of the selector 426 is connected to the input terminal of the second data holder 424, and is stored in the second data holder 424 as the amount of data change in the next calculation.

The first data holder 422 stores a logic 1 at the output of the comparator 421 as the next operation data. The output of the selector 426 is also input to the integrator 430, is added to the output of the third data holder 432 by the adder 431, and is added to the third data holder 432 as update data at the time of the next calculation. It can be stored. With the update data thus provided, the output of the amplifier 114,
That is, if the signal input from the input terminal 410 changes from positive to negative, the comparator 421 outputs a logic 0,
On the other hand, since the logical 1 is stored in the first data holder 422, the exclusive OR gate 423 outputs the logical 1. Since a logic 0 is input to the control terminal of the selector 426, the selector 426 selects the output signal of the second data holder 424 via the multiplier 425. That is, from the selector 426, the amount of data change in the previous calculation is -1.
The data that has been multiplied by / 2 is output, is added to the output of the third data holder 432 by the adder 431, and is stored in the third data holder 432 as update data for the next calculation. The same calculation process is performed thereafter, and when the absolute value of the data change amount becomes smaller than a predetermined value, the offset calculation process ends.

The second adder 117, the second D / A converter 118, and the second offset computing device 119 respectively include a first adder 112, a first D / A converter 113, and a first offset. The output data of the second offset calculation device 119 is updated so that the output signal B of the second D / A converter 118 also has an offset of zero, which has the same configuration as the calculation device 115.

Since the second offset computing device 119 is the same as the first offset computing device 115, its explanation is omitted.

Next, the data division processing unit 111 causes the input data of the second D / A converter 118 to exceed the full scale by the data given from the second offset arithmetic unit 119 and the third offset arithmetic unit 121. The maximum possible direct current data D2 is output from the second output terminal within the range that is not expected. The second D /
Data D1 = -D2 / β for outputting the signal A from the amplifier 114 whose absolute value is equal to that of the output signal B of the A converter 118 and whose sign is opposite is output from the first output terminal.

The third offset computing device 121 first outputs data (Equation 10).

[0043]

[Equation 10]

At this time, the sign of the output signal C of the analog adder 120 is detected by the third offset computing device 121, whereby the gain on the side of the first D / A converter 113 and the second
The magnitude of the gain on the D / A converter 118 side can be discriminated. For example, data is given such that the output signal B of the second D / A converter 118 is positive and the output signal A of the amplifier 114 is negative, and (1) the output signal C of the analog adder 120 is negative. In some cases, it can be seen that the gain on the first D / A converter 113 side is larger than the gain on the second D / A converter 118 side. In this case, data (Equation 11) is given as the data of the third offset computing device 121.

[0045]

[Equation 11]

Second D / when data OFST (1) is given
The output signal B of the A converter 118 shifts in the positive direction (B ′) as shown in FIG. 6, and the output signal C of the analog adder 120 shifts in the positive direction (C ′) accordingly.

(2) When the output signal C of the analog adder 120 is positive, the gain on the first D / A converter 113 side may be smaller than the gain on the second D / A converter 118 side. Recognize. At this time, data (Equation 12) is given as the data of the third offset calculation device 121.

[0048]

[Equation 12]

As the data change amount Δ '(0), when the data D1 and the data D2 are given respectively, the amplifier 11
The output data C of the analog adder 120, which is the addition result of the output data A of No. 4 and the output data B of the second D / A converter 118, corresponds to the maximum value expected from the error range of the analog element. Give it.

Thereafter, similarly to the first offset calculation device 115 and the second offset calculation device 119, the detection of the change in the sign of the signal C and the update of the offset calculation data are repeated,
The offset of the signal C is set to zero, that is, the first D /
The data OFST (m) that equalizes the gain on the A converter 113 side and the gain on the second D / A converter 118 side is obtained. Since the word length of the data to be given is actually limited, the update is terminated when the absolute value of the data change amount Δ ′ (m) becomes less than or equal to the LSB of the data word length.

After the calibration is completed as described above, the data division processing device 111 operates on the input terminal 11
The size of the input data D from 0 is determined, and when a signal larger than the value K which is 1 / β times the full scale is input, the upper M bits of the first output terminal and the second output terminal are output. Outputs zero, and when a signal smaller than the value K continues to be input for a predetermined period, the value K is output from the second output terminal.
Is output from the second output terminal of the lower M bits such that the maximum value becomes.

In the first embodiment, since the calculation processing of the first offset calculation device 115 and the second offset calculation device 119 can be performed at the same time, the calibration time can be shortened.

Next, a second embodiment of the D / A converter of the present invention will be described with reference to the drawings. FIG. 2 shows a block diagram of a D / A converter according to the second embodiment of the present invention. In FIG. 2, 210 is an input terminal and 211
Is a data division processing device, 212 is a first adder, 213
Is a first D / A converter, 214 is an amplifier, 230 is an analog switch, 215 is an offset arithmetic unit, 231 is a first register, 216 is a multiplier, 217 is a second adder, and 218 is a second adder. The D / A converter, 232 is a second register, 233 is a third register, 220 is an analog adder, and 222 is an output terminal.

Input terminal 210, data division processing device 21
1, a first adder 212, a first D / A converter 213,
Amplifier 214, offset calculation device 215, multiplier 21
6, the second adder 217, the second D / A converter 218,
The analog adder 220 and the output terminal 222 are respectively the first
Input terminal 110, data division processing device 111, first adder 112, and first D / A converter 11 in the embodiment of FIG.
3, amplifier 114, first offset calculation device 115,
The multiplier 116, the second adder 117, the second D / A converter 118, the analog adder 120, and the output terminal 122 have the same configuration and operate in the same manner, and therefore detailed description thereof will be omitted.

At the time of calibration, first the amplifier 2
The first of the analog switches 230 to which the 14 outputs are connected
The input terminal is selected, and the data such that the offset of the output signal A of the amplifier 214 becomes zero is stored in the first register 231 through the offset calculation device 215 in the same procedure as in the first embodiment. Next, the second input terminal of the analog switch 230 to which the output of the second D / A converter 218 is connected is selected, and the second input terminal is selected via the offset calculation device 215 in the same procedure as in the first embodiment. The data such that the offset of the output signal B of the D / A converter 218 of 0 is stored in the second register 232.

Finally, the third input terminal of the analog switch 230 to which the output of the analog adder 220 is connected is selected, and the analog adder is processed through the offset calculation device 215 in the same procedure as in the first embodiment. 220 output signal C
Is zero, that is, the first D /
The data that makes the gain on the A converter 213 side equal to the gain on the second D / A converter 218 side is the third register 23.
It is stored in 3 and the calibration is completed. The operation after the end of the calibration is also the same as that of the first embodiment, so the explanation is omitted.

In the second embodiment, since the offset calculation device is composed of one piece of hardware, the scale can be reduced.

[0058]

As described in detail above, the D / A conversion device of the present invention is effective in switching between two D / A converters even if there is an amplifier gain error or offset due to an analog element error. Noise can be suppressed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a D / A conversion device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a D / A conversion device according to a second embodiment of the present invention.

FIG. 3 is an explanatory diagram showing a process of offset removal calculation in the first or second embodiment of the present invention.

FIG. 4 is a block diagram showing the configuration of an offset calculation device according to the first or second embodiment of the present invention.

FIG. 5 is a characteristic diagram showing characteristics of each D / A conversion block before and after an offset removal calculation in the first or second embodiment of the present invention.

FIG. 6 is a characteristic diagram for explaining characteristics of an adjustment process of a gain adjustment calculation in the first or second embodiment of the present invention.

FIG. 7 is a characteristic diagram showing characteristics of each D / A conversion block after gain adjustment calculation in the first or second embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a conventional D / A conversion device.

FIG. 9 is a waveform diagram showing an output waveform of a conventional D / A converter.

FIG. 10 is a characteristic diagram showing characteristics of each D / A conversion block of a conventional D / A conversion device.

[Explanation of symbols]

 110 Input Terminal 111 Data Division Processing Device 112 First Adder 113 First D / A Converter 114 Amplifier 115 First Offset Calculation Device 116 Multiplier 117 Second Adder 118 Second D / A Converter 119 Second offset calculation device 120 Analog adder 121 Third offset calculation device 122 Output terminal 210 Input terminal 211 Data division processing device 212 First adder 213 First D / A converter 214 Amplifier 215 Offset calculation device 216 Multiplier 217 Second adder 218 Second D / A converter 220 Analog adder 222 Output terminal 230 Analog switch 231 First register 232 Second register 233 Third register

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hideaki Hatanaka 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (3)

[Claims] 1. The size of the inputted digital data D is judged, and when a signal larger than a value K which is 1 / β times (β> 1) of the full scale is inputted, the M higher than the first output terminal is detected. A data division processing device which outputs bits and outputs the lower M bits such that the value K becomes the maximum value from the second output terminal when a signal smaller than the value K is input; A first adder connected to a first output terminal of the data division processing device; a first D / A converter for converting output data of the first adder into an analog signal; An amplifier that gives a gain of approximately β to the output of the D / A converter, a first offset computing device that inputs the output signal of the amplifier and outputs offset removal data, and the data division processing device at one input terminal Second output of , A second adder having one input terminal connected to the output terminal of the multiplier, and a second D / which converts the output data of the second adder into an analog signal. An A converter, a second offset computing device that inputs the output signal of the second D / A converter and outputs offset removal data, an output signal of the amplifier, and the second D / A converter And an analog adder for adding the output signals of the analog offset adder and a third offset arithmetic unit for receiving the output signal of the analog adder and outputting the offset removal data. The output of the second offset removing device is connected to the other input terminal of the first adder, and the output of the third offset removing device is connected to the other input terminal of the second adder. The other input of the multiplier Connected to a terminal, D / A converter, characterized in that they were taken out an analog output from an output terminal of the analog adder. 2. The size of the input digital data D is judged, and when a signal larger than a value K which is 1 / β times (β> 1) of the full scale is input, M higher than the first output terminal is detected. A data division processing device which outputs bits and outputs the lower M bits such that the value K becomes the maximum value from the second output terminal when a signal smaller than the value K is input; A first adder connected to a first output terminal of the data division processing device; a first D / A converter for converting output data of the first adder into an analog signal; An amplifier that gives a gain of approximately β to the output of the D / A converter, a multiplier having one input terminal connected to the second output terminal of the data division processing device, and one input terminal of the multiplier. A second adder to which the output terminal is connected, A second D / A converter for converting the output data of the second adder into an analog signal; and an analog adder for adding the output signal of the amplifier and the output signal of the second D / A converter. An analog switch that selects and outputs any one of the amplifier, the second D / A converter, and the analog adder; and an offset that inputs an output signal of the analog switch and outputs offset removal data. An arithmetic unit and first, second, and third registers for storing output data of the offset arithmetic unit are provided, and the output of the first register is connected to the other input terminal of the first adder. , The output of the second register is connected to the other input terminal of the second adder, the output of the third register is connected to the other input terminal of the multiplier, the output of the analog adder Terminal? D / A converter, characterized in that they were taken out of the analog output. 3. The offset calculation device compares the code F (n) of the current input signal with the code F (n-1) of the input signal one calculation time before, and F (n) = F (n-1) ), Output the data C (n-1) one operation time before, and output the data -C (n-1) / 2 when F (n) ≠ F (n-1). The D / A converter according to claim 1 or 2, further comprising an integrator that accumulates an output of the data updater, wherein an output of the integrator is taken out from an output terminal.