JPS6318366B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a nonlinear distortion reduction circuit for a digital filter, and an object of the present invention is to provide a circuit capable of reducing multiplication errors, that is, nonlinear distortion, occurring in a multiplier with a limited number of bits in a digital filter. FIG. 1 shows a block system diagram of an example of a conventional acyclic digital filter. In the figure, 1 is an input terminal, from which an m-bit digital signal that is a pulse code modulation (PCM) or differentially modulated pulse modulation wave is held by an input register 2 and then transferred to a multiplier 4. Here, the signal is multiplied by the digital coefficient from the coefficient unit 3 and then supplied to the adder 5. Adder 5 is multiplier 4
The digital signal obtained by the addition is added to the output digital signal of the register 6, and the digital signal obtained by the addition is applied to the register 6 again and outputted from the output terminal 7. The digital signal from the output terminal 7 is passed through a DA converter (not shown) and is extracted as an analog signal in which a frequency characteristic corresponding to the coefficient of the coefficient multiplier 3 is added to the original analog signal. The above acyclic digital filter has a sampling period of an input digital signal of T and a time of nT.
The input digital signal sequence in x _o is coefficient multiplier 3
Assuming that the coefficient of the equation is a _i and the output digital signal sequence at time nT is y _o , it is expressed by the following difference equation. y _o = _N-1 〓 ⁱ⁼⁰ a _i x _oi (1) Fig. 2 shows a block system diagram of an example of a conventional cyclic digital filter. In the figure, the same components as in FIG. 1 are denoted by the same reference numerals, and their explanations will be omitted. The n-bit output digital signal of the adder 5 is fed back to the input register 2 and subjected to predetermined signal processing (at this time, the output coefficient value of the coefficient multiplier 3 becomes b _i ). As a result, the cyclic digital filter shown in FIG. 2 is expressed by the following difference equation. y _o = _N-1 〓 ⁱ⁼⁰ a _i x _oi − _N-1 〓 ⁱ⁼⁰ b _i y _oi (2) In this way, digital filters are both acyclic and cyclic. Also, multiplier 4
use. Here, assuming that the number of bits of the two input digital signals is m bits and n bits, the multiplier 4 normally outputs a (m+n) bit digital signal. However, the number of bits of the digital signal that can be transmitted by the multiplier 4 is limited by various constraints, and therefore errors, that is, nonlinear distortion, occur due to the finite number of bits. On the other hand, it is possible that the number of bits in the multiplier 4 is smaller than that of the input digital signal, but even in this case, information other than the effective bits of the input digital signal will be deleted. The above-mentioned nonlinear distortion had a large effect on the lower bits of the digital signal. The present invention eliminates the above-mentioned drawbacks, and one embodiment thereof will be described below with reference to the drawings of FIGS. 3 to 6A to 6C. FIG. 3 is a block system diagram of an embodiment in which the circuit of the present invention is applied to an acyclic digital filter, and FIG. 4 is a block system diagram of an embodiment in which the circuit of the present invention is applied to a cyclic digital filter. shows. In Figures 3 and 4, the same components are denoted by the same reference numerals, and in Figures 1 and 2.
Components that are the same as those in the figures are given the same reference numerals, and their explanations will be omitted. The basic operation of the circuit of the present invention in an acyclic digital filter and a cyclic digital filter is the same. In Figures 3 and 4, input terminal 1 has discrete time and amplitude axes obtained by sampling and quantizing an audio signal at a predetermined sampling period using an AD converter (not shown). A binary digital signal (pulse code modulated wave or constant difference modulated wave) is input. In addition, this digital signal is expressed in two's complement representation as an example below, and its first
The significant bit (LSB) indicates the lowest input audio signal level, and the bit following the MSB indicates the highest input audio signal level. The above-mentioned digital signal (assuming m bits) that has entered the input terminal 1 is supplied to the delay device 10 via the input register 2, where it is delayed by at least one sampling period and then sent to the shift register 14.
is applied to the signal, and is shifted in the MSB direction by a shift pulse from a detection/controller 11, which will be described later, and is output as an n-bit digital signal.
Here m>n. The m-bit digital signal from the input register 2 is also supplied to the detection/controller 11, and is delayed for a predetermined time by the delay device 12 for detection/controller 11.
The signal is supplied to the controller 13. Detector/controller 11, 1
3 has a configuration as shown in Fig. 5, and the same value as the MSB of the input digital signal is P than the MSB.
If the bits continue in the direction of the lower bits,
In order to shift the input digital signal by (P-1) bits, (P-1) shift pulses are output. That is, in FIG. 5, the input digital signal from the input terminal 1 is sent via the input register 2, and the output of the upper 5 bits including the MSB is supplied to the input signal determination circuit 19 which is constituted by an exclusive OR circuit. and here the input digital signal is
It is determined how many bits have the same sign as the MSB in the upper 5 bits, and the number to be shifted is determined based on this. The output signal of this input signal determination circuit 19 is supplied to an encoder 20 , where it is converted into a hexadecimal number and supplied to a comparator 22 . On the other hand, a control clock pulse enters the input terminal 17 and is applied to the counter 21, while being applied to the gate circuit 23. The counter 21 counts the rising edge of the control clock pulse and supplies a 4-bit count output to the comparator 22, where the value is compared with the 4-bit output from the encoder 20. Here, an example of the output digital value of the input signal determination circuit 19 and the output digital value of the encoder 20 is as shown in Table 1.

[Table] When the output of the encoder 20 and the output of the counter 21 respectively match, the comparator 22 applies a gate pulse to the gate circuit 23 to close the gate circuit 23 from then on, and until the output matches the output of the counter 21, the comparator 22 applies a gate pulse to the gate circuit 23. Leave 23 open. Therefore, for example, if the input digital signal is 12 bits (m=12), "0000 1011
1111'', the output of the input signal determination circuit 19 is the exclusive OR output of the MSB and 4 bits other than the MSB among the upper 5 bits including the MSB, so it becomes ``1110'', and the encoder 20 outputs the From this, it is detected that the upper 4 bits including the MSB are a joint code, and "0100" is output. Therefore,
The comparator 22 outputs a gate pulse that closes the gate circuit 23 when the fourth control clock pulse from the input terminal 17 arrives.
3, the fourth and subsequent control clock pulses are not output to the output terminal 24, and a total of three control clock pulses are output as shift pulses. The input digital signal of the shift register 14 is shifted by a number of bits equal to the number of output shift pulses of the detection/controller 11 obtained in this way. Note that the shift direction is shift register 1.
4 is predetermined as the MSB direction. The number of bits of the output digital signal of the shift register 14 is determined by taking into account the configuration of the multiplier 4 and the number of bits of the output coefficient of the coefficient multiplier 3. It shall be bit. The output n-bit digital signal of the shift register 14 is obtained by shifting the input digital signal, in which the same value as the MSB continues in the direction of P bits lower than the MSB, by (P-1) bits in the direction of the MSB. Since the input digital signal is expressed in two's complement representation, no important high-level audio signal information is lost, and it also contains relatively low-level audio signal information.
Apparently, the level of the original audio signal is increased uniformly. The output n of this shift register 14
The bit digital signal is supplied to a multiplier 4, where it is multiplied by an n-bit digital signal (coefficient) from a coefficient unit 3 to become a 2n-bit digital signal, and then supplied to a shift register 15. The shift register 15 receives the LSB by the shift pulse from the detection/controller 13 having the configuration shown in FIG.
direction. The number of bits shifted is the same as the number of bits shifted in the MSB direction by the shift register 14, and the output of the shift register 15 is applied as an m-bit digital signal to the input terminal A of the adder 5. After being added to the output digital signal of the register 6 which enters the input terminal B, the upper m bits are outputted as an output digital signal. Shifting in the LSB direction mentioned above using the shift register 15 and returning to the original state is as follows:
This is because the level of the original audio signal has apparently increased due to the shift in the MSB direction by the shift register 14, so this is returned to the original level of the original audio signal. FIG. 6A shows the start/stop control signal waveform of the multiplier 4, which is generated based on a clock pulse from a clock pulse generator (not shown), and at the rising edge of which a multiplication operation (for example, a ₁ x _o-1 ) is performed. , the multiplication result from the previous multiplication operation (e.g.
a ₀ x _o ) is output. 6B shows the output shift pulse of the detection/controller 11, and FIG. 6C shows the output shift pulse of the detection/controller 13. Further, r indicates the delay until the output of the comparator 22 shown in FIG. 5 is determined. Next, the output results of the conventional cyclic digital filter are shown in Table 2.
The output results of the cyclic digital filter shown in the figure are shown in Table 3, and the results are compared. However, for the sake of simplicity, it is assumed that the cyclic digital filter operates as expressed by the following differential equation. y _o =a ₀ x _o −b ₁ y _o-1Also , as an initial condition, {x _o }=0000 1011 1111 {y _o-1 }=0000 0000 0000 {a ₀ }=0100 1010 {−b ₁ }= 1100 0000, and in Tables 2 and 3, the ∧ mark such as x _o indicates a signal that has been bit shifted in the shift register 14 or 15. Furthermore, m=12, n=
8.

[Table] In Tables 2 and 3, () indicates that the values are not actually output.

【table】

[Table] In Table 3, the A input of the adder 5 is also the output of the shift register 15. From Tables 2 and 3 above, for example, the output of adder 5
While y _o+2 is "0000 0100" in the conventional filter, it becomes "0000 0101" in the cyclic digital filter shown in FIG. 4 to which the circuit of the present invention is applied, and the two are different. According to the embodiment shown in FIG. 4, the input digital signal of the multiplier 4 has four bits including the LSB of the input digital signal of the input terminal 1, x _o , x _{o +1} of Table 3, and Table 2 As can be seen from the outputs x _o and x _o+1 of input register 2, the second
Compared to the conventional cyclic digital filter shown in FIG. Therefore, the final output of the digital filter to which the circuit of the present invention is applied clearly has less nonlinear distortion than the conventional one, and the effect of reducing this nonlinear distortion is due to the fact that the original analog signal of the input digital signal is low in the above embodiment. It's great when it's on the level. As mentioned above, the nonlinear distortion reduction circuit of the digital filter according to the present invention is configured such that the bit having the same value as the MSB value of the digital signal from the input register is
First and second detection/control for detecting how many bits continue from the MSB in the direction of lower bits and outputting the same number of shift pulses corresponding to the detected number and for shifting bits in mutually opposite directions. a delay device for delaying the input digital signal of the second detection/controller by a predetermined period relative to the input digital signal of the first detection/controller;
The digital signal from the input register is input by the shift pulse from the first detection/controller.
A first shift register that shifts in the MSB direction and outputs it to the multiplier, and a digital signal from the multiplier is shifted in the MSB direction by the first shift register in response to a shift pulse from the second detector/controller. LSB for the same number of bits as the number of bits
Since the multiplier is configured with a second shift register that shifts in the direction and outputs it to the adder, it is possible to significantly reduce nonlinear distortion that occurs due to the limited number of bits in the multiplier. It is effective for the original analog information signal, and even if the number of bits in the multiplier is limited, the performance of the multiplier can be fully utilized (usually when the low-level original analog information signal is processed by digital signal processing). The performance of the multiplier when inputting a digital signal obtained by
It drops to about 3. ), does not require complicated circuits and does not significantly increase the number of parts.
It has the advantage of being relatively simple and inexpensive.

[Brief explanation of the drawing]

FIG. 1 is a block system diagram showing an example of a conventional acyclic digital filter, FIG. 2 is a block system diagram showing an example of a conventional cyclic digital filter, and FIG. 3 is a block system diagram showing an example of a conventional acyclic digital filter. FIG. 4 is a block system diagram showing an example when the circuit of the present invention is applied to a recursive digital filter, and FIG. 6A to 6C are signal waveform diagrams for explaining the operation of FIGS. 3 and 4, respectively. 1... Digital signal input terminal, 2... Input register, 4... Multiplier, 5... Adder, 6... Register, 7, 8... Output terminal, 10, 12... Delay device, 11, 13 ...detection/controller, 14, 15
...Shift register, 19...Input signal judgment circuit, 17...Control clock pulse input terminal, 2
4...Shift pulse output terminal.

Claims (1)

[Claims] 1. A digital signal obtained by sampling an analog information signal at a predetermined sampling period and converting it into a binary code is held in an input register, and the digital signal from this input register is sent to a multiplier. In the digital filter configured such that a digital signal obtained by multiplying by a predetermined coefficient is added to an output signal of a register by an adder and then supplied to the register, and an output digital signal can be taken out from the adder, the input register Detect how many bits of the same value as the MSB value of the digital signal continue in the lower bit direction than the MSB, and select the same number of bits corresponding to this detected number and for shifting bits in opposite directions. first and second detectors/controllers each outputting a shift pulse, and an input digital signal of the second detector/controller is set to a predetermined value relative to an input digital signal of the first detector/controller. a delay device that delays a period of time; a first shift register that shifts the digital signal from the input register in the MSB direction by a shift pulse from the first detection/controller and outputs it to the multiplier;
The digital signal from the multiplier is shifted in the LSB direction by the same number of bits as the number of bits shifted in the MSB direction by the first shift register by the shift pulse from the second detection/controller, and then added. 1. A nonlinear distortion reduction circuit for a digital filter, comprising a second shift register for outputting to a digital filter. 2 The input digital signal of the input register is
2. The nonlinear distortion reduction circuit for a digital filter according to claim 1, wherein the digital filter is processed so that the level of the analog information signal becomes smaller as the bit array moves toward LSB.