JPH0718177Y2 - Muting circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a muting circuit in a digital audio device.

In recent audio equipment, the following devices have been put into practical use with the introduction of digital technology.

After sampling the audio signal and converting it to digital data, special signal processing is performed to record it on an optical disk or magnetic tape, and the digital data recorded on these information recording media is read, and the reverse of the above is performed. Signal processing, and then digital-to-analog conversion to restore the original audio signal.

By the way, audio devices are provided with a muting function that instantly lowers the volume level. Conventionally, the following method has been adopted as a method of applying muting in such digital audio devices.

The first is a method for forcibly setting digital data to [0] by a miuteing signal, as shown in FIG.

The second method is, as shown in FIG. 3 (b), a method of detecting a zero-cross where the digital data becomes [0] after the input of the miuteing signal and applying the miuteing accordingly.

[Problems to be Solved by the Invention] In the first method, since digital data is forcibly set to [0], noise is generated when digital-analog conversion is performed.

The second method does not generate noise when digital-to-analog conversion is performed because zero crossing is detected and miuteing is applied according to the zero crossing. However, as shown in FIG. 3 (c), after the miuteing signal is input, , If the zero cross of digital data does not come immediately, the function as a miuteing cannot be realized. Therefore, after a lapse of a certain time, it is necessary to forcibly set the digital data to [0] and perform the miuteing, so that noise is generated when the digital-analog conversion is performed as in the first method.

[Means for Solving Problems] The present invention provides a k-bit counter output in an audio device in which digital data corresponding to an audio signal is given by n-bit digital data [Dn-1Dn-2 ... D1D0]. Kn-1Kn-2 ... K1K0] output up / down counter means, and the digital data [Dn-1Dn-2 ... D1D0] and the counter output [Kn-1Kn-2 ... K1K0] are multiplied. Output means for outputting the digital data [Dn-1Dn-2 ... D1D0] and the counter output [Kn-1Kn-2 ... K1K0] by up-counting the up / down counter means. By multiplying the multiplication output with and down-counting the up / down counter means, the digital data [Dn-1Dn-2 ... D1D0] and the counter output [Kn-1Kn-2 ... K1K0] Reduce the multiplication output It is characterized by

[Operation] According to the above configuration, the up / down counter means down-counts when the meeting is ON, and the counter output [Kn-1Kn-2 ... K1K0] is [111 …… 11] [111 …… 10 ] :: Changes like this.

Therefore, the multiplication output of this counter output and the digital data [Dn-1Dn-2 ... D1D0] gradually decreases, and when the counter output reaches [000 …… 00], the multiplication output becomes It becomes [0].

When the meeting is off, the up / down counter means counts up, and the counter output [Kn-1Kn-2 ... K1K0] changes as [000 …… 00] [000 …… 01] :::.

Therefore, the multiplication output of this counter output and the digital data [Dn-1Dn-2 ... D1D0] gradually increases, and when the counter output eventually becomes [111 …… 11], the multiplication output becomes It becomes the above digital data [Dn-1Dn-2 ... D1D0] itself.

[Embodiment] A representative embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

First, the basic configuration of this embodiment will be described with reference to FIG.

In this embodiment, the digital data corresponding to the audio signal is given as n-bit digital data [Dn-1Dn-2 ... D1D0]. Also, this digital data is given as serial data.

This serial data [Dn-1Dn-2 ... D1D0] is 1 in synchronization with the clock signal that divides one word.
Words are sequentially input from the input terminal 1 and converted into parallel data [Dn-1Dn-2 ... D1D0] by the serial-parallel data converter 2.

This parallel data is latched by the first latch circuit 3, and the latch output is input to the multiplier 4.

On the other hand, the k-bit counter output [Kn-1Kn-2 ... K1K0] of the up / down counter circuit 5 is input to the multiplier 4, and this counter output is multiplied by the parallel data.

The up / down counter circuit 5 operates as follows.

When the meeting is ON, the up / down counter circuit 5 is loaded with hex (FF) [111 …… 11], and the clock signal is down-counted, and the counter output is [111 …… 10] [111]. ...... 01]: Change to, and eventually become [000 …… 00].

When the meeting is off, the up / down counter circuit 5 is loaded with zero zero [000 ... 00], and the clock signal is up counted, and the counter output is [000 …… 01] [000 …… 10]. ] :: changes to, and eventually becomes [111 …… 11].

That is, the up / down counter circuit 5 up / down-counts the clock signal for each word of the parallel data and sequentially increases or decreases the counter output.

Therefore, in the multiplier 4, when the meeting is ON, the parallel data [Dn-1Dn-2 ... D1D0] is reduced by the counter output [111 ... 11] for each word. ] [111 …… 10] :: It is sequentially multiplied with [000 …… 00], and the multiplication output becomes smaller,
Eventually, it will be [000 …… 00].

When muting is OFF The above parallel data [Dn-1Dn-2 ... D1D0] increments the contents of each word. Counter output [000 …… 00] [000 …… 01] ：： [ 111 …… 11] are sequentially multiplied, and the multiplication output gradually increases,
Eventually, it becomes the above parallel data [Dn-1Dn-2 ... D1D0] itself.

The multiplication output of the multiplier 4 is converted into serial data [Dn-1Dn-2 ... D1D0] by the parallel-serial data converter 6 and output from the output terminal 7.

A control circuit 8 controls the multiplier 4, the up / down counter circuit 5 and the parallel-serial data converter 6.

Next, a specific example of the multiplier 4 will be described with reference to FIG.
In the figure, the part surrounded by the dotted line operates as the multiplier 4, and the same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

In this embodiment, the digital data corresponding to the audio signal is given as 2's complement data [D15D14 ... D1D0], and it is given as 16-bit serial data. The up / down counter circuit 5 is an 8-bit up / down counter, and its counter output [K7K6 ... K1K0] is given as 8-bit parallel data.

The multiplexer circuit 13 shifts to the signal path 9 side when the muting is held in the OFF state and normal operation such as music reproduction is performed.
The latch output from the latch circuit 3 is input to the second latch circuit 14 through the signal path 9 and the multiplexer circuit 13. The latch output latched by the second latch circuit 14 is converted into serial data [D15D14 ... D1D0] by the parallel-serial data converter 6 and output from the output terminal 7.

When the meeting is ON or OFF, the multiplexer circuit 13 shifts from the signal path 9 side to the shift circuit 12 side.

Parallel data (hereinafter referred to as PD) [D15D14 ... D1D0] from the first latch circuit 3 is sequentially input to the gate circuit 10 word by word in synchronization with a clock signal for delimiting one word.

That is, the parallel data PD changes like PDn-1PDnPDn + -... in synchronization with the clock signal for delimiting one word.

On the other hand, the 8-bit counter output [K7K6 ... K1K0] from the up / down counter circuit 5 is converted by the parallel-serial data converter 15 into serial data (hereinafter referred to as SK) [K7K6 ... K1K0]. .

Since the up / down counter circuit 5 up / down counts the clock signal for delimiting the one word, the serial data SK changes as follows: SKm-1SKmSKm + 1.

In this way, the parallel data PD changes like PDn-1PDnPDn + -... in synchronism with the clock signal for delimiting one word, and accordingly, the counter output of the up / down counter circuit 5 is changed. The parallel-serial data converted serial data SK changes like ...... SKm-1SKmSKm + 1 ..., but during one cycle of the clock signal that divides one word, that is, one word of the parallel data PD. Each time, the following operation is performed.

The serial data SK is sequentially input to the gate circuit 10 from the least significant bit (LSB) as [K0] [K1] ... [K6] [K7].

Then, the parallel data PD and the serial data SK
LSB of this serial data SK ([K
The gates are sequentially taken from [0]).

Here, at a certain time point m, the gate output between the parallel data PD and each bit of the serial data SK is G0.
m, G1m …… G6m, G7m, the gate output is G0m = PDn × [K0] m G1m = PDn × [K1] m :: G6m = PDn × [K6] m G7m = PDn × [K7] m become that way.

In the first step, the gate output G0m of the above gate circuit 10
Pass through the 17-bit adder 11 and the shift circuit 12
It is shifted by 1 bit to the side, becomes * S0m, and is latched by the second latch circuit 14.

In the next step, the data * S0m latched in the second latch circuit 14 and the gate output G1m are added by the 17-bit adder 11 and then by the shift circuit 12 to the LSB side.
Bit-shifted to * S1m and the second latch circuit 14
Be latched on.

After that, the same operation is repeated until the gate outputs G2m, G3m ...
... G6m and the latch output of the second latch circuit 14 (addition output Gk-1m immediately before the present addition output Gkm (k = 0 to 7))
* Sk-1m) which is shifted by 1 bit to the LSB side are sequentially added by the 17-bit adder 11, and then these addition outputs S0m, S1m ... S6m are shifted to the LSB side by the shift circuit 12. Shifted by 1 bit, * S2m, * S3m ...
* S6m.

That is, the addition outputs S0m, S1m ... S6m are S1m = G0m S1m = G1m + * S0m :: S6m = G6m + * S5m, and the final addition output S7m is S7m = G7m + * S6m.

This means that the parallel data PDn at a certain time point m and the serial data SKm are multiplied during one cycle of the clock signal for delimiting the one word, and the final addition output S7m is S7m = PDn × It is represented by SKm.

This addition output S7m is shifted by 1 bit to the LSB side by the shift circuit 12 and becomes * S7m, which is input to the multiplexer circuit 13 and the latch circuit 14 and latched.

Here, the 2's complement data [D15D14 ... D1D0] is multiplied by a coefficient (counter output [K7K6 ... K1K0] of the up / down counter circuit 5) to attenuate the 2's complement data. In this case, since the change of the coefficient only needs to be on the positive side, its MSB needs to be always [0]. Therefore, in the present embodiment, as described above, the final addition output S7m is shifted to the LSB side by one bit to obtain the M of * S7m.
SB is set to [0].

The latch output * S7m is converted into serial data [D15D14 ... D1D0] by the parallel-serial data converter 6 and output from the output terminal 7.

Such a multiplication operation is performed during one cycle of the clock signal for delimiting one word, but as described above, the up / down counter circuit 5 up / down-counts the clock signal. , The serial data SK changes as ...... SKm-1SKmSKm + 1 ..., and such serial data SK
Since the above multiplication operation is performed for each change of the above, that is, for each cycle of the clock signal for delimiting one word, the addition output S7m is :: S7m-1 = PDn-1 × SKm-1 S7m = PDn × SKm S7m + 1 = PDn + 1 × SKm + 1 S7m + 2 = PDn + 2 × SKm + 2 ::

Then, the addition output ... S7m-1, S7m, S7m + 1 ... is L
Shifted to the SB side by one bit ... * S7m-1, * S7m,
* S7m + 1 ... Is converted to serial data and output from output terminal 7 sequentially.

Here, the up / down counter circuit 5 is loaded with hex (FF) [111 ... 11] when the meeting is ON, and down counts the clock signal, and the counter output is [111 ... 10] [111 …… 01] :: Since it changes like this, the above addition output …… S7m-1, S7m,
S7m + 1 ... becomes gradually smaller, and when the counter output becomes [000 ... 00], the addition output becomes [0].

Therefore, these added outputs were shifted to the LSB side ...
… * S7m-1, * S7m, * S7m + 1 ... gradually decrease and eventually become [0].

When the meeting is off, the up / down counter circuit 5 is loaded with zero zero [000 ... 00], and the clock signal is up counted, and the counter output is [000 ... 01] [000 ... 00]. ... 10] :: Since it changes like this, in the same way, the addition output above ...
S7m-1, S7m, S7m + 1 ... gradually increase.

Therefore, these added outputs were shifted to the LSB side ...
… ＊ S7m-1, ＊ S7m, ＊ S7m + 1 …… will gradually increase.

Reference numeral 16 is a timing generation circuit for controlling the operation timing of the up / down counter circuit 5, the multiplexer circuit 13, the second latch circuit 14 and the parallel-serial converter 15.

Next, the above operation will be described based on a specific example.

 When the meeting is ON, the up / down counter circuit 5 is loaded with hexa (FF) [11111111] (hereinafter, this FF is referred to as K).

At this time, the parallel data [D15D14 ... D1D0] latched by the first latch circuit 3 is PD0.

K is parallel-serial converted into serial data SK, which is sequentially shifted from the LSB side and input to the gate circuit 10.

First, take the gate of LSB of K and PD0, and add the 17-bit adder.
It goes through 11 and is shifted one bit by the shift circuit 12,
It is latched by the second latch circuit 14.

This latched data and the next bit 7SB of the LSB of K
The gate of PD0 and the gate of PD0 are added by the adder 11 and are shifted by one bit to be latched in the second latch circuit 14.

In this way, the MSB of K and the gate of PD0 are sequentially added between the gates, shifted by one bit, and then latched.
Finally, parallel-serial conversion is performed and output.

If this output is PD0 ', PD0' = PD0 x [01111111] = PD0 x 0.996.

Next, the content of the up / down counter circuit 5 that counts down one clock signal for delimiting one word becomes [11111110], and when the above operation is performed on the parallel data PD1 next to PD0, PD1 ' = PD1 × [01111110] = PD1 × 0.992 ... Output is obtained.

In this way, the up / down counter circuit 5 counts down by one count for each clock signal for delimiting one word, that is, for each word of parallel data, and the above operation is repeated, and finally, At [00000000], the output is PDk ′ = PDk × [00000000] = PDk × 0 = 0.

When the meeting is off, the up / down counter circuit 5 is loaded with zero zero [00000000].

Contrary to the case where the meeting is ON, the up / down counter circuit 5 is provided for each clock signal for delimiting one word, that is, for each word of parallel data.
Counts up one count at a time, and repeats the above operation, and when it finally becomes [11111111], its output becomes PDk '= PDk × [01111111] = PDk × 0.996 ....

[Effect of the Invention] Instead of forcibly setting the digital data to [0] as in the prior art, the digital data and the counter output of the up / down counter means are multiplied and output, and / By counting up the down counter means, the multiplication output of the digital data and the counter output is increased, and by counting down the up / down counter means, the multiplication output of the digital data and the counter output. By reducing the audio signal output, the audio signal output is gradually increased or decreased to perform the muting operation, so that the noise during the muting operation can be removed. In particular, in the embodiment shown in FIG. ,
Since it is composed of the adder 11 and the shift circuit 12, there is an effect that an expensive multiplier is unnecessary.

[Brief description of drawings]

FIG. 1 is a diagram showing the configuration of a miuteing circuit of the present invention,
FIG. 2 is a diagram showing the construction of another embodiment of the present invention, and FIG. 3 is a diagram showing a conventional muting system. 1 ... input terminal, 2 ... serial-parallel data converter, 3 ... first latch circuit, 4 ... multiplier, 5 ... up / down counter circuit, 6 ... parallel-serial data converter, 7 ... Output terminal, 8 ... Control circuit, 9 ... Signal path, 10 ... Gate circuit, 11 ... Adder,
12 …… Shift circuit, 13 …… Multiplexer circuit, 14 ……
Second latch circuit, 15 ... Parallel-serial data converter, 16 ... Timing generation circuit.

Claims (1)

[Scope of utility model registration request] 1. In an audio device in which digital data corresponding to an audio signal is given as n-bit serial digital data [Dn-1Dn-2 ... D1D0], a k-bit counter output [Kn-1Kn-2 ... K1K0 ] Up / down counter means for outputting the digital data and a multiplying means for multiplying and outputting the digital data and the counter output are provided. By up-counting the up / down counter means, the digital data and the By increasing the multiplication output with the counter output and down-counting the up / down counter means, the multiplication output with the digital data and the counter output is decreased, and the miuteing circuit using these multiplication outputs as output signals The above-mentioned multiplication means is composed of the following constituent elements. Circuit. (A) Serial-converting serial digital data corresponding to the audio signal into parallel digital data
Parallel data conversion circuit (3). (B) A serial-parallel data conversion circuit (15) for converting the counter output (parallel digital data) of the up / down counter means into serial digital data. (C) A gate circuit (10) for multiplying parallel digital data corresponding to the audio signal by serial digital data corresponding to the counter output. (D) An adder circuit (11) for adding the gate output of the gate circuit (10) and the output of the shift circuit (12). (E) A shift circuit (12) for shifting the output of the adder circuit (11) by 1 bit to the LSB side.