JP2003243990A - Apparatus and method for processing digital signal - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To directly output an input digital signal of a plurality of bit lengths in order to prevent error signals due to quantization, when the gain becomes 1.0 or 0.0 in performing arithmetic processing for varying the level of the ΔΣ- modulated digital signals of a plurality of bit lengths. <P>SOLUTION: A signal processing part 4 returns a bit length expanded in the low order direction of an arithmetic output signal in a period while arithmetic by an arithmetic processing part 3 is performed to a plurality of bit lengths (m) before arithmetic processing by using n (n is an integer ≥1) delaying devices and a quantization means. When arithmetic processing by the arithmetic processing part 3 is finished, the signal processing part 4 makes the input digital signal pass through. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing apparatus and a digital signal processing method, for example, a digital signal processing apparatus and a digital signal for performing arithmetic processing and signal processing on a ΔΣ-modulated digital audio signal having a plurality of bit lengths. Regarding processing method.

[0002]

2. Description of the Related Art High speed 1 modulated by delta sigma (ΔΣ)
The bit audio signal has a very high sampling frequency and a short data word length (for example, sampling frequency) compared to the data format used for conventional digital audio (for example, sampling frequency 44.1 kHz, data word length 16 bits). Is 64 times as large as 44.1 kHz and has a data word length of 1 bit), and features a wide transmittable frequency band. Further, even if it is a 1-bit signal by ΔΣ modulation, it is possible to secure a high dynamic range in an audio band which is a low band with respect to an oversampling frequency of 64 times. Utilizing this feature, it can be applied to high-quality sound recorders and data transmission.

The delta-sigma modulation circuit itself is not a new technology, its circuit configuration is suitable for integration into an IC, and the accuracy of AD conversion can be obtained relatively easily. Circuit.

The ΔΣ-modulated signal can be returned to an analog audio signal by passing through a simple analog low-pass filter.

[0005]

By the way, the ΔΣ-modulated signal is usually converted into a 1-bit signal, but the signal is not necessarily limited to 1-bit, and it is possible to obtain more S It is possible to realize the characteristics of high / N. Since some A / D converters generate an audio signal having a ΔΣ-modulated high-speed sampling multiple bits, there is a demand for an apparatus capable of directly recording this signal.

On the other hand, in an apparatus for recording / reproducing an audio signal, a fade process is applied to the signal in order to prevent noise from being generated at the start and stop.
In the fade process, the bit length of the input signal is expanded because the multiplication process of the input signal by the level coefficient is performed. Δ
In the case of a Σ-modulated signal having a plurality of bit lengths, in order to restore the expanded bit length to the original bit length, it is necessary to convert the bit length by a ΔΣ modulator or the like. Then, the gain becomes 1.0 or 0.0, and the processing is continued even if the bit length expansion due to the fade processing disappears, and the original signal is affected. Therefore, when the gain becomes 1.0 or 0.0, this Δ
It is necessary to bypass the Σ modulator or the like and perform switching processing so that the input signal is directly output.

Regarding the switching method in the case where the 1-bit audio signal is the input signal, the applicant of the present invention discloses in Japanese Patent Laid-Open No.
No. 307,452. This is a method for a 1-bit input signal, and does not support an input signal having a plurality of bit lengths. This does not solve the problem of preventing noise generated at the switching point when a signal having a plurality of bit lengths is directly switched.

The present invention has been made in view of the above circumstances, and when a gain is 1.0 or 0.0 when performing a calculation process for varying the level of a digital signal having a multiple bit length, the multiple bit length is used. It is an object of the present invention to provide a digital signal processing device and a digital signal processing method capable of directly outputting the input digital signal of (1) while preventing an error signal due to quantization.

[0009]

In order to solve the above-mentioned problems, a digital signal processing device according to the present invention performs arithmetic processing and signal processing on an input digital signal having a plurality of bit lengths m (m is an integer of 2 or more). In the digital signal processing device, the arithmetic processing means for performing arithmetic processing for varying the level of the input digital signal, and the bit expanded in the lower direction of the arithmetic output signal during the arithmetic processing by the arithmetic processing means. The length is returned to the multi-bit length m before the arithmetic processing by using n (n is an integer of 1 or more) delay units and the quantizing means, and when the arithmetic processing by the arithmetic processing means is finished, the input digital signal is Signal processing means for bypassing, and when the arithmetic processing by the arithmetic processing means ends, the signal processing means includes the delay device and the quantizing means. The zero error signal by have been quantized, bypassing the input digital signal.

With such a configuration, the digital signal processing apparatus according to the present invention can reduce the gain by the arithmetic processing means.
When it becomes 1.0 or 0.0, add a signal that does not cause noise to the sense of hearing to the input at an appropriate timing. by this,
Make all data values stored in multiple delay units the same. Therefore, the input digital signal can be bypassed without generating noise.
As a result, it becomes possible to record and reproduce the .DELTA..SIGMA.

One delay device of the signal processing means (n =
In the case of 1), if the configuration is such that the noise shaper returns to m bits, there is no need for control, that is, no offset signal is added, and if the input bit length becomes m bits, the input digital The signal can be bypassed.

If the number of delay devices is two (n = 2), the error signal values can all be made the same by adding an offset signal having a sufficiently small level. In this case, the signal in which the audio band component is sufficiently suppressed is an offset signal having a sufficiently low level.

The digital signal processing method according to the present invention comprises:
In order to solve the above-mentioned problems, in a digital signal processing method for performing arithmetic processing and signal processing on an input digital signal having a plurality of bit lengths m (m is an integer of 2 or more), arithmetic processing for varying the level of the input digital signal And a delay means and a quantizing means of n (n is an integer of 1 or more) bit lengths extended in the lower direction of the operation output signal during the operation processing by the operation processing step. And a signal processing step for returning the input digital signal to a through state when the arithmetic processing by the arithmetic processing step is completed, and the arithmetic processing by the arithmetic processing step is completed. Then,
The signal processing step controls the error signal by the quantization using the delay device and the quantizing means to pass the input digital signal.

The digital signal processing method according to the present invention comprises:
In order to solve the above-mentioned problems, an arithmetic process for varying the level of the input digital signal is performed on an input digital signal having a plurality of bit lengths m (m is an integer of 2 or more), and an arithmetic process is performed during the period when the arithmetic process is performed. The bit length expanded in the lower direction of the output signal is returned to the multi-bit length m before the arithmetic processing by using a plurality of n (n is an integer of 3 or more) delay units and the quantizing means, and the arithmetic processing by the arithmetic processing is performed. When completed, in the digital signal processing method for performing signal processing for passing the input digital signal through, the arithmetic processing step of performing the arithmetic processing includes a level coefficient changing step of gradually changing the level coefficient and a level coefficient to a predetermined value. A signal processing step of performing the signal processing, wherein the signal processing step of performing the signal processing receives the determination result from the determination step. The offset signal adding step of generating a sufficiently small offset signal and adding it to the input digital signal and the past two samples of the quantization error signal due to the quantization are compared, and the difference values are substantially the same twice consecutively. The detection step of detecting a point, and the stop of the generation of the offset signal based on the result of the detection step, and then the transition of the three samples at substantially equal intervals, the quantization error signal of the three samples A first difference value between the sample and the succeeding sample is generated and added to the input digital signal, and a second difference value between the center sample and the preceding sample is generated in the next sampling period to generate the second difference value. And a difference value adding step of adding to the signal.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In this embodiment, Δ
A digital signal processing apparatus 1 having the configuration shown in FIG. 1, which performs arithmetic processing and signal processing on an input digital signal composed of m bits (m is an integer of 2 or more) generated by Σ modulation.

The digital signal processing apparatus 1 has an arithmetic processing unit 3 for performing arithmetic processing for varying the level of an m-bit input digital signal supplied from an input terminal 2, and a signal for an arithmetic processing output from the arithmetic processing unit 3. A signal processing unit 4 for performing processing is provided, and a signal processing output by the signal processing unit 4 is supplied to an external device connected to the output terminal 5.

Further, the digital signal processing apparatus 1 is provided with a key operation section 6 provided with a start key and a stop key which are operated by the user to perform a start operation and a stop operation, for example.
And a system controller 7 that generates a start command and a stop command corresponding to a key operation by a user using the key operation unit 6 and supplies the start command and the stop command to the arithmetic processing unit 3.

The arithmetic processing section 3 subjects the input digital signal to fade-in processing, fade-out processing or cross-fade processing.

The signal processing unit 4 uses the n delay units and the quantizing means to expand the bit length in the lower direction of the operation output signal while the operation is being performed by the operation processing unit 3 before the operation processing. When the arithmetic processing by the arithmetic processing unit 3 is completed, the input digital signal is passed through while returning to the plural bit length m.

In particular, when the arithmetic processing by the arithmetic processing unit 3 is completed, the signal processing unit 4 sets all the values of the quantization error signals stored in a plurality of n delay units to the same value, and the input digital signal To let through.

For this reason, the signal processing unit 4 includes an nth-order noise shaper 12 having the n delay devices and the quantizing means.
And a detection & control unit 13 for detecting the transition points of the error signal due to the quantization in the n-th order noise shaper 12 at substantially equal intervals and controlling the addition data generator 10 described later.
Then, when the calculation end by the calculation processing unit 3 is notified, an offset signal having a sufficiently small level with respect to the input digital signal is generated, and the detection & control unit 13 receives the detection result of detecting the transition point. And an addition data generator 10 that stops the generation of the offset signal, generates a first difference value, and generates a second difference value in the next sampling period, and the offset signal from the addition data generator 10. An adder 11 for adding the first difference value or the second difference value to the arithmetic processing output of the arithmetic processing unit 3.

First, the addition data generator 1 of the signal processing unit 4
When the arithmetic processing by the arithmetic processing unit 3 is completed, 0 generates an offset signal having a sufficiently small level and adds it to the input digital signal via the adder 11.

Next, when the detection & control unit 13 of the signal processing unit 4 detects the points at which the error signal due to the quantization in the nth-order noise shaper 12 makes a transition at substantially equal intervals, the addition data generator 10 causes The offset signal is stopped, and a first difference value is generated and added to the input digital signal via the adder 11, and a second difference value is generated at the next sampling period to be added via the adder 11. Add to the input digital signal.

As a result, the digital signal processing device 1 shown in FIG. 1 detects and controls the timing at which the quantization error data in the nth-order noise shaper 12 transits at substantially equal intervals over three consecutive samples. Detected at 13,
The sum data generator 10 generates a first difference value between the center sample and the subsequent sample and a second difference value between the center sample and the previous sample continuously over two samples from the detection point. However, since it is alternately added to the input once via the adder 11, it is possible to make all the values stored in the n-stage delay devices the same value.
As a result, the m-bit input data to the noise shaper 12 can be directly obtained as output data at the output terminal 5, and the noise shaper can be bypassed.

Next, a specific example of the digital signal processing device 1 will be described with reference to FIGS. An example of this is
The digital signal processing device 1 is applied to a ΔΣ audio data recording system 20 that starts recording of 4-bit audio data obtained by ΔΣ modulation after a fade-in process in response to a user's start command.

ΔΣ audio data recording system 20
Is an A / D converter 22 that performs a ΔΣ modulation process on the analog audio signal 100 supplied from the input terminal 21 to generate a 4-bit ΔΣ audio signal 101, and a 4-bit ΔΣ audio from the A / D converter 22. Digital signal processing apparatus 1 for performing fade-in processing and signal processing on signal 101, and digital signal processing apparatus 1
4-bit ΔΣ audio signal output from
6 and a signal recording device 50 for recording 6.

This ΔΣ audio data recording system 2
The arithmetic processing unit 3 constituting the digital signal processing device 1 in 0 performs the fade-in process as described above, and the level coefficient generator 32 which receives the command from the system controller 7 causes the level coefficient 102 From 0.0
The value is changed to 1.0, the 4-bit ΔΣ audio signal 101 is multiplied through the multiplier 31, and the level is changed. 4 bits during this fade-in process Δ
The Σ audio signal 101 becomes the digital signal 103 whose bit length is expanded to the lower order.

The signal processing unit 4 in the digital signal processing device 1 restores the original bit length of the digital signal 103 whose bit length is expanded to the lower 4 bits by the arithmetic processing relating to the fade-in processing in the arithmetic processing unit 3. Signal processing for. Therefore, the signal processing unit 4 includes the addition data generator 11, the adder 11, and the third-order noise shaper 12.
And a detection & control unit 13 for controlling the internal state of the third-order noise shaper 12.

The third-order noise shaper 12 includes an adder 1
1 addition output and multiplication outputs from the three coefficient multipliers described later
Adder 41 for adding and and the addition output of this adder 41
A 4-bit quantizer 42 that quantizes
The quantization error data, which is the difference between the input and output of the quantizer 42,
Calculator 43 for calculating data 105 and quantization error data
Three delay units 44 for performing three-stage delay processing on 105
₁, 44_TwoAnd 44_ThreeAnd these three delay devices 44₁，
44_TwoAnd 44_ThreeThe value of each stage by K1, K2
And the multiplication output multiplied by K3 is supplied to the adder 41.
Coefficient multiplier 45 ₁, 45_TwoAnd 45_ThreeWith. here
And the coefficient multiplier 45₁, 45_TwoAnd 45 _ThreeThe coefficient value of is
K1 = -3, K2 = 3, K3 = -1, respectively.
Than (1-z^-1)^ThreeThe characteristics of are realized.

The signal recording device 50 outputs the 4-bit ΔΣ audio signal output 106 output from the digital signal processing device 1 to, for example, a tape-shaped recording medium, a disk-shaped recording medium such as a hard disk, an optical disk, a magneto-optical disk, or the like. It is recorded in a semiconductor memory or the like.

Next, the operation of the ΔΣ audio data recording system 20 will be described with reference to the timing chart of FIG. First, when the user presses the start key in the key operation unit 6, the system controller 7 generates a start control signal (start command signal) and supplies it to the level coefficient generator 32 of the arithmetic processing unit 3.

The level coefficient generator 32 of the arithmetic processing unit 3 is
Upon receiving the start command signal from the system controller 7, the level coefficient 102 is gradually increased from 0.0 to 1.0,
Performs fade-in processing. At this time, the level coefficient 102
Is multiplied by the 4-bit ΔΣ audio signal 101 from the A / D converter 22, the bit length of the input word length to the noise shaper 12 in the signal processing unit 4 is expanded.

[0033] Therefore, the noise shaper 12, 4 quantization error data 105 in bit quantizer 42, a delay unit ₄₄ 1 of the three-stage, 44 ₂ and 44 ₃ by the delayed coefficient multiplier values in each stage 45 ₁ , 45 ₂ and 45 ₃ multiply K1, K2 and K3, respectively, and feed back to the input via the adder 41, and return to 4 bits before the arithmetic processing.

When the level coefficient 102 reaches 1.0, the bit length is not expanded in the arithmetic processing unit 3 and the 4-bit length A / D converter output signal (4-bit ΔΣ audio signal) 101 is directly converted into the noise shaper. 12 will be added. However, noise shaper 12 3
One in the delay unit 44 _1, 44 ₂ and 44 _3, hitherto quantized error data are accumulated, this component is circulated feedback loop, influences the output data. Therefore, even if the input to the noise shaper 12 is 4 bits, it does not match the output 4 bit data.

Therefore, when the addition data generator 10 of the signal processing device 4 receives a signal from the level coefficient generator 32 of the arithmetic processing section 3 indicating that the level coefficient 102 has reached 1.0 and the fade-in processing has been completed, Noise shaper 12
An offset signal having a sufficiently small value is generated as the addition data 104 with respect to the 4-bit ΔΣ audio signal 101 toward the input signal 101, and the addition data 104 corresponding to the offset signal is added to the input signal 101. This prevents the output from forming a fixed pattern.

Thereafter, the detection & control unit 13 of the signal processing unit 4
Is the quantization error data 105 and the delay devices 44 ₁ , 44.
From the output of the ₂ and 44 _3, compares the quantization error data value over the last two samples, the difference value is detected a point substantially coincident successively twice. And the detection & control unit 1
3 detects an almost coincident point of the difference values twice consecutively, and outputs a signal indicating the detection, to the addition data generator 10
Send to.

Then, the addition data generator 10 of the signal processing unit 4 stops the offset signal which has been added to the input signal through the adder 11 so far, and also the quantization error of 3 samples at the detection point. Of the data, first, the data of the first difference value with respect to the latter sample with respect to the center sample is generated, and this is added to the input signal via the adder 11. Then, in the next sampling period, data of the second difference value between the central sample and the previous sample is generated, and this is added to the input signal via the adder 11.
After that, the addition data generator 10 stops the output.

[0038] By the signal processing unit 4 performs the above processing, the delay unit 44 1 of the _three-stage, 44 ₂ and the values are stored in the 44 ₃ All become the same value, 4 bits to the result noise shaper 12 The ΔΣ audio signal 101 is obtained as it is as an output, and the noise shaper 12 is bypassed.

Next, a specific example of the digital signal processing method performed inside the digital signal processing device 1 will be described. A specific example of this digital signal processing method includes an arithmetic processing method performed by the arithmetic processing unit 3 of the digital signal processing apparatus 1 and a signal processing method performed by the signal processing unit 4.

First, the calculation processing method will be described with reference to the processing procedure of FIG. In addition, here, the key operation unit 6
A process procedure relating to a fade-in process started when a start key in the inside is pressed by a user and a fade-out process started when a stop key is pressed will be described.

In step S1, the system controller 7
It is checked whether or not the start command signal is received from, and if it is determined that the start command signal is received, the process proceeds to step S2 and the level coefficient
02 is gradually increased from 0.0 to 1.0, and fade-in processing is performed.

Then, in step S3, the level coefficient is 1.
When it is determined that the level coefficient has reached 0, the process proceeds to step S4, the addition data generator 10 is notified that the level coefficient has reached 1.0, and 1.0 is continued. This level coefficient 1.0 is the step S
It continues until it judges that the stop command signal was received from the system controller in 5.

If it is determined in step S5 that the stop command signal has been received, the process proceeds to step S6 to set the level coefficient.
Fade out from 1.0 to 0.0.

When it is determined in step S7 that the level coefficient has reached 0.0, the process proceeds to step S8 and the addition data generator 10 is informed that the level coefficient has reached 0.0.

Next, the signal processing method will be described with reference to the processing procedure of FIG. First, in step S11, it is checked whether the addition data generator 10 has received the notification that the level coefficient has reached 1.0. When the notification is not received, that is, when the level coefficient has not reached 1.0, a process of returning the bit length expanded in the lower direction by the fade-in process to 4 bits before the arithmetic process is performed in step S12.

On the other hand, if it is determined in step S11 that the notification has been received, the process proceeds to step S13, in which the addition data generator 10 is caused to generate an offset signal that is sufficiently smaller than the input signal, and the addition signal is applied to the input signal via the adder 11. To add.

[0047] Then, from the output of the quantization error data 105 and the delay unit ₄₄ 1, 44 ₂ and 44 ₃ at step S14, and compares the quantization error data value over the last two samples, the continuous and the difference value is 2 times Then, it is checked whether or not a point that substantially coincides is detected. Here, if it is determined that the point where the difference values substantially match twice consecutively is detected, the addition data generator 10 is caused to stop generating the offset signal in step S15, and then the detection is performed in step S16. Of the three samples of quantization error data at points,
Data of a first difference value between the central sample and the subsequent sample is generated and added to the input signal via the adder 11.

If it is determined in step S17 that the next sampling period has come, the process proceeds to step S18, in which the addition data generator 10 is caused to generate the data of the second difference value between the central sample and the previous sample, and this is generated. Adder 1
Add to input signal via 1. After that, step S
At 19, the output from the addition data generator 10 is stopped.

Next, the operation of the signal processing section 4 will be described in detail with reference to FIGS. 6 and 7. FIG. 6 shows the signal processing unit 4.
FIG. 7 is a diagram showing changes in internal quantization error data 105 and addition data 104 with respect to time. FIG. 7 is a diagram in which the internal state of the noise shaper 12 at each time in FIG. 6 is written by paying attention to the quantization error data. In the figure, the quantization error data over the past two samples includes the quantization error data 105 and the delay units 44 ₁ and 44 in the first and second stages.
It can be known by the value of the output of ₂ .

Now, as shown in (1) of FIG. 7, the quantization error data over the past two samples at time t3 is A,
If the difference values (B−A) and (C−B) between these data are B and C, as shown in FIG. In the case of (CB), the detection & control unit 13 causes the addition data generator 10 to operate as shown in FIG.
As shown in (2), the difference value data (CB) between the central sample value B and the subsequent sample value C is generated as the addition data 104, and this is the noise shaper 1.
2 is added to the input signal. As a result, FIG. 7 (2)
Further, as shown in FIG. 6A, the current quantization error data 105 is B, which is the same value as the value of the delay unit 441 at the _first stage from C- (CB).

As a result, in the next sampling period t4, as shown in FIG.
4 _1, 44 ₂ of the data value is B in the same value. Here the coefficient multipliers 45 ₁ and 45 ₂ of the coefficients K1 and K2, respectively K1 = -3, for K2 = 3, these by a feedback component 3B -3B is canceled, becomes zero.
Therefore, since K3 = -1, the feedback data is
Only feedback component -A by 3-stage delay 44 ₃ data will be is added to the input, the quantization error data 105 becomes A. At this time, as shown in FIG. 6 (2), the addition data generator 10 adds the difference data (AB) between the central sample value B and the previous sample value A detected in the previous sampling cycle to the addition data. It is generated as 104, and this is added to the input signal to the noise shaper 12. As a result, FIG. 7 (4) and FIG. 6 (1)
As shown in FIG.
From (AB), the value of B is the same as the value of the delay device 44 _{1 at} the first stage.

As a result, in the next sampling period t5, as shown in FIG. 7 (5), the three-stage delay devices 44 ₁ , 4 are provided.
All 4 ₂ and 44 ₃ have the same value B. After that, the data B of the delay device is directly used as the quantization error data 10
Since it is fed back as 5, the value of the delay device always circulates the constant value B thereafter.

In this way, the signal processing unit 4 detects the timing at which the quantized error data 105 transits at approximately equal intervals over three consecutive samples by the detection & control unit 13, and continuously detects 2 points from the detection point. A first difference value between the center sample and the rear sample and a second difference value between the center sample and the previous sample are generated by the addition data generator 10 across the samples, and the adder 11
The by adding the input alternately once through, it can be achieved be the delay unit 44 _1, 44 _2, 44 identical values all are stored value to ₃ of three stages. As a result, 4-bit input data to the noise shaper 12 is always obtained as it is as output data. That is, it becomes feasible to bypass the noise shaper 12 so as to pass through the input data.

By this processing, the difference data (CB) and (A
-B) is added, but since the difference values (B-A) and (C-B) between the respective data have detected points that are almost coincident with each other, the difference between A, B, and C is detected. In between, (B-
As a result, the data added from the input becomes (C−B) and (A−B) ≅− (C−B), and the data with almost the same amplitude and the opposite sign is 1 The signals are adjacent for each sample. Therefore, the low-frequency components (audio band components) cancel each other out and are sufficiently attenuated. Therefore, this signal has almost no effect on the output. In addition, the offset signal is added by the addition data generator 10 until the detection & control unit 13 detects a difference match. However, since this signal is also a sufficiently small value, there is no influence on the output by this signal. rare.

The quantization error data transits within the range of the least significant 1 bit or less of the input data. However, when calculating the difference value, the maximum value may be calculated as circulating in connection with the minimum value. For example, assuming that the least significant 1 bit is 1.0, in the case of rounding, the quantization error data transits between -0.5 and 0.5, but in this case, 0.5 is connected to -0.5, and for example 0.4 and -0.4 The difference may be calculated as 0.2.

As described above, the ΔΣ audio data recording system 20 having the configuration shown in FIG. 2 bypasses the noise shaper 12 without generating noise in the output, and
Direct output of bit A / D converter 22
It becomes feasible to record in the bit recording / reproducing device 50.

Here, when the start key is pressed by the key operation unit 6 and the level coefficient 102 becomes 1.0, A
Although the case where the / D converter output signal is directly output has been shown, even when the stop key is pressed in the key operation unit 6, the same processing is performed after the level coefficient 102 becomes 0.0. It is possible to output 0 data directly. Steps S5 to S8 of the arithmetic processing method whose processing procedure is shown in FIG.
Step S11 of the signal processing method whose processing procedure is shown in FIG.
This is possible by applying the corresponding part of step S19.

Further, FIG. 2 shows a digital signal processing device 1
As an application example of the above, a system in which the ΔΣ audio data output from the digital signal processing device 1 is recorded by the signal recording device 50 has been described. However, a system for transmitting ΔΣ audio data having a plurality of bit lengths output from the digital signal processing device 1 Needless to say, can be cited as an application example.

Further, in the digital signal processing device 1, the arithmetic processing unit 3 has been described as a row of fade-in processing and fade-out processing, but cross-fade processing may be performed, for example. In this case, when the level coefficient of the crossfade becomes 1.0 or 0.0, the same process as described above is performed, so that the crossfaded signal having a plurality of bit lengths can be directly output. Furthermore, by using the mute pattern signal as one of the signals to be cross-faded, switching to the mute pattern signal may be performed.

As the noise shaper, a third-order noise shaper using 3 (n = 3) delay devices has been taken as an example. However, if there is one or more delay devices, 2, 4, 5, 6 , 7
・ ・ ・ You may also use individual pieces.

For example, a first-order noise shaper having one delay device (n = 1) may be used. In this case, the noise shaper may be configured to return to m bits, without any control, that is, the offset signal. If the bit length of the input becomes m bits without adding, the input digital signal can be bypassed.

Further, assuming that there are two delay devices (n = 2),
By adding an offset signal having a sufficiently small level, all the error signal values can be made the same value. In this case, the signal in which the audio band component is sufficiently suppressed is an offset signal having a sufficiently low level.

Although the A / D converter 22 has been described as generating 4-bit ΔΣ audio data, a plurality of bits of 2 bits or more, for example, 3, 5, 6, are used.
Of course, a plurality of bit lengths such as 7, 8, ... May be generated.

In the present invention, the m-bit input digital signal is a signal generated by ΔΣ modulation, but it is an m-bit signal obtained by a modulation method such as PCM, PNM, PWM, PPM, PAM. Of course it is good.

[0065]

According to the digital signal processing device of the present invention, when the gain becomes 1.0 or 0.0 when performing the arithmetic processing for varying the level of the digital signal having a plurality of bit lengths, the plurality of bit lengths having a plurality of bit lengths are obtained. An input digital signal can be directly output while preventing an error signal due to quantization.

According to the digital signal processing method of the present invention, when the gain becomes 1.0 or 0.0 when performing the arithmetic processing for varying the level of the digital signal of the plural bit length, the input digital of the plural bit length is obtained. The signal can be directly output while preventing an error signal due to quantization.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital signal processing device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a ΔΣ audio data recording system to which a specific example of the digital signal processing device is applied.

FIG. 3 is a timing chart for explaining the operation of the ΔΣ audio data recording system.

FIG. 4 is a flowchart showing a processing procedure of an arithmetic processing method of a digital signal processing method according to the present invention.

FIG. 5 is a flowchart showing a processing procedure of a signal processing method of the digital signal processing method.

FIG. 6 is a diagram showing changes in quantization error data inside a signal processing unit and addition data with respect to time.

FIG. 7 is a diagram in which the internal state of the noise shaper at each time point in FIG. 6 is written by focusing on the quantization error data.

[Explanation of symbols]

1 digital signal processing device, 3 arithmetic processing unit, 4 signal processing unit, 6 key operating unit, 7 system controller, 10 addition data generator, 11 adder, 12 n
Next noise shaper, 13 Detection & control unit

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Claims (18)

[Claims] 1. A digital signal processing device for performing arithmetic processing and signal processing on an input digital signal having a plurality of bit lengths m (m is an integer of 2 or more), the arithmetic processing for varying the level of the input digital signal. A processing means, and n (n is an integer of 1 or more) delay units and quantizing means for expanding the bit length in the lower direction of the operation output signal while the operation processing by the operation processing means is being performed. And a signal processing means for returning the input digital signal to a through state when the arithmetic processing by the arithmetic processing means is completed, and returning to the plural-bit length m before the arithmetic processing, and when the arithmetic processing by the arithmetic processing means is completed, The signal processing means controls an error signal by quantization using the delay device and the quantization means, and allows the input digital signal to pass through. Digital signal processing device. 2. The signal processing means sets all error signal values due to the quantization stored in n delay devices which are integers of 2 or more to the same value.
The described digital signal processing device. 3. The signal processing means, from the end of the arithmetic processing by the arithmetic processing means, until all the error signal values due to the quantization stored in the n delay devices become the same value. The digital signal processing apparatus according to claim 2, wherein an offset signal having a sufficiently small level is added to the input digital signal in between. 4. The signal processing means outputs a signal in which a component of an audio band is sufficiently suppressed in order to make all erroneous calculation signal values due to the quantization stored in the n delay devices equal to each other. 3. The digital signal processing device according to claim 2, wherein the digital signal processing device performs processing that is added from an input or is equivalent to that added. 5. The signal processing means sets all error signal values due to the quantization stored in n delay devices, which are integers of 3 or more, to the same value.
The described digital signal processing device. 6. The signal processing means, after the arithmetic processing by the arithmetic processing means is completed, all the error signal values due to the quantization stored in the n delay devices which are integers of 3 or more. 6. The digital signal processing apparatus according to claim 5, wherein an offset signal having a sufficiently small level is added to the input digital signal until the input signal has the same value. 7. The component of the audio band is sufficient so that the signal processing means makes all the miscalculated signal values due to the quantization stored in the n delay devices which are integers of 3 or more, equal to each other. Or add a suppressed signal from the input,
The digital signal processing apparatus according to claim 5, wherein processing equivalent to addition is performed. 8. The signal processing means adds, to the input, a signal composed of at least two samples whose absolute values are substantially the same and whose opposite signs are continuous, as a signal in which an audio band component is sufficiently suppressed, or added. 8. The digital signal processing device according to claim 7, wherein the digital signal processing device performs processing equivalent to that. 9. The signal processing means adds, to the input, a signal composed of at least two samples whose absolute values are substantially the same and whose opposite signs are continuous as a signal in which an audio band component is sufficiently suppressed. As a timing point for performing a process equivalent to that, detecting a point at which the error signal due to the quantization transitions at substantially equal intervals over three consecutive samples or more after the arithmetic process by the arithmetic processing means is completed. 9. The digital signal processing device according to claim 8, wherein. 10. The signal processing means includes the delay unit of 3
, The absolute value is substantially the same value, and the signal is composed of two consecutive samples of opposite signs, and after the arithmetic processing by the arithmetic processing means is completed, the error signal due to the quantization is substantially equal over three samples. Of the three sample quantization error signals at the detected points that transition at intervals,
10. The digital signal processing apparatus according to claim 9, wherein the first difference value between the center sample and the rear sample is used first, and then the second difference value between the center sample and the previous sample is used. . 11. Detecting means for detecting points at which the error signal resulting from the quantization transitions at substantially equal intervals over three consecutive samples, and a level for the input digital signal when the completion of the operation by the operating means is notified. Generates a sufficiently small offset signal, and when the detection result that the transition point is detected by the detection means is received, the generation of the offset signal is stopped and the first difference value is generated, and the next sampling cycle is generated. 11. The digital signal processing device according to claim 10, further comprising: addition data generating means for generating the second difference value. 12. The signal processing means includes a third-order noise shaping means including three delay devices and a quantizing means, and a point that the error signal due to the quantizing transitions at substantially equal intervals over three consecutive samples. Detecting means for detecting, an offset signal having a sufficiently small level with respect to the input digital signal, and a sample after the middle sample of the quantization error signals of 3 samples at the points of transition at substantially equal intervals over the 3 samples. And a second difference value for generating a second difference value between the center sample and the previous sample, and the addition data generating means notifies the addition data generating means of the calculation end by the calculation means. According to the detection result of the transition point by the detection means, the generation of the offset signal After stopping, the first difference value is generated, the second difference value is generated in the next sampling period, and the values stored in the three delay devices are all set to the same value. 6. The digital signal processing device according to claim 5, wherein an error signal resulting from the quantization is controlled. 13. The digital signal processing apparatus according to claim 1, wherein the arithmetic processing means performs a fade-in process, a fade-out process or a cross-fade process on the input digital signal. 14. A multi-bit length m (m is an integer of 2 or more)
In a digital signal processing method for performing an arithmetic processing and a signal processing on an input digital signal, the arithmetic processing step of performing an arithmetic processing for varying the level of the input digital signal, and a period during which the arithmetic processing by the arithmetic processing step is performed. The bit length expanded in the lower direction of the operation output signal is returned to the multiple bit length m before the operation processing by using n (n is an integer of 1 or more) delay units and the quantizing means, and the operation by the operation processing step is performed. And a signal processing step of passing the input digital signal through when the processing is completed. When the arithmetic processing by the arithmetic processing step is completed, the signal processing step is performed by quantization using the delay device and the quantizing means. A digital signal processing method characterized by controlling an error signal and allowing the input digital signal to pass through. 15. The signal processing step according to claim 14, wherein all the error signal values due to the quantization stored in the n delay devices which are integers of 2 or more are set to the same value. Digital signal processing method. 16. The signal processing step, from the end of the arithmetic processing by the arithmetic processing step until all the error signal values due to the quantization stored in the n delay devices are made the same value. 16. The digital signal processing method according to claim 15, wherein an offset signal having a sufficiently small level is added to the input digital signal in between. 17. The signal processing step, in order to make all erroneous calculation signal values due to the quantization stored in the n delay units the same, outputs a signal in which an audio band component is sufficiently suppressed. 16. The digital signal processing method according to claim 15, wherein the processing is equivalent to the addition from the input or the addition. 18. A multi-bit length m (m is an integer of 2 or more)
To the input digital signal consisting of the following: arithmetic processing for varying the level of the input digital signal, and the bit length extended in the lower direction of the arithmetic output signal during the arithmetic processing is n (n is an integer of 3 or more) In the digital signal processing method, which uses a plurality of delay devices and quantizing means to restore the bit length m before the arithmetic processing, and performs signal processing for passing the input digital signal through when the arithmetic processing by the arithmetic processing is completed, The arithmetic processing step of performing arithmetic processing includes a level coefficient changing step of gradually changing the level coefficient and a determining step of determining whether or not the level coefficient reaches a predetermined value, and the signal processing step of performing the signal processing. Receives the judgment result from the judgment step, generates an offset signal sufficiently smaller than the input digital signal, and And an offset signal adding step of adding to the above, a detecting step of performing a comparison between the past two samples of the quantization error signal by the quantization, and detecting a point where the difference values are substantially coincident with each other twice, and a result of the detecting step. Of the quantization error signal of 3 samples at the point where the transition of the offset signal is stopped based on A difference value adding step of generating and adding to the input digital signal and generating a second difference value between the central sample and the previous sample in the next sampling period and adding to the input digital signal. A characteristic digital signal processing method.