JP2637768B2 - Multitrack digital magnetic recording device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a multi-track digital magnetic recording apparatus for recording data on a magnetic recording medium having a plurality of tracks in a digital recording / reproducing system, in units of M-bit data words. It is about.

<Prior art> In recent years, analog signals such as voice have been converted to digital signals, and the digital signals have been modulated by a predetermined modulation method to generate self-clockable digital signals. Devices for recording on a medium are being put to practical use. When an analog signal is converted to a digital signal, a digital magnetic recording / reproducing apparatus that handles this signal requires a much wider band than a conventional analog magnetic recording / reproducing apparatus.

The multi-track digital magnetic recording / reproducing apparatus distributes a digital signal to a plurality of tracks to reduce the recording density per track. In multi-track digital magnetic recording, a digital signal is divided into a plurality of blocks, and a synchronizing signal is added to each of the blocks and recorded on a recording medium. FIG. 14 shows a signal format in general multi-track digital magnetic recording. In this signal format, one frame is composed of a frame synchronization signal, data, and parity. In the example of FIG. 14, the number of tracks is five.

FIG. 15 shows a configuration of a recording apparatus in a conventional multi-track digital magnetic recording / reproducing apparatus. The analog input signal is converted into a digital signal in the AD converter 1, a parity is generated in the recording signal processing circuit 2, and a synchronization signal is added. In this example, the code modulation circuit 3 performs time division processing to convert, for example, N-bit input data into an M-bit data word.

As shown in the timing chart of FIG. 16, the M-bit data word a converted by the code modulation circuit 3 is
The symbol clock b from the timing signal generation circuit 11 causes the M-bit registers 12-5, 12-
4,..., 12-1. Next, the data held in the M-bit registers 12-5, 12-4,..., 12-1 is converted into M-bit parallel-in / serial-out registers 13-5, 13- by the load signal c from the timing signal generation circuit 11.
4,..., 13-1. M-bit parallel-in / serial-out registers 13-5, 13-4, ..., 13-
Numeral 1 denotes magnetic heads 7-5, 7-4,... 7-1 corresponding to bit clocks d from the timing signal generating circuit 11, respectively.
Send data to Thus, recording is performed on the magnetic recording medium (not shown) in the format shown in FIG.

<Problems to be Solved by the Invention> In the conventional multi-track digital magnetic recording / reproducing apparatus, the data register and the parallel-in / serial-out register for latching the data after code modulation by the code modulation circuit 3 are all the same. Bit lengths are required by the same number as the number of tracks. Therefore, when the number of tracks in the multi-track is increased, the bit capacity of the data register is increased in proportion to the number of tracks, resulting in an increase in hardware cost.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a multi-track digital magnetic recording device capable of reducing the capacity of a register even when the number of tracks is large.

<Means for Solving the Problems> In order to achieve the above object, in a multi-track digital magnetic recording apparatus for recording a digital signal in units of M-bit data words on a magnetic recording medium having the number of tracks T, The number of bits M and the number of tracks T of the word are each divisible, and the bit length A is determined according to the minimum value (l _min , n _min ) of the set of integers (l, n) whose quotients are equal to each other and greater than 1. _i is an i-stage register that satisfies the following equation; data transfer means for sequentially transferring data other than the MSB among the data latched in the i-stage register to a next-stage register; Data recording means for writing the MSB of the data latched in the register to a predetermined track of the magnetic recording medium.

Where INT (X) is the largest integer not exceeding X,
i is an integer from 1 to T.

<Operation> In this equation, the value of INT ((i-1) / n _min ) increases by 1 every n _min . Therefore, l _min × INT ((i−
1) / n _min ) is increased by l _min every n _min . Therefore, the bit length Ai obtained by subtracting l _min × INT ((i−1) / n _min ) from the number of bits M decreases by l _min every time the register string increases by n _min . Here, l and n divide M and T, respectively, and their quotients are integers.
The shorter the bit length for each n _min only l _min, reduction of the register bit length between the tracks is completely regular. Also, l _min and n _min are the minimum values of integers that divide the number of bits M and the number of tracks T of the data word, and whose quotients are equal to each other and are integers greater than 1, so that i satisfies the above expression. In the register of the stage, the bit length of the register is reduced by the smallest amount for each of the smallest register columns. For this reason, the register bit length can be minimized among the registers in which the register bit length between the register strings is completely and regularly reduced.

<Embodiment> FIG. 1 shows the configuration of the first embodiment. In the figure, 1 is an AD converter, 2 is a recording signal processing circuit, 3 is a code modulation circuit, 4 is a timing signal generation circuit, 5-1, 5-2,.
5-10 is a data register, 6 is a selection circuit, 7-1, 7-2,
.., 7-10 are magnetic heads. In this first embodiment,
The bit length M of the data word is 10 bits, and the number of tracks T is
It is 10.

The analog input is converted into a digital signal in the AD conversion circuit 1, and the recording signal processing circuit 2 generates a parity word and adds a synchronization signal. The code modulation circuit 3 converts the 8-bit input data into a 10-bit data word and outputs it. Timing signal generation circuit 4
Outputs a symbol clock b for giving a data word transfer timing and a selection signal e for giving a data recording timing to a track.

10 data registers 5-1 with the same number as 10 tracks
5-2, ..., 5-10 are the bit length of each register is 10,9,
, 1, the bit length A _{i of} each register (i = 1, 2,
…, 10) Here, K is an integer.

According to the minimum values l _min , n _min of the integers l, n that satisfy Here, INT (X) is the largest integer not exceeding X.

Defined by The specific meaning of these equations (1) and (2) will be described later. In the 10-stage data registers 5-1, 5-2,..., 5-10, data other than the MSB of the data held by the upper register is sequentially transferred to the lower register in accordance with the symbol clock b. Is transferred to the selection circuit 6. The selection circuit 6 selectively transfers the data transferred from the data registers 5-1, 5-2,..., 5-10 to the magnetic heads 7-1, 7-2,. Forward. The magnetic heads 7-1, 7-2,..., 7-10 have ten tracks T1, T2,
…, Record data in T10 respectively.

The 10-bit data word output from the code modulation circuit 3 is first transferred to the data register 5-1, and the MSB of the data written to the data register 5-1 is selected by the selection circuit 6
Is recorded on the track T1 by the magnetic head 7-1.
At the same time, 9-bit data other than the MSB of the data register 5-1 is transferred to the register 5-2 at the next stage, and the MSB of the data written to the register 5-2 at the next timing is the previous recording position of the track T1. Is recorded in the position following the. Hereinafter, in a similar manner, data other than the MSB of the preceding register is transferred to the data register 5-3 and subsequent registers, and the MSB of each register is sequentially transferred to the track T1 by the magnetic head 7-1 via the selection circuit 6. Be recorded.

The code modulation circuit 3 outputs 10-bit data words one after another in response to the input of the symbol clock b. In the data registers 5-1, 5-2,..., 5-10, other than the MSB of the upper register Is transferred to the lower register, new data is further transferred from the upper register to the upper register. Therefore, data other than the MSB of the data register 5-1 is stored in the register 5-
The new data word is transferred to the data register 5-1 at the next timing after the data is transferred to the track 2 and the MSB is recorded on the track T1, and the MSB is recorded on the track T2 by the magnetic head 7-2. The data other than the MSB is transferred to the register 5-2.

FIG. 2 shows a signal timing chart. Record 10-bit word data "253H" on track T1,
When recording the word data "356H" on the track T2, first, the data "253H" is latched in the register 5-1, and its MSB "1H" is controlled by the selection circuit 6 in response to the selection signal e to control the magnetic head 7--1. 1 is recorded on the track T1. Thereafter, the 9-bit data “0” excluding the MSB of the register 5-1 is read.
When 53H "is transferred to the register 5-2, the register 5-1
Then, the word data "356H" is latched, and the MSB "1" of this data "356H" is recorded on the track T2. At the same time, the data “05” latched in the register 5-2.
The MSB “0” of 3H ”is recorded on the track T1. In the same manner, each time data other than the MSB is transferred from the register 5-2 to the register 5-3, the register 5-4, and The MSB is recorded on the track T1.In parallel with this, the word data “356” is delayed by one cycle of the symbol clock b.
H "is transferred to the register 5-1. Every time data other than the MSB is transferred from the register 5-1 to the register 5-2 and the register 5-3, the MSB of each register is recorded on the track T2.

FIG. 3 shows the format of the tape recorded on the magnetic tape. There is a one-bit delay between the tracks, and a 9-bit phase difference occurs between the track T1 and the track T10. However, for example, it is known as a unified format of a fixed head type digital audio tape. S-DAT uses 8/10 modulation and has a recording density of 64 KBP
Since I (0.317 μm / bit) and the pitch between tracks are 80 μm, the azimuth deviation θ generated by the method of the present invention
Is This is a negligible range in consideration of head mounting accuracy and the like.

Equations (1) and (2) above are used for the data registers 5-1 and 5-1.
The bit length of 5-2,... Is determined. Hereinafter, the meanings of the expressions (1) and (2) will be described with reference to specific examples.

Now, the number M of pits in the data word is 10, and the number T of tracks is
Is 10. In this case, equation (1) There are numerical values shown in Table 1 for integers l and n satisfying the following.

Therefore, the minimum values l _min and n _min of the integers l and n are 1 respectively.
It is. Using these l _min and n _min , the equation (2) _{A 4 = = M-3 =} 7 A 5 = = M-4 = 6 A 6 = = M-5 = 5 A 7 = = M-6 = 4 A 8 = = M-7 = 3 A 9 = = M −8 = 2 A ₁₀ == M−9 = 1 FIG. 4 shows the configuration of the data register in this case. The integer n is the number of tracks having the same register length, and the integer l is the amount of register bit reduction between tracks.

Now, assuming that the integers l and n take the value 2 which is not the minimum value, And the configuration of the register is as shown in FIG. When the integers l and n are set to a value of 5, The configuration of the register is as shown in FIG. In any case, the register length is larger only in the shaded portion than in the case where the minimum value 1 is taken as the integer l, n.
That is, since the number of bits M and the number of tracks T of the data word are fixed as a system, the bit length of the register can be reduced by making the bit configuration of the register close to a triangle as shown in FIG. it can.

FIG. 8 shows a second embodiment. This system has a data word bit number M of 10 and a track number T of 5
It is. In this case, the values of l and n satisfying the expression (1) are shown in Table 2.
As shown in (1), the register bit length between tracks is reduced by 2, and the number of tracks having the same register length is 1. FIG. 9 is a timing chart of the second embodiment. FIG. 10 shows a recording format of a magnetic tape.

FIG. 11 shows a third embodiment. This system has a data word bit number M of 10 and a track number T of 20.
It is. In this example, the values of l and n satisfying the expression (1) are as shown in Table 3, and the minimum values of l and n in these are 1,2.

Therefore, the amount of decrease in the register bit length between tracks is 1, and the number of tracks having the same register length is 2.
FIG. 12 shows a timing chart of the third embodiment, and FIG. 13 shows a recording format of a magnetic tape.

<Effects of the Invention> As described above, according to the multi-track digital magnetic recording apparatus of the present invention, the bit lengths of the data registers of the same number as the number of tracks are configured to be regularly reduced at a predetermined rate. , MS of each register
The system is equipped with a transfer unit that transfers the data excluding B to the next-stage register in order, and a recording unit that sequentially writes the MSB of each register to the track, so that the bit length required for the register can be minimized. Thus, hardware down-counting can be achieved.

[Brief description of the drawings]

FIGS. 1, 8, and 11 are block diagrams showing the configuration of an embodiment of the present invention, FIGS. 2, 9, and 12 are timing charts of the embodiment of the present invention, FIGS. 10 and 13 are diagrams showing the recording format of the magnetic tape of the embodiment of the present invention, FIGS. 4, 5 and 6 are diagrams for explaining the bit length of the register of the embodiment of the present invention, FIG. FIG. 14 is a diagram conceptually illustrating a bit length of a register according to an embodiment of the present invention. FIG. 14 is a diagram illustrating a recording format of a conventional magnetic tape. FIG. 15 is a block diagram illustrating a configuration of a conventional example. FIG. 16 is a diagram showing a timing chart of a conventional example. DESCRIPTION OF SYMBOLS 1 ... AD converter 2 ... Recording signal processing circuit 3 ... Code modulation circuit 4 ... Timing signal generation circuit 5 ... Data register 6 ... Selection circuit 7 ... Magnetic head 8,9 ... Data register

Claims (1)

(57) [Claims] In a multi-track digital magnetic recording apparatus for recording a digital signal in units of M-bit data words on a magnetic recording medium having a number of tracks of T, the number of bits M and the number of tracks T of the data word are each divisible. And the minimum value (l _min ,
n _min) bits long A _i in response to the a register of i stages satisfying the following formula, the data other than the MSB of the data latched in the register of the i-th stage, sequentially transferred to the next register A multi-track digital magnetic recording apparatus, comprising: data transfer means; and data recording means for writing the MSB of data latched in the i-th register to a predetermined track of the magnetic recording medium. Where INT (X) is the largest integer not exceeding X,
i is an integer from 1 to T.