JPH09246979A - Modulation method, modulation device, demodulation method and demodulation means for digital data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the absolute value of a cumulative added value and to prevent increase over the long period of time by adjusting the cumulative added value for respective synchronizing signals inserted to modulation signals in a fixed cycle. SOLUTION: A data conversion means 1 inputs the digital data of 8 bits, converts them to 16-bit digital data along 8-16 modulation specifications and inputs them to a serializing means 2. For the conversion data serialized in the means 2, in a cumulative added value measuring means 3 and a time division multiplex means 6, the serialized conversion data and the synchronizing signals outputted from a synchronizing signal switching means 5 in the fixed cycle are time division multiplexed and outputted as the modulation signals. In the meantime, by the cumulative added value of the serialized conversion data measured in the means 3, a conversion data code in the means 1 and the changeover of the plural kinds of the synchronizing signals in the means 5 are controlled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data modulator / demodulator capable of reducing an error rate even in a band-limited transmission line.

[0002]

2. Description of the Related Art From a CD-audio to a personal computer, which is used in a music CD (compact disc) and a CD-ROM (read only memory)-(Corona Publishing, edited by Mauri, P13-P15) E as shown in
Although there are FM (eight to four modulation) modulation systems and the like, considering an application that requires a large capacity such as a moving image, it is necessary to increase the density of a storage medium (disk or the like). There is a demand for higher modulation efficiency to support this.

The main specifications of the EFM modulation method are: (1) Input: 8 bits (2) Output: 17 bits (NRZI format) 17 bits breakdown ... Data 14 bits + margin 3 bits (3) Run length limit min: 2 Bit max: 10 bits (4) Synchronization pattern: 27 bits including a fixed pattern of 11T-11T. The run length is limited and the cumulative addition value is suppressed by a margin of 3 bits.

An example of the EFM modulation method will be described with reference to FIG. Reference numeral 11 is a data converting means, 12 is a serializing means, 13 is a bit adding means, 14 is a cumulative addition value measuring means, 15 is a synchronizing signal generating means, and 16 is a time division multiplexing means. The operation of the above digital data modulation processing will be described below. The data conversion means 11 inputs 8-bit data, converts it into 14-bit data according to the EFM modulation specification, and inputs it to the serialization means 12. The serializing means 12 outputs the serialized converted data to the bit adding means 13. The bit addition means 13 adds 3 bits of the margin bit based on the run length and the cumulative addition value measured by the cumulative addition value measuring means 14 and outputs it to the time division multiplexing means 16. The time-division multiplexing means 16 time-division-multiplexes the converted data after bit addition and the synchronization signal output from the synchronization signal generating means 15 in a constant cycle, and outputs the modulated signal.

As described above, the absolute value of the cumulative addition value of the modulated signal is suppressed by controlling the margin bit by the bit adding means 13 based on the cumulative addition value after serialization.

If the absolute value of the cumulative addition value is not sufficiently suppressed, the error rate at the time of reproduction is deteriorated, which appears as obstacles such as a reduction in reproduction speed and inability to reproduce.

On the other hand, EFMPlus: The C
oding format of the High-D
energy Compact Disc (IEEE,
WPM 6.1, 0-7803-2140-5 / 95, K
ees A. (Schoolhammer Imink)
As in the EFM Plus modulation method as shown in (1), it is possible to improve the modulation efficiency by converting data from 8 bits → 14 bits to 8 bits → 16 bits and eliminating margin bits.

For example, (1) Input: 8 bits (2) Output: 16 bits (NRZI format) 16-bit breakdown ... 16 bits of data (no margin bit) (3) Run length limit min: 2 bits max: 10 bits ( 4) Synchronization pattern: 32 bits including a fixed pattern of 11T-11T. This method (hereinafter referred to as 8-16 modulation method) is based on EFM.
As compared with the modulation method, the number of output bits after conversion is small, and thus high modulation efficiency can be realized. However, since there is no margin bit, it is necessary to limit the run length and suppress the cumulative addition value by the data itself. As a specific method, it is general to prepare a plurality of types of conversion data having different run lengths, polarities, and cumulative addition values for each input data, and sequentially select the conversion data according to the run lengths and cumulative addition values.

An example of the prior art relating to the 8-16 modulation system will be described with reference to FIG. Reference numeral 21 is a data converting means, 22 is a serializing means, 23 is a cumulative addition value measuring means, 24 is a synchronizing signal generating means, and 25 is a time division multiplexing means. The operation of the above digital data modulation processing will be described below. The data conversion means 21 inputs 8-bit data, converts it into 16-bit data according to the 8-16 modulation specification, and inputs it to the serialization means 22. In the serialization means 22,
The serialized conversion data is output to the cumulative addition value measuring means 23 and the time division multiplexing means 25. The time-division multiplexing means 25 time-division-multiplexes the serialized converted data and the synchronization signal output from the synchronization signal generating means 24 at a constant cycle, and outputs the modulated signal. On the other hand, the conversion data code in the data conversion unit 21 is controlled by the cumulative addition value of the serialized conversion data measured by the cumulative addition value measuring unit 23.

As described above, the absolute value of the cumulative addition value of the modulated signal is suppressed by controlling only the converted data code by the data converting means 21 based on the cumulative addition value after serialization. In order to improve the ability to suppress the absolute value of the cumulative addition value of the modulated signal only by the data conversion means 21, the number of types of conversion data that can be selected must be increased, which causes an increase in the circuit scale. Further, when considering a series of data strings, the types of data strings generated from the combination of data become enormous, and it is virtually impossible to consider all the data strings. Therefore, it can be said that there is always a possibility that the cumulative addition value can be suppressed only for a specific input code and the absolute value of the cumulative addition value continues to increase for a long time.

A case where the absolute value of the cumulative addition value continues to increase for a long time will be described with reference to the drawings. FIG. 4 shows an example of a sector unit format. n bytes (1 byte = 8
(Bit) data and a sync signal including a sync pattern of 11T-11T form a frame, two frames form one row, and m rows form one sector. Three types of synchronization signals, Sy1, Sy2, and Sy3, are prepared and assigned to the beginning of a sector, the beginning of a row, and the timing of the middle of a row. FIG. 5 shows an example of the sync signal format. Of the 32 bits, the first 9 bits are used for distinguishing the sync signal type, and the remaining 23 bits are used for the 11T-11T sync pattern. Hereinafter, the description will proceed based on the formats shown in FIGS. 4 and 5. FIG. 6 shows an example in which the absolute value of the cumulative addition value continues to increase for a long time. In the change of repeating “continuous data A → synchronous signal → continuous data B → synchronous signal → continuous data A”, when the polarity of the cumulative addition value of the data A is +, the cumulative addition value continues to increase by the conversion amount 4. Since the sync signal has the cumulative addition value of 0 and the polarity is inverted, the cumulative addition value does not change at the synchronization timing, but the signal polarity is inverted before and after the synchronization signal. Next, in the data B, since the polarity is inverted by the synchronization signal, the cumulative addition value polarity becomes +, and the cumulative addition value continues to increase with the change amount 4. As described above, the absolute value of the cumulative addition value may continue to increase for a long time depending on the combination of the data and the synchronization signal.

Next, an example of demodulation will be described with reference to FIG.
Reference numeral 31 is a synchronization detecting means, 32 is a parallelizing means, and 33 is a data converting means. The operation of the digital data demodulation process described above will be described below. Modulation signal (16
(Bit serial), the synchronization detection means 31 detects and outputs a synchronization signal. On the other hand, the parallelization means 32 converts the data into 16-bit parallel data and outputs it. The data converting means 33 performs the reverse conversion of the 8-16 modulation data conversion, and outputs 8-bit parallel demodulated data.

[0013]

[Problems to be Solved by the Invention]

 (1) Strengthen the suppression of the absolute value of the cumulative addition value.

(2) In the prior art, there is a possibility that the absolute value of the cumulative addition value may continue to increase for a long time under a specific condition, and a countermeasure is taken.

[0015]

A cumulative addition value is adjusted (selection of a value and a polarity (inversion / non-inversion)) by a synchronization signal.

By adjusting the cumulative addition value for each synchronization signal inserted into the modulation signal at a constant cycle, it is possible to suppress the absolute value of the cumulative addition value and keep the absolute value of the cumulative addition value continuously increasing for a long time. To prevent.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of modulation according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of digital data modulation in the present invention. In FIG. 1, 1 is data conversion means, 2 is serialization means, 3 is cumulative addition value measurement means, 4
Is a synchronizing signal generating means, 5 is a synchronizing signal switching means, and 6 is a time division multiplexing means. The operation of the above digital data modulation processing will be described below. The data converting means 1 receives 8-bit digital data and inputs 8-1.
It is converted into 16-bit digital data according to the 6-modulation specifications and input to the serializing means 2. The serializing means 2 outputs the serialized converted data to the cumulative addition value measuring means 3 and the time division multiplexing means 6. The time-division multiplexing means 6 time-division-multiplexes the serialized converted data and the synchronization signal output from the synchronization signal switching means 5 at a constant cycle, and outputs the result as a modulation signal. On the other hand, the cumulative addition value of the serialized conversion data measured by the cumulative addition value measurement means 3 is used as the data conversion means 1
The switching of the conversion data code and the switching of the plurality of types of synchronization signals by the synchronization switching means 5 are controlled. The cumulative addition value can be measured in 1-bit units regardless of before, after, and after data input.

As described above, based on the cumulative addition value after serialization, not only the conversion data code in the data conversion means but also
By controlling the cumulative addition value and the polarity of the synchronization signal as well, the number of adjustment opportunities increases, so that the absolute value of the cumulative addition value of the modulation signal can be suppressed more than before.

In particular, the phenomenon that the absolute value of the cumulative addition value continues to increase for a long time under the specific condition as shown in FIG. 6 can be prevented because the adjustment is made in the synchronizing signal period in the present invention. This will be described with reference to FIG. Same as Fig. 6 "Continuation of data A →
In the change of repeating “synchronization signal → continuous data B → synchronization signal → continuous data A”, when the polarity of the cumulative addition value of the data A is +, the cumulative addition value continues to increase by the change amount 4. The sync signal is not the sync signal A corresponding to the sync signal in FIG. 5, but the sync signal B having a cumulative addition value of 0 and a non-inverted polarity is selected. As a result, in the data B, the polarity of the sync signal is non-inverted, so that the polarity of the cumulative addition value becomes − and the cumulative addition value starts to decrease at the change amount 4. In this way, it is possible to prevent the absolute value of the cumulative addition value from continuing to increase for a long time.

FIG. 8 shows an example of a plurality of types of sync signals that can be used in the present invention. The 8-16 modulation specification which is the premise of the present invention is satisfied, and a plurality of types of synchronization signals having different cumulative addition values or different polarities actually exist. Among them, the case 1 pattern has a role of controlling the run length min and the case 2 pattern has a role of controlling the run length max. With these 12 kinds of synchronization signals, the cumulative addition value can be adjusted with the synchronization signals in the format of FIG.

Next, a demodulation embodiment of the present invention will be described.
In FIG. 9, it can be realized by the same processing as the conventional technique except that a plurality of kinds of signal patterns (corresponding to the synchronization signal generated by the synchronization generating means 4 in FIG. 1) for determining the synchronization signal by the synchronization detecting means 31 are provided.

[0022]

According to the present invention, it is possible to suppress the absolute value of the cumulative addition value of the modulated signal and prevent the phenomenon that the absolute value of the cumulative addition value keeps increasing for a long time.

[Brief description of drawings]

FIG. 1 is a block diagram of an 8-16 modulation embodiment according to the present invention.

FIG. 2 is a block diagram of an embodiment of an EFM modulation method.

FIG. 3 is a block diagram of an example of an 8-16 modulation method according to the related art.

FIG. 4 is an explanatory diagram of a sector format of an 8-16 modulated signal.

FIG. 5 is an explanatory diagram of a sync signal format of an 8-16 modulated signal.

FIG. 6 is an explanatory view of a cumulative addition value change according to a conventional technique.

FIG. 7 is an explanatory diagram of a cumulative addition value change according to the present invention.

FIG. 8 is an explanatory diagram of a sync signal pattern of an 8-16 modulation signal.

FIG. 9 is a block diagram of a demodulation example of an 8-16 modulated signal.

[Explanation of symbols]

1 ... Data conversion, 2 ... Serialization, 3 ... Cumulative addition value measurement, 4
... Synchronization signal generation, 5 ... Synchronization signal switching, 6 ... Time division multiplexing.

Front page continuation (72) Inventor Takao Arai 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock company, Hitachi Ltd. multimedia system development headquarters No. 1 stock company Hitachi Ltd. semiconductor division

Claims (5)

[Claims] 1. A frame is composed of n-byte (n: natural number) data, and 8-bit data is composed of run lengths 2 to 1.
A block modulation method for converting to 16-bit data limited by 0, wherein the frame includes a synchronization signal including repetition of a longest pattern, and the synchronization signal includes a plurality of types of patterns having different digital cumulative addition values or inversion numbers. And a method of controlling the switching of the synchronization signal according to a digital cumulative addition value of the modulated data. 2. An n-byte (n: natural number) data constitutes one frame, two frames constitute one row, m (m: natural number) rows constitute one sector, and 8-bit data is run-length. In the block modulation method for converting to 16-bit data limited by 2 to 10, the frame includes a synchronization signal including repetition of a longest pattern, and the synchronization signal includes a plurality of sectors that can identify a head of a sector and a head of a row. The plurality of sync signals each include a digital cumulative addition value (DSV) or a plurality of types of patterns having different numbers of inversions, and control switching of the sync signal according to the digital cumulative addition value of the modulated data. A digital data modulation method characterized by the above. 3. One frame is composed of n-byte (n: natural number) data, and 8-bit data is composed of run lengths 2 to 1.
In a block modulation device for converting 16-bit data limited by 0, the synchronization signal includes a synchronization signal generation means for generating a plurality of types of patterns including repetition of the longest pattern and different digital cumulative addition values or inversion numbers. A digitally accumulating means for calculating the digital cumulative addition value of the modulated signal, and means for controlling the switching of the generation pattern of the synchronizing signal generating means according to the calculation result of the digital cumulative addition value calculating means. Modulator. 4. A means for detecting a plurality of types of synchronizing signals switched by digital cumulative addition values, and a means for converting 16-bit data limited by run lengths 2 to 10 into 8-bit data. Digital data demodulating method having. 5. A method according to claim 1, further comprising means for detecting a plurality of types of sync signals including a sync pattern including repetition of a longest pattern, and means for converting 16-bit data limited by run lengths 2 to 10 into 8-bit data. A digital data demodulator provided.