JP3004106U - Disk medium and recording / reproducing apparatus thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] The ratio of "0" and "1" of recorded data is averaged to stabilize the operation of the servo system and the carrier reproduction of the PLL. A spiral recording track is divided into a plurality of zones in a radial direction, a recording track is divided into a plurality of sectors, and one sector format is composed of a header field 100 on the head side and a data field 200 on the rear side. In the header field 100, at least a sector mark (SM) indicating the beginning of a sector, a single period pattern (VFO) used for synchronization pull-in, a data number indicating a zone number, a track number, a sector number to which the following data field belongs are modulated. Identification data (ID) and DC cancellation code (DCC) are arranged. The DCC pattern is determined by a 9-bit code, the second bit from the beginning is undefined, and the sixth bit from the beginning is 1,
The other bits are 0.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a disc recording / reproducing device, and more particularly to a device for handling a disc having a structure and recording system with an improved data format.

[0002]

[Prior art]

 In an optical disc recording / reproducing system, in order to stabilize the recording and reproducing of digital data, the data is modulated at the time of recording, recorded on the disc, and demodulated at the time of reproducing. The modulation method includes an EFM (Eight to Fourteen Moduration) method, a (2, 7) modulation method, and the like. When data is recorded on a disc using such a modulation method, during reproduction, the ratio of “0” and “1” in the pickup signal is averaged, carrier reproduction is stabilized, and the servo system The operation stabilizes.

By the way, a predetermined format of the recording data on the optical disc is determined in advance, but in any case, the header part and the data part are paired (hereinafter, this structure is referred to as 1-sector format). To). Here, the data in the data section is modulated by the EFM method or the (2,7) modulation method, but in the header section, a signal that is not modulated is also arranged.

[0004]

[Problems to be solved by the device]

 The digital data recorded on the optical disk is subjected to data modulation by the EFM method or the (2,7) modulation method. However, in the case of formatted digital data, there is a header part and a data part, and there is also a signal that is not modulated in the header part. For this reason, when a plurality of 1-sector formats are connected, the averaging of the ratio of "0" and "1" may be broken between blocks. If the averaging of the ratio of “0” and “1” is broken, the operation of the carrier reproduction system and the servo system becomes unstable, and a data error or a control error may occur.

Therefore, the present invention has a configuration in which the averaging of the ratio of “0” and “1” of the recording data to be arranged is more sufficient, and a DC cancel code having a pattern in which DC averaging is easily performed is provided. It is an object of the present invention to provide a disc recording / reproducing device having the same.

[0006]

[Means for Solving the Problems]

 According to the present invention, in a signal recorded in a sector, a format of one sector consists of a header field on the head side and a data field on the rear side, and in the header field, at least a sector mark indicating the head of the sector and a sync mark are set. The data is modulated to indicate the single cycle pattern used for the buffer, the first DC cancel code, the address mark for achieving byte synchronization of the following data, the track number to which the data field belongs, the sector number, etc. Identification data is sequentially arranged, and the DC cancel code is a disk medium including data of either "000001000" or "010001000".

Further, the present invention comprises a header field on the head side and a data field on the rear side, and in the header field, a sector mark indicating at least the head of a sector, a single period pattern used for synchronization pull-in, A first DC cancel code, an address mark for byte synchronization of the following data, and data-modulated identification data indicating the track number, sector number, etc. to which the data field belongs are sequentially arranged. In order to obtain the format for one sector, the data modulating means for outputting the data contained in the data field and the identification data, the sync signal for containing the data field, the end mark, and the header field are included. Fixed signal holding means for outputting an address mark for The register means for temporarily storing the signal obtained from the adjusting means and the fixed signal holding means, the address mark for arranging in the header field, and the content of the DC cancel code are determined according to the content of the identification data. In this case, the DC cancel code is set to “0X0001000” (X is indefinite), DC cancel code determining means for determining X or 0 of the second bit from the head of the code by data total value calculation, and the DC cancel code. It is provided with means for selectively deriving the DC cancel code output from the cancel code determining means and the output of the register means and outputting the signal of the one sector format.

[0008]

[Action]

 By the above means, even if there is a signal that is not subject to data modulation in the header part of the sector format, the averaging of the ratio of "0" and "1" is more sufficient because the DCC is inserted. can do. Further, the DC cancel code can easily control the imbalance with respect to subsequent data by selecting the X of the second bit to be 0 or 1.

[0009]

【Example】

 An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram for explaining a data format in an optical disc according to an embodiment of the present invention. FIG. 1A shows an example of a signal format of a sector. The 1-sector format in the sector is roughly divided into a header field 100 and a data field 200. In this invention, a DCC (direct current cancellation code) signal is particularly inserted in the header field 100. This signal will be described in detail later.

The header field 100 is a sector mark (SM) indicating the start of a sector, a single cycle pattern (VFO) for pulling in the synchronization of PLL (phase locked loop), and byte synchronization of the ID field that follows. Address mark (AM), track number, ID data in which sector number is recorded (ID), user data area in which recording and reproduction can be freely performed, and the like. The sector mark (SM) is composed of a long mark pattern so that it can be detected without depending on the PLL. FIG. 1B shows an example of four patterns A, B, C and D of the sector mark (SM), which are identified by the zone to which the sector belongs. In other words, sectors belonging to the same zone are marked with sector marks having the same pattern. The sector mark (SM) can be easily distinguished from other data. When reproduced by the reproducing apparatus, 24 sampling clocks (24T) become "0", the next 24 sampling clocks (24T) become "1", and thereafter, 6T cycle change pattern, 8T cycle change pattern, There are 12T cycle change patterns and 24T cycle change patterns.

FIG. 1C shows a single-cycle pattern, in which “0” and “1” are continuous in a 4T cycle and are continuous for 288T periods. The playback device locks an internal PLL and the like in this VFO. FIG. 1D shows an address mark (AM) pattern, and there are two types. It is used to obtain byte synchronization of the ID field that follows.

FIG. 2A further shows an example of a pattern of the end mark (EM). The end mark (EM) indicates the end of the sector, and is a code having a code length of 18T and a DC component of 0.

FIG. 2B shows an optical disc on which the above data is recorded. The recording capacity of an optical disc is increased by dividing the recording surface into several concentric zones in the radial direction and increasing the number of sectors per track toward the outer zone. I am trying to In the recording / reproducing sequence, first, the sector mark (SM) is found, the start of the sector is detected, the PLL is bit-synchronized by the single cycle pattern (VFO) that appears next, and the address mark (AM) is detected from the data identified by the PLL. ) Is detected, the ID data (ID) is demodulated on the basis of the detected value), the sector is recognized as a target, and the subsequent data recording / reproducing processing is linked.

FIG. 3 shows a basic configuration of the recording data creation unit of the above optical disc. The input terminal 11 is supplied with data (DATA, CONTROL, CRC, ECC) or ID that should be included in the data field 200 shown in FIG. 1A, and is input to the 4/9 modulator 12 to output 4 bits. Is converted to a 9-bit signal. The 4/9 modulator 12 divides a continuous binary data string into 4-bit codes, converts the 4-bit code into 4-bit codes, and converts the 4-bit code into a 9-bit modulation code. In this case, the modulation unit 12 selects and modulates the code so that the number of consecutive bits "0" is less than 3 does not occur between the continuously converted modulation codes. (This modulation method is described in detail in Japanese Patent Application No. 5-76692 filed by the present applicant).

The signal output from the 4/9 modulator 12 is supplied to the selector 13. The selector 13 can be supplied with the synchronization signal (SYNC), address mark (AM), end mark (EM), etc. from the fixed signal holding unit 14. The modulation code, the synchronization signal (SYNC), the ID modulation code, and the like that form the data field 200 obtained by the 4/9 modulator 12 are selected by the selector 13 and sent to the shift register 15, and finally. An end mark (EM) indicating the end of the block is added and temporarily stored. An address mark (AM) is also stored in advance in the shift register 15. The ID (48 bits) indicates the zone number, track number, and sector number to which the following data field 200 belongs.

Therefore, in the shift register 15, AM, ID1, AM, ID2 of the header field 100 and the contents of the data field 200 of the format shown in FIG. 1A are prepared.

Next, in order to complete the format of FIG. 1A, it is necessary to sequentially determine the first DCC, the second DCC, and the third DCC from the left side. These DCCs are determined by the calculation result of the DSV (Digital Sum Value) calculation unit 16.

First, a plurality of DC cancel codes (for example, 9-bit code = DCC) are held in the DC control code holding unit 17, and are selectively used. The DSV calculation unit 16 determines the DCC using the DC cancellation code and the data string before and after the DCC in FIG. That is, the difference between the sum of “0” s and the sum of “1s” is as small as possible in a predetermined data string section, and three or more “0s” are arranged between “1” s and “1s”. DC cancel code is selected. The pattern of the DC cancel code (DCC) is determined by a code of 9 bits, the second bit from the beginning is an undefined X, the sixth bit from the beginning is 1, and the other bits are 0. That is, "0100100" and "00000100" are prepared. When the DCC is determined by the calculation result, it is set in the DCC determination unit 18 and waits for the insertion timing. As shown in FIG. 1A, in the header field 100, the DC C is inserted at a position between VFO and AM (first), between ID1 and AM (second), and ID2 and data. There is a space (3rd) from the head position of the field 200. The insertion position and the number of insertions are not limited to those in this embodiment, but in this embodiment, the arrangement is as shown in FIG. 1 (A). When deciding the first DCC, the contents of VFO and AM are known in advance, so it is decided by the contents of ID1. When determining the second DCC, the content of ID1, the content of the following AM, the content of ID2, etc. are referred to. The contents of ID1 and ID2 are specifically the same. When determining the third DCC, ID1 and a part of the following data are referred to and determined. Therefore, the DSV calculator 16 can also read the contents of a part of the shift register 15. Alternatively, a part of the output from the selector 13 can be stored in advance in order to perform the calculation for determining the DCC. Further, although not shown, a read address control unit is also provided which stores a plurality of types of patterns (for example, address marks) in the shift register 15 in advance and reads the patterns in combination according to the pattern of the DC cancel code. Be done.

The output of the DCC determination unit 18 and the output of the shift register 15 are supplied to the selector 19. First, in order to configure the format shown in FIG. 1A, the selector 19 selects the first DCC and then the AM stored in the shift register 15. Next, the ID1 stored in the shift register 15 is selected, and then the second DCC, the AM, the ID2, the third DCC, and the data field are selected and derived.

The output from the selector 19 is serially converted by the parallel / serial (P / S) converter 20, and the NRZI circuit 21 performs polarity processing according to “0” and “1” data, and the selector 22. Is supplied to. In this selector 22, a sector mark (SM) and a single cycle pattern (VFO) are added to the head of the sector. The sector mark (SM) and the single period pattern (VFO) are obtained from the SM / VFO output unit 23. As a result, sector data having the format shown in FIG. 1A is formed and output to the output terminal 24.

As described above, in this embodiment, the DC C (DC cancel code) is also inserted in the header field 100. For this reason, the averaging of the ratio of "0" and "1" of the recording data becomes more sufficient, and the operation of the servo system and the carrier reproduction of the PLL can be stabilized.

Next, an example of the pattern of the DCCs that are selected and determined in the header field 100 described above is shown. As the DCC, “0X0001000” is prepared, and X is initially undecided, and it is decided to be “0” or “1” according to the pattern of the previous data. For example, the case where the first DCC is determined is as follows. The data before the first DCC is VFO, and the last data ends with "low level". Therefore, as the DCC pattern, the pattern P1 or P3 starting from "low level" is a selection candidate. Next, the DSV calculation unit 16 adds up the contents of the address mark and ID1 (data of 0 and 1) and, when averaging, determines whether X of DCC is 0 or 1 to perform averaging. decide. If it is decided to set X = 0, the pattern P1 is decided as the DCC and the pattern starting from "high level" is decided as the subsequent address mark (AM). If it is determined by the DSV calculation that X of DCC is set to X = 1, the pattern P3 is determined as the DCC, and the pattern starting from "low level" is determined as the subsequent address mark (AM). Will be decided. The pattern by DCC is determined by such a rule that the level does not change when it is "0" and the level is inverted when it is "1".

When the second DCC is determined, the start level of the DCC is determined depending on whether the final level of ID1 ends at a low level or a high level, and four patterns are possible. . After the start level is decided from the four patterns, it will be narrowed down to two patterns. Next, one pattern is determined by the DSV calculation result, and the pattern of the subsequent address mark (AM) is also determined. Also when the third DCC is determined next, the start level of D CC is determined depending on whether the final level of ID 2 ends at the low level or the high level. When deciding the third DCC, up to a part of the data of the subsequent data field is the calculation target of DSV.

[0024]

[Effect of device]

 As described above, according to the present invention, the averaging of the ratio of “0” and “1” of the recorded data is made more sufficient, the operation of the servo system and the carrier reproduction of the PLL are stabilized. It is possible to obtain, especially DC stabilization in the header field. This is effective for stabilizing DC even if an ID (data pattern is indeterminate) is inserted in the header field, providing flexibility in the data format, and improving the reliability of system operation. Become.

[Brief description of drawings]

FIG. 1 is a diagram showing a signal format for explaining an embodiment of the present invention.

FIG. 2 is an explanatory view of a signal format and an optical disk according to the present invention.

FIG. 3 shows a processing device for obtaining the signal format of FIG.

FIG. 4 is a diagram showing an example of various usage patterns of the DCC shown in FIG. 1.

[Explanation of symbols]

100 ... Header field, 200 ... Data field, 12 ... 4/9 modulation section, 13 ... Selector, 14 ... Fixed signal holding section, 15 ... Shift register, 16 ... DSV calculation section, 17 ... DC control code holding section, 18 ... DCC determination unit, 19 ... selector, 20 ... parallel-serial conversion unit,
21 ... NRZI circuit, 22 ... selector, 23 ... SM / V
FO output section.

Claims (6)

[Scope of utility model registration request] 1. In a signal recorded in a sector on a disc, a format of one sector consists of a header field on the head side and a data field on the rear side, and in the header field, a sector mark indicating at least the head of the sector. A single cycle pattern used for synchronization pull-in, a first DC cancel code, an address mark for achieving byte synchronization of the following data, and data modulation indicating the track number, sector number, etc. to which the data field belongs. Identification data is sequentially arranged, and the DC cancel code is data of either "000001000" or "010001000". 2. The leading level of the DC cancel code starts at the same level as the final level of the pattern of signals arranged before it.
The described disc medium. 3. A header field on the head side and a data field on the rear side, wherein the header field includes at least a sector mark indicating the head of a sector, a single period pattern used for synchronization pull-in, and a first DC cancel. To obtain a format for one sector in which a code, an address mark for byte synchronization of subsequent data, and data-modulated identification data indicating a track number, a sector number, etc. to which the data field belongs are sequentially arranged. A data modulation means for outputting the data contained in the data field and the identification data, and a fixed signal for outputting a synchronization signal for inclusion in the data field, an end mark, and an address mark for inclusion in the header field. Holding means, the modulating means and the fixed signal holding means Register means for temporarily storing the signal obtained from the means, the address mark for arranging in the header field, the DC cancel code when determining the content of the DC cancel code according to the content of the identification data Is "0X0001000" (X is indefinite),
A direct current cancel code determining means for determining the second bit X of the code from the beginning of the code to 0 or 1, a direct current cancel code output from the direct current cancel code determining means, and the register means And a means for selectively deriving an output and outputting the signal of the 1-sector format. 4. A signal pattern when the DC cancel code is reproduced is a waveform in which a 5-bit period section has a low level (or high level) and a 4-bit period section has a high level (or low level). Claim 3
The described disk recording / reproducing apparatus. 5. A signal pattern when the DC cancel code is reproduced is a low level (or high level) in a 1-bit cycle section, a high level (or low level) in a 4-bit cycle section, and a low level in a 4-bit cycle section. 4. A level (or high level) waveform is provided.
The described disk recording / reproducing apparatus. 6. A signal recorded in a sector on a disc, wherein the format of one sector comprises a header field on the head side and a data field on the rear side, and in the header field, a sector mark indicating at least the head of the sector. , A single cycle pattern used for synchronization pull-in, a DC cancel code of a predetermined bit length, an address mark for achieving byte synchronization of subsequent data, and data modulation indicating the track number, sector number, etc. to which the data field belongs. A recording data in which the identification data and the identification data are sequentially arranged. When determining the DC cancel code having the predetermined bit length, the unbalanced 0 or 1 is obtained by inverting the few bits from the beginning. Characterized by having a DC cancellation code setting means for controlling the balance Disk recording and reproducing apparatus.