JP2833852B2 - Digital signal output circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal output circuit, and more particularly to a digital signal output circuit used for a processing circuit of an output signal of a digital audio device.

[Conventional technology]

Digital audio media such as compact discs (hereinafter referred to as CDs) have been replaced by analog records such as conventional LPs, and have become mainstream music media. Accordingly, digital audio equipment such as a CD player for reproducing the audio data has become a central component of the audio component, and the demand for higher functionality has been increasing.

The digital signal output circuit is used for demodulating an input signal in the signal processing circuit of these digital audio devices.
The main function of the circuit is to perform processing for forming an output signal which is serial data having a predetermined bit length after signal processing such as error correction.

FIG. 4 shows an example of a conventional digital signal output circuit.

Here, as an example of this type of conventional digital signal output circuit, a digital signal output circuit used in a signal processing circuit of a CD player will be described.

Referring to FIG. 4, the conventional digital signal output circuit 3 includes a data bus 31, an output data register 32, and a 16-bit register 33.

FIG. 3 is a diagram showing an example of the configuration of a signal processing circuit of a CD player including the digital signal output circuit 3, which is commonly used in the description of the embodiments described later.

In FIG. 3, the signal processing circuit of the CD player includes a demodulation unit 1, a signal processing unit 2, and a digital signal output circuit 3.
, An interface unit 4, a system bus 5, a microcomputer 6, and a key input unit / display unit 7.

For the above configuration and each function,
Description is omitted as it is well known as a signal processing system of the player except for the following which is directly related to the present invention so as not to be redundant.

Next, the operation of the conventional digital signal output circuit shown in FIG. 4 will be described in relation to the operation of the entire signal processing circuit of the CD player shown in FIG.

As is well known, in a CD, EFM (Eig)
ht to Fourteen Modulation). EFM signals I from the pickup is inputted from the input terminal T _I, demodulated by the demodulator 1 is input to the signal processing unit 2 is an 8-bit symbol data.

The signal processing unit 2 performs signal processing such as deinterleaving and error correction, and inputs the processed data to the digital signal output circuit 3.

The digital signal output circuit 3 processes the input signal-processed 8-bit data by an output signal processing circuit including a data bus 31, an output data register 32, a 16-bit shift register 33, etc., and outputs a 16-bit digital signal. Form output D.

The data bus 31 has a function of interfacing the 8-bit signal data processed by the signal processing unit 2 with the output data register 32 corresponding to the respective upper 8 bits and lower 8 bits.

The output data register 32 is a 16-bit parallel shift register, and stores upper 8 bits and lower 8 bits of signal-processed data from the data bus 31 to form 16-bit output data.

The 16-bit shift register 32 is a 16-bit parallel input serial output shift register.
It receives the bit parallel data, stores it, and outputs a 16-bit digital signal D as serial data at a predetermined timing.

The interface unit 4 decodes a track number, an index number, and the like from the demodulated subcode signal and displays them on a key input unit / display unit 7, and also interfaces with a microcomputer 6 for system control via a system bus 5. Is what you do.

The key input unit / display unit 7 is a front panel of the CD player,
Alternatively, the track number, index number, and the like are input using keys on the remote control.

As described above, this type of conventional digital signal output circuit combines a plurality of data of a processing unit processed in the preceding signal processing, for example, 8 bits in the case of a CD, in a predetermined time order. Has a function of forming serial output data of a predetermined bit length, for example, 16 bits.

[Problems to be solved by the invention]

The above-described conventional digital signal output circuit does not have a level setting function for a demodulated and signal processed reproduced music signal.

Therefore, when the reproduction level is changed, as in the case of fade-in or fade-out, it is common to use an analog signal after digital-to-analog conversion.

In this case, for example, there is a disadvantage that the reproduction level needs to be changed by manual operation of a volume adjuster of an audio amplifier to which a reproduction music signal from a CD player is input.

Also, when recording the CD playback signal on a magnetic tape with a tape recorder, when performing fade-in and fade-out, use the recording level adjuster of the tape recorder.
There is a drawback that the operator must manually adjust or add a fade-in / fade-out function to the tape recorder.

Further, in a CD player having a variable level output terminal, it is necessary to provide a volume controller for varying the level, and there is a disadvantage that the cost is increased.

[Means for solving the problem]

The digital signal output circuit of the present invention comprises: a first storage means for converting a first digital signal, which is a parallel digital audio signal, into a serial second digital signal in a predetermined format and storing the converted first digital signal; The second digital signal is shifted from the first storage means for each one time signal, and the second digital signal shifted for each predetermined second time signal is sequentially output from the most significant bit A digital signal output circuit for converting the first digital signal into the second digital signal and outputting the second digital signal in a predetermined time sequence, wherein the second storage means from the second storage means The output from the most significant bit of the second digital signal during the period of the set bit value set in response to the control of the volume control signal from the start of the output of the digital signal It is provided with an output control means for controlling to prohibit.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, the target digital signal output circuit is for a CD player cited in the conventional example.

Referring to FIG. 1, a digital signal output circuit 3 of the present invention includes a data bus 31, an output data register 32, and a data bus 32 which are common parts to those shown in the above-mentioned prior art example.
It comprises a level control unit 40 in addition to the bit shift register 33.

The level control unit 40 includes a timing generator 34, AND gates 35 and 36, a counter 37, a coincidence detector 38, and an RS flip-flop 39.

FIG. 3 is a diagram showing an example of the configuration of a signal processing circuit of a CD player including the digital signal output circuit 3, which is commonly used in the description of the above-mentioned conventional example.

In FIG. 3, the signal processing circuit of the CD player includes a demodulation unit 1, a signal processing unit 2, and a digital signal output circuit 3.
, An interface unit 4, a system bus 5, a microcomputer 6, and a key input / display unit 7.

The above configuration and respective functions are common parts to those shown in the above-described example of the related art, and the description is omitted so as not to be redundant except for the following which is directly related to the present embodiment. .

 Next, the operation of the present embodiment will be described.

As described in the above-mentioned conventional example, EFM (Eight to Fourteen Modulation) is employed for recording and reproducing signals in a CD. The EFM signal I from the pickup is input terminal T
_The signal is input from _I , demodulated by the demodulation unit 1, and input to the signal processing unit 2 as 8-bit symbol data.

The signal processing unit 2 performs signal processing such as deinterleaving and error correction, and inputs the processed data to the digital signal output circuit 3.

The digital signal output circuit 3 processes the input signal-processed 8-bit data by an output signal processing circuit including a data bus 31, an output data register 32, a 16-bit shift register 33, etc., and outputs a 16-bit digital signal. Form output D. Further, under the control of the microcomputer 6, via the system bus 5 and the interface unit 4,
The level controller 40 varies the level represented by the digital value of the digital signal.

The interface unit 4 decodes a track number, an index number, and the like from the demodulated subcode signal and displays them on a key input unit / display unit 7, and also interfaces with a microcomputer 6 for system control via a system bus 5. Is what you do.

The key input unit / display unit 7 is a front panel of the CD player,
Alternatively, a track number, an index number, and the like are input using the keys of the remote control, and designation of level control such as fade-in and fade-out is input.

For example, when a fade-in level control command is issued from the key input unit 3, the command is transferred to the microcomputer 6. The microcomputer 6 inputs this to the interface unit 4 via the system bus 5 as a control command including a series of level control programs. The interface unit 4 has a level setting value,
That is, in this embodiment, the signal attenuation is converted into 4-bit data A and input to the level control unit 40 of the digital signal output circuit 3.

Level control unit 40, the data A, and generates the serial shift inhibiting signal S, by controlling the 16 bit shift register 33, adjusts the level of the digital signal output D output from the terminal T _D.

FIG. 2 is a time chart of the circuit of this embodiment shown in FIG.

The above level control will be described in more detail.

As is well known, a CD system employs a 16-bit serial two's complement binary code. Therefore, MSB
Is 0 when the reproduction signal waveform is positive and 1 when the reproduction signal waveform is negative. This is digital-to-analog converted and output as an analog audio signal.

As described above, the digital signal output circuit 3 receives the processed 8-bit parallel data from the signal processing unit 2 and, via the data bus 31, corresponds to each of the upper 8 bits and the lower 8 bits. Then, the data is stored in the output data register 32 to form 16-bit output data.

The 16-bit shift register 33 is a 16-bit parallel input serial output shift register, and outputs 16 to 16 bits.
It receives the bit parallel data, stores it, and outputs a 16-bit digital signal D as serial data at a predetermined timing.

Here, as the clock pulse CP of the signal processing system, two-phase clock pulses CP1 and CP2 are used as shown in FIG. Unless otherwise specified, the high level of the signal is a logical value “1”,
The low level is a logical value “0”.

The digital signal D is loaded from the output data register 32 to the 16-bit shift register 33 by the load signal L from the timing generator 34 of the level control unit 40 operated by the clock pulse CP1. When the load signal L falls to "0", the shift signal S rises and holds "1" during the period in which the 16-bit serial data is shifted.

At this time, 4 input from the interface unit 4
It is assumed that the bit level control command data A specifies the attenuation amount 0, that is, the digital number 0000. In this case, the count value of the counter 37 reset by the load signal L is 0, that is, 0000. Therefore, the coincidence detector 38 detects the coincidence between the two, so that the output is "1". The output "1" of the coincidence detector 38 is applied to the RS flip-flop 39 reset by the load signal L, and outputs a Q output "1".

The output “1” of the RS flip-flop 39 is an AND gate
At 36, the AND of the clock pulse CP2 is taken and passed therethrough, and therefore, in synchronization with CP2, the numerical value stored in the 16-bit shift register 33 is serially output from the MSB sequentially.

As is clear from the above description, in this case, all the numerical values stored in the 16-bit shift register 33 are output. Therefore, the amount of attenuation is zero.

Next, the data of the level control command is, for example, 3,
That is, it is assumed that it is 0011.

In this case, since the coincidence detector 38 outputs “0” until the counter 37 counts 3, that is, 0011,
The output of the RS flip-flop 39 is also "0", and therefore the output of the AND gate 36 is also "0", during which the 16-bit shift register 33 stops and continues to output the MSB.

When the counter 37 counts up to 3, the coincidence detector 38, the RS flip-flop 39, and the AND gate 36 each indicate "1".
And outputs a clock pulse to the 16-bit shift register 33.
CP2 is applied, the shift operation is started, and the stored numerical values are sequentially output from the MSB.

As is clear from the above description, in this case, the numerical value stored in the 16-bit shift register 33 is output with a delay of 3 bits, during which the MSB is output. Now, when the MSB is 0, that is, when the MSB is positive, it becomes 0000, and then the second and lower SBs are output. Also in the case of a negative value, first, 1111 and then the second SB or less are output. As a result, the output level is reduced by 3 bits, that is, 2 ³ (18 dB).

The embodiments of the present invention have been described above, but the present invention is not limited to the above embodiments, and various modifications can be made.

〔The invention's effect〕

As described above, the present invention provides a digital signal output circuit with a function of arbitrarily setting an attenuation amount by a control signal using a digital code by adding a small circuit in addition to a normal output process. There is an effect that the level of music reproduction can be freely changed.

Also, there is an effect that an advanced audio processing technique such as fade-in and fade-out at the time of recording on a general tape recorder or the like can be easily performed with high quality, for example, with a constant level change rate, and easily.

Further, since a volume controller for an analog signal system in this kind of digital audio equipment can be omitted, it is effective in cost reduction.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart of the circuit shown in FIG. 1, FIG. 3 is a block diagram showing an example of the configuration of a CD player, and FIG. FIG. 3 is a circuit diagram illustrating an example of a digital signal output circuit. DESCRIPTION OF SYMBOLS 1 ... Demodulation part, 2 ... Signal processing part, 3 ... Digital signal output circuit, 4 ... Interface part, 5 ... System bus, 6 ... Microcomputer, 7 ... Key input part / display part, 31 ... Data bus, 32 ... Output data register, 33 ... 16-bit shift register, 34 ... Timing generator, 35, 36 ... AND gate, 37 ... Counter, 3
8… Match detector, 39… RS flip-flop, 40…
Level control unit.

Claims (4)

(57) [Claims] 1. A first storage means for converting a first digital signal, which is a parallel digital audio signal, into a serial second digital signal of a predetermined format and storing the converted first digital signal;
Shifting the second digital signal from the first storage means for each predetermined first time signal, and shifting the second digital signal shifted for each predetermined second time signal from the most significant bit A second storage means for sequentially outputting, the digital signal output circuit to convert the first digital signal into the second digital signal and output in a predetermined time order, Output control means for controlling output of the second digital signal from the most significant bit to be inhibited during a set bit value set in response to control of a volume control signal from the start of output of the second digital signal A digital signal output circuit comprising: 2. The second storage means shifts and stores stored numerical values in parallel from the first storage means for each of the first time signals, and is driven by a clock pulse which is the second time signal. A timing signal generating circuit that outputs a predetermined timing signal, a counter that counts the clock pulse in response to the supply of the timing signal, and outputs a count value, A coincidence detector that detects a coincidence between the volume setting value corresponding to the volume control signal and the count value and outputs a coincidence signal; and inhibits supply of the clock pulse to the shift register until the coincidence signal is supplied. 2. The digital signal output circuit according to claim 1, further comprising a clock pulse output prohibition circuit that performs the operation. 3. A digital signal output circuit according to claim 1, wherein said digital signal output circuit is an output circuit of a signal processing circuit of a compact disc player. 4. The digital signal output circuit according to claim 3, wherein said setting bit value is set by a microcomputer for controlling said compact disc player in accordance with designation of control command means by key input.