JPH0923123A - Device for attenuating digital audio signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To use a multiplier in a filter also as a fade-in/fade-out multiplier in a muting period, and at the time of muting off, to directly output a digital audio signal to the output side so as not to execute requantization. SOLUTION: An input digital audio signal is supplied to a multiplier circuit 3 in a digital filter and a coefficient signal for executing fade-in or face-out in a muting or pause period is supplied from an up/down counter 2 to which a soft muting signal is supplied to execute multiplication. At the time of a muting or pause off state, the input digital audio signal is directly outputted to a player or the like through a switching means 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
Disc) players and DAT (digital audio
The present invention relates to a digital audio signal attenuator suitable for use in a magnetic recording / reproducing device for tapes.

[0002]

2. Description of the Related Art Continuous analog audio signals such as music
If the signal is interrupted during the playback of the signal, it is shown in Figure 5A.
As shown, the playback signal 1 was paused or stopped.
Time t ₁Then, the pause or stop is released and the playback signal 1
Time t to be reproduced again_TwoThat is, at the time of falling and rising
Occasionally, a click sound is generated when the reproduction signal level is high.

Further, at the time of signal switching, that is, as shown in FIG. 5B, the first reproduction signal 1a is changed to the second reproduction signal 1b at time t ₃ .
At the moment of switching to, the click sound is generated. Fade in to prevent such clicks,
It is well known that the reproduction signal is gradually decreased and gradually increased by performing fade-out.

[0004]

As described above, when an analog signal is faded in or faded out, this can be performed relatively easily by using a variable resistor or the like. However, approximation, C, which has started to be used a lot
Digital players such as D players and DAT magnetic recording / reproducing devices
In the case of attenuating a click generated by interruption or switching in the signal at the digital stage before being input to the analog conversion circuit, there is a drawback that many parts are required.

The present invention has been made in view of the above drawbacks, and the present invention is a multiplication circuit for gradually reducing or gradually increasing a large-scale multiplication circuit used as a digital filter in a CD player or the like when a digital signal is interrupted. It is intended to reduce the cost and save the space without requantizing the input data.

[0006]

A digital audio signal attenuator according to the present invention, as shown in the principle system diagram of FIG. 1, has a multiplier circuit 3 and a coefficient whose coefficient is gradually increased or decreased. It has an up / down counter 2 for signal generation, and the multiplication circuit 3 is also used as a multiplication circuit of a digital filter. The input digital audio signal 8 and the coefficient signal 2 from the up / down counter 2 are added to this multiplication circuit 3.
In addition to multiplying a, the input digital audio signal is directly output without passing through the multiplication circuit when muting is off.

The digital audio signal attenuator of the present invention uses the multiplication circuit 3 of the digital filter in common and multiplies the input digital audio signal 8 and the coefficient signal 2a from the up / down counter 2 and outputs the result, thereby interrupting the digital signal. Alternatively, the click sound at the time of switching can be faded in or out, and the input data at the muting off can be directly supplied to the output terminal without requantization.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION One embodiment of the present invention will be described in detail below with reference to FIGS. FIG. 1 is a system diagram of a digital audio signal attenuator of the present invention, and FIG. 2 is a waveform explanatory diagram.

In FIG. 1, reference numeral 2 denotes an up / down counter circuit for generating a coefficient signal, and a soft mute signal 6 for soft muting is added to one input terminal T ₁₄ thereof. When the soft mute signal 6 is "off", the counter circuit is up-counted, and when it is "on", it is down-counted.

The other input terminal is the clock terminal CK, but the muting time can be externally controlled by passing the OR gate circuit OR without directly supplying the clock signal. That is, the count clock signal 46 from the timing oscillation circuit (see 22 in FIG. 4) is applied to one input terminal T ₂₄ of the OR gate circuit OR, and the muting time is changed or changed to the other input terminal T _15. A hold signal 7 is added so that the fader control can be performed gently, and a clock signal obtained by changing the count clock 46 to an appropriate period is added to the chrono terminal CK of the up / down counter 2.

From the output terminal of the up / down counter 2, a coefficient signal 2a (coefficient K = 1, corresponding to the mute signal).
2, 3, ...) Are output and added to the multiplication circuit 3.

This multiplication circuit 3 also serves as a multiplication circuit of a digital filter, which receives an input digital audio signal 8 (hereinafter referred to as data) via an input terminal T ₂ and outputs this data D _in and a coefficient signal. K is D _out = K × D
_in are multiplied by the multiplier circuit 3 as a, it applied to the contact b of the switching means 5. The contact c is connected to the input terminal T ₂ to which the data D _in is added, and the common contact a is the output data D
It is connected to the output terminal T ₂₀ for outputting _out .

The output terminal T ₂₀ is connected to a digital-analog conversion circuit (not shown) such as a CD player.

The movable contact piece a of the switching means 5 is controlled by the control circuit 4 when the muting in the up / down counter 2 is "off", and the contact piece is tilted to the c side for data D.
_It is configured to add _in directly to the output terminal T ₂₀ . This prevents the data D _in from being requantized.

According to such a digital audio signal attenuator, as shown in FIG. 2A, D _out from the output terminal T ₂₀ , that is, the level of the reproduction signal 1 is in a pause (muting) from "off" to "on". ) Or stop time t ₁
Does not reach zero immediately and is multiplied by the multiplication circuit 3 as in D _out = K × D _in (K = 1,2,3 ...), and gradually attenuates according to the data D _in until t _1-1. Reaches a zero level, and even when the pause shown by t ₂ is released, the data D is not immediately reached the predetermined level of the reproduced waveform 1 and within the period from t ₂ to t _2-1.
It gradually increases according to _in and reaches a predetermined level.

The first and second reproduced signals 1 shown in FIG. 2B.
Also at the time of switching between a and 1b, during the period from the switching time point t ₃ to t _3-1 the data signal D _in which is the first reproduction signal 1a is multiplied by the sequentially decreasing coefficient signal K to be gradually attenuated, and t
At time _3-1 the data D _in which is the second reproduction signal 1b is multiplied by the coefficient signal K which increases _in sequence and gradually increases, and at t _3-2 the switching of the second reproduction signal is performed. As a result, D _out with a smooth movement can be obtained.

The above-mentioned up / down counter 2 stops counting when the count output becomes 1 or 0. Therefore, when the CD player or the like is stopped as shown in FIG. 2A, the coefficient signal K = 1. , K = 1 → 0 during interruption (pause or muting), K = 0 → 1 when muting is released, and K = 1 → 0 → 1 when switching is performed as shown in FIG. 2B.

Since the multiplication circuit 3 of the above-mentioned digital audio signal attenuator utilizes the multiplication circuit arranged in the integrated circuit for the oversampling filter, the oversampling filter characteristics and An integrated circuit (I
The system diagram of C) will be described.

In the CD player, when the stereo left and right channel signals are sampled at the sampling frequency fs = 44.1 kHz, as shown in FIG. 3A, in addition to the original signal 10, fs, 2f.
A fundamental wave centered on s, 3fs, 4fs, ... And high frequencies 11, 12, 13, 14, ... Of odd and even times are generated.

In order to filter these high frequencies 11, 12, 13, and 14, as shown in FIG. 3B, the fundamental wave (4
4.1 kHz) 11 and the third harmonic (44.1 kHz)
z × 3) Eliminate 13 odd harmonics.

As shown in FIG. 2C, the even harmonics of the second harmonic (44.1 kHz × 2) 12 are generated by the second oversampling filter of the 21st order, which is cascade-connected to the first oversampling filter. Eliminate.

Here, the fourth harmonic (44.1 kHz ×
4) 14 is eliminated by the frequency characteristic of the analog low-pass filter shown by the broken line 15 in FIG. 3D, which is added after the digital-analog conversion, and is not removed here.

That is, the fundamental wave and the second and third harmonics are attenuated or eliminated by the first and second oversampling filters as shown in FIG. 3D.

Such a digital filter IC is shown in FIG.
6 is shown. T _{1 to} T ₂₃ indicate input / output terminals of the IC, and the input circuit 17 includes data D _in 8 from the input terminal T _2.
Is serially input and added to one input terminal of the exclusive OR gate circuit EOR, and the input terminal T ₁
Is supplied with the phase inversion control signal 18 and is applied to the other input terminal of the exclusive OR gate circuit EOR.

Exclusive OR gate circuit EOR
The polarity of the output of is changed when the phase inversion control signal 18 is "H" level, that is, it is inverted, and when it is "L" level, it is not inverted.

Output terminal T _{20 of the} digital filter IC 16
Digital-analog conversion circuit (hereinafter D / A)
There is a voltage output type and a power supply output type, and if the current output type D / A is used _in a system _in which the data D _in is in positive phase by using the voltage output type D / A, the output is in reverse phase. Since there is a restriction on the selection of D / A, and vice versa, there is a restriction on the selection of A / D by adding this input terminal T ₁ .

In a CD player or the like, when all the bits are 0 or 1, the expression becomes as close to zero as possible.
Because the binary number display called "2'S compliment" is performed, the polarity of the audio output is controlled for phase inversion by utilizing the property that the polarity of the data is inverted if all the bits are inverted. It can be easily switched by a signal.

Exclusive or gate circuit EOR
The serial data from is supplied to the error correction circuit 21 as parallel data through the serial-parallel conversion circuit SP.

A bit clock 19 and a left / right signal discrimination clock 20 in the input digital audio signal are added to the input terminals T ₃ and T ₄ of the input circuit 17. The left / right signal discrimination clock 20 is also added to the timing oscillation circuit 22.

An error flag 23 is given from an input terminal T ₅ of the error correction circuit 21, and the data 8 is error-corrected. However, in practice, the multiplication circuit / accumulator 3 performs multiplication to perform various error corrections. .

The first switching means 25 has a contact a,
Although b and c are shown, an electronic switch is enabled and a memory (RA for storing data through one switching passage ba) is used.
M) 24 is input.

The data RAM 24 has an 8th order data RAM 24a and a 21st order data RAM 24b.
These data RAM outputs are added to the multiplication circuit 3 described in FIG.

The multiplying circuit 3 includes an accumulator, and the coefficient K ₁ and K ₂ columns from the coefficient ROM 26 are input to the accumulator of the multiplying circuit 3 through one switching passage ba of the second switching means 27. It

The coefficient ROM 26 also has coefficient ROMs 26a and 26b for the 83rd order and the 21st order.

The coefficient ROM 26 is provided with two types of coefficient K ₁ and K ₂ rows depending on whether or not the frequency characteristic is corrected. Coefficient switching signals 28 and 29 for switching these coefficients are provided to the terminal T _{16 as} required. , T ₁₇ and coefficient ROM 26
It is designed to switch the coefficient stored in the memory.

Input to the multiplication circuit / accumulator 3
Terminal T₁₈, T₁₉Has an input terminal T ₁₈For offset
Signal 30 is input and input terminal T₁₉Zero level ± 1%
The offset signal 31 is added.

The output of the multiplier circuit / accumulator 3 is applied as a parallel output to the overload limiter circuit 32, and the overshoot is suppressed and applied to the output circuit 33.

The output of the overload limiter circuit 32 is returned to the data RAM 24 through the line 34 and the other switching passage c → a of the first switching means 25.

The mute signal 35 to the input terminal T ₆ of the output circuit 33, a serial / parallel data switching signal 36 to the input terminal T _7, the format switching signal 37 to the input terminal T ₈ is the input terminal T ₉ The 16-bit / 18-bit switching signal 38 is added respectively.

The output terminal T ₂₀ of the output circuit 33 has D ₁
Data D to D ₁₆ and a bit clock and a word clock 39 are fed to the output terminal T ₂₁ by the left and right (L, R) clocks 4
0, the left aperture clock 41 at the output terminal T ₂₂ ,
Right aperture clock 42 are respectively output to the output terminal T _23.

Here, the left and right aperture clocks 41, 4
2 is a clock for controlling the sampling and holding circuit, and the word clock is 2 of the LR clock frequency.
It is twice.

The input terminal T of the timing oscillation circuit 22 is
₁₀ is input / output at power-on, an initialization signal 42 for phase adjustment of the LR clock, a crystal input signal 45 is input to the input terminal T ₁₃ , a system clock 43 is output to the output terminal T ₁₁ , and an output terminal T. _A crystal output signal 44 can be taken out at 12.

Further, the up-down counter circuit 2 described in FIG. 1 is provided, and the coefficient signal 2a is added to the multiplication circuit / accumulator 3 through the other switching passage c → a of the second switching means 27, and the input terminal T ₁₄ Is applied to the up / down counter 2, and the hold signal 7 from the input terminal T ₁₅ is applied to one input of the OR gate circuit OR. Further, the count clock 46 from the timing generation circuit 22 is added to the other input of the OR gate circuit OR.

The output of the OR gate circuit OR is applied to the clock terminal CK of the up / down counter 2.

In the above structure, when performing the function as a digital filter, the first and second switching means 25 and 27 are in contact with one of the switching passages a-b, and the data 8 is the multiplication circuit / accumulator. 3 is used to perform error correction in the previous process, and the output of the 83rd-order RAM 24a is added to the multiplication circuit 3 to perform the 83rd-order filtering on the data stored in the data RAM 24, and the coefficient for the 83rd-order of the coefficient ROM is added. The K ₁ column is multiplied by this data, and the L and R data signals are multiplied 22 times, respectively, for a total of 44 times. As a result, filtering as shown in FIG. 3B is performed.

The result of such multiplication is applied to the data RAM 24 through the line 34 and the other switching passage c-a of the first switch means 25, and the output of the 21st-order RAM 24a is added to the multiplication circuit / accumulator 3 to obtain the 21st-order. The coefficient string stored in the coefficient ROM is multiplied again.

This multiplication is also performed on the L and R data signals 22 times, 44 times in total, and filtering as shown in FIG. 3C is performed, and the output circuit 33 outputs data having the characteristics as shown in FIG. 3D. Is obtained.

The above-mentioned multiplication circuit / accumulator 3 is a CD
It is possible to multiply 96 times during 22 μs which is one cycle of the data, and there is a margin to perform 96-88 = 8 times of multiplication.

When performing the soft muting operation of the present invention, it is only necessary to multiply the L and R data once, respectively, a total of two times, and the second switching means 27 is connected to the other switching passage c-a side. None, a soft mute signal 6 applied to the up / down counter 2 switches up or down counting.

A count value that counts down or counts up corresponding to the coefficient signal 2a that gradually decreases or increases according to the clock signal is output.

Such a coefficient signal 2a is multiplied by the L and R data, and fade-in or fade-out is performed according to the L and R data as shown in FIGS. 2A and 2B to output the overload limit circuit 32 and the output. Data is output to the output terminal T ₂₀ through the circuit 33, converted into analog by a D / A (not shown), and the low-pass filter provided in the analog stage removes the fourth-order frequency spectrum component shown in FIG. 3D.

As described above, in the present invention, since the multiplication circuit / accumulator for filtering or error correction can be used also for the fade-in or the fade-out during muting, the multiplication circuit of the multiplication circuit can be removed at the same time as click removal during muting. The shared use greatly reduces the space and cost, and when soft muting is off, the input data can be bypassed without being multiplied by the coefficient as detailed in FIG. Can be prevented.

It is needless to say that the present invention is not limited to the above-mentioned embodiments and various modifications can be made without departing from the gist of the present invention.

[0054]

Since the present invention is constructed as described above, it is possible to prevent a click sound generated at the time of interruption, reproduction start or switching of a signal in a digital audio device through a digital data path.

Since the multiplication circuit used in the digital filter IC can be used, the space can be saved and the cost can be greatly reduced, and requantization can be prevented when soft muting is turned off. Have.

[Brief description of drawings]

FIG. 1 is a system diagram of a digital audio signal attenuator of the present invention.

FIG. 2 is an audio signal waveform diagram of the present invention obtained with the configuration of FIG.

FIG. 3 is an oversampling filter characteristic diagram for explaining the digital audio signal attenuator of the present invention.

FIG. 4 is a system diagram of a digital filter integrated circuit used in the present invention.

FIG. 5 is a conventional audio signal waveform diagram at the time of interruption or switching of data.

[Explanation of symbols]

2 up / down counter, 3 multiplication circuit, 4 control circuit, 5 switching means, OR or gate circuit, 6
Soft mute signal, 7 hold signal, 8 input digital audio signal, 46 count clock

Claims (1)

[Claims] 1. A multiplication circuit, and an up / down counter for generating a coefficient signal whose coefficient is gradually increased or decreased. The multiplication circuit also functions as a multiplication circuit of a digital filter. In the multiplication circuit, the input digital audio signal is multiplied by the coefficient signal of the up / down counter, and at the time of muting off, the input digital audio signal is directly output without passing through the multiplication circuit. A characteristic digital audio signal attenuator.