JPH01319178A - Data recording method and data recording medium - Google Patents

Abstract

PURPOSE:To attain data control for the unit of block by independently controlling the DSV (Digital Sum Variation) of recording data for the unit of data block and executing the writing or rewriting of the recording data for the unit of data block. CONSTITUTION:For example, by resetting registers 29 and 30, which hold cumulative DSV and polarity, to a frame, namely, in each sub block, the control of the DSN is independently executed for the unit of one sub block and the recording data, for which the marging bit of a bit pattern to correspond to the value of this DSV is inserted between the data of an (n)-bit. Accordingly, for the recording data, the independent control of the DSV is executed for the unit of one sub block. Thus, the data are independently controlled as block data, which define one sub block unit as one sector, and the recording and reproducing of the data can be executed.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention converts m-focus data into n-bit data larger than the m bits, and inserts n-bit merging bits between the n-bit data. At the same time, the number of consecutive “°0” bits in the alternating series of these n-bit data and n-bit merging bits is at least a predetermined number d and at most a number larger than this d. Regarding a data recording method for recording data by modulating the data, and a data recording medium on which the above-mentioned data is recorded, for example, it is applied to data storage such as CD-WO and CD-RAM according to the data format of the so-called compact disc (CD). Ru.

[Summary of the Invention] The present invention converts m-bit data into n-bit data larger than the m-bit data, inserts ρ-bit merging bits between the n-bit data, and converts these n-bits into n-bit data. Data that records data by modulating it so that the number of consecutive °゛O'' bits in an alternating series of merging bits of data and p bits is at least a predetermined number d and not more than a predetermined number greater than d. In the recording method, digital sum variation (
DSV:Digital Sum Variation
) by inserting merging bits with a bit pattern corresponding to the value of n-bit data between the n-bit data and resetting the value of the DSV in units of predetermined data blocks, data management in units of predetermined data blocks is facilitated. It has been made possible to do so.

Further, the present invention provides data recording that allows data management in units of predetermined data blocks to be easily performed by recording data in which merging bits of a bit pattern according to the value of DSV reset in units of predetermined data blocks are inserted. It is a realization of the medium.

[Prior Art] Conventionally, so-called compact discs (C
D) Disc player devices dedicated to playback, such as CD players, are generally provided.

In the above-mentioned compact disc (CD), E F M (Eightt) is a signal of 8 bits per symbol converted into data of 14 bits (1 channel bit).

Fourteen? 24-bit synchronization signal given as 1 odulation) data, 14-bit (l
One frame consists of 588 bits consisting of the subcode of the symbol, 14 x 32 bits (32 symbols) of data such as performance information, parity, and 3 margin bits between each symbol, as shown in Figure 6. A data format in which a 9-day frame constitutes one subcode block has been standardized, and the absolute address of the above-mentioned l subcode block is given by the Q channel signal of the above subcode, and the above-mentioned 1 subcode block unit is Data processing is performed on data such as performance information.

In the EFM on the above compact disc (CD),
Modulation is performed so that the number of consecutive "0" bits in the series of 14 pinto (L symbol) data and 3-bit merging bits is 2 or more and 10 or less, and also from the start position of the recorded data. Digital Sum Variation (DSV)
The DSV is controlled by continuously counting the DSV and providing merging bits with a bit pattern corresponding to the value of the DSV.

In addition, the digital audio signals of the left and right channels recorded on the compact disc (CD) are treated as one channel serial data signal by alternately consecutiveing each word (2 symbols = 16 bits), and etc., by adding a header section and a synchronization signal in advance of one subcode block, that is, 98 frames of data in the CD data format, byte data is added to 2 in the data format as shown in Figure 7. constitutes one sector (or one block).

Furthermore, since conventional CD players are only for playback, it is possible to record and play back using a magneto-optical disk made of a rewritable magneto-optical recording medium, making it compatible with the above CDs. CD-WO and C that keep
Development of data storage such as D-RAM has been progressing for some time.

(Problem to be Solved by the Invention) By the way, in the data format of a CD, as mentioned above, the DSV is continuously counted from the start position of the recorded data, and merging bits of a bit pattern according to the value of this DSV are provided. As a result, since the DSV is controlled, data cannot be written or rewritten.Also, CD-WO and CD-RAM
In data storage such as , it is necessary to efficiently manage data in block units.

Therefore, in view of the above-mentioned circumstances, the present invention converts m-focus data into n-focus data larger than m bits, inserts p-bit merging bits between these n-bit data, and The data is modulated such that the number of successive 00″' focuses is greater than or equal to a predetermined value d and less than or equal to d greater than d in an alternating series of n-bit data and ρ-bit merging bits. Data recording method to record and data recording medium such as CD-WO or CD-RAM on which the above data is recorded, data can be written and rewritten in block units, and data management in block units is possible. It aims to make it possible.

[Means for Solving the Problems] In order to achieve the above-mentioned object, the present invention converts m-bit data into n-bit data larger than m bits, and converts p bits between the n-bit data. merging bits are inserted, and the number of consecutive "0" bits in the alternating series of these n-bit data and p-bit merging bits is greater than or equal to a predetermined number d and less than or equal to d greater than this d. In a data recording method that records data by modulating it so that
A merging bit of a bit pattern according to the value of
It is characterized by resetting the value of v.

Further, in the data recording medium according to the present invention, m-bit data is converted to n-bit data larger than the m-bit data, and the merging bits of the p-bits of the bit pattern according to the DSV value of the recording data are the n-bit data. and in the alternating series of these n bits of data and p merging bits.
The data is recorded by resetting the above-mentioned DSVO value in units of a predetermined data block, and modulating the data so that the number of successive bits of "O" is greater than or equal to a predetermined value d and less than or equal to d greater than d. It is said that

[Operation] In the method of the present invention, merging bits with a bit pattern corresponding to the DSV value of the recording data are inserted between the n-bit data, and the DSV value is reset in units of predetermined data blocks. DSV of data
are controlled independently on a data block basis, and recording data is written or rewritten on a data block basis.

Furthermore, in the data recording medium according to the present invention, since the DSV of recorded data is independently controlled in units of data blocks, even if recorded data is written or rewritten in units of data blocks, recorded data in other data blocks does not affect the content of

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

In the block diagram of FIG. 1 showing the modulation circuit used to implement the method of the present invention, (1) is a CI (not shown).
8-pin parallel data signal (Sd) from RC encoder
is the data input terminal to which is supplied, and <2) is 4
．． It is a clock input terminal to which a 3218 MHz system cross sync signal (Sc) is supplied, and (3) and (4) are also supplied with a 7.35 kllzO frame sync signal (Sc).
f) and l subcode blocks, that is, block sync signals (Sb) for every 98 frames are supplied to each sync input terminal.

Here, as shown in FIG. 2, between the frame sync signals (Sf), 32 8-bit parallel data signals (Sd) of CrRC encoded audio signals are formed, and subcode signal (SC
) is formed, and the data signal (Sd) and subcode signal (SC) are selected at a predetermined timing by a selector or the like (not shown) and supplied to the data input terminal (1).

The data signal (Sd) is connected to the data input terminal (1).
The 8-bit data is then supplied to the read-only memory (11), where it is converted from 8-bit data to 14-bit data according to a predetermined conversion table. The data signal converted into 14-bit data by the read-only memory (11) is sequentially transferred to registers (12), (13), and (14).

In addition, the system clock signal (Sc), frame sync signal (S'') and block sync signal (Sb) are sent to the system control circuit (15) via the input terminals (2), (3) and (4). The system control circuit (15) receives the system clock signal (Sc).

Based on the frame sync signal <sr> and the block sync signal (Sb), the operation of each circuit block is controlled in units of 98 frames, that is, one subblock.

Here, in the CD data format, the sync pattern in the data signal is (100000000001
000000000010), and in this embodiment, the above register (12),
(13) and (14) handle 14-bit data, so (100000000001
00) (7) l 4 hira) (It is replaced with the D pattern and restored to a 24-bit sync pattern at the output stage. The 14-bit pattern data is processed according to the frame sync signal (Sf). A signal from the system control circuit (15) causes the read-only memory (16) to read the register (12).
, (13), (14).

Also, in the above subcode signal, 5o-(0010
0000000001) Sl-(0000000001
0010) is inserted, so
These signals (30) and (Sl) are used by the system control circuit (15) according to the block sync signal (Sb).
The read-only memory (16
) formed by the above registers (12), (13)
, (14).

These signals are sent to the registers (12) and (13) above.
By sequentially transferring data in (14), the data one before the data held in the register (12) is held in the register (13), and the data two previous data is stored in the register (13). (14) is held.

Furthermore, the number of 0'' at the leading end and the number of '0' at the end of the 14-bit data formed in the read-only memories (11) and (16) are uniquely determined by the data signal (Sd). These numbers are formed simultaneously with the data signal. Here, the number of "0"s at the beginning and end of the 14-bit data is determined to be 9 or less in the above-mentioned conversion table, and is represented by 4 bits. Note that in the sync pattern, the number of #0'' at the end of the 14-bit replacement data is two, but in the 24-bit pattern it is one, so the number of #0'' at the end in this case is (0001
). These 4-bit signals are also transferred in the register bars 12), (13), and (14) in the same way as the data signals.

A numerical value (
F+) and a numerical value (B2) indicating the number of "0"s at the end of the register (13) are supplied to addresses of read-only memories (17) and (18) forming 3-bit merging bits.

Here, the merging bit is (000) in the read-only memories (17) and (18).
, (001), (010), and (100), four bit patterns are selected that satisfy the above-mentioned rule in which the number of consecutive 0'' is 2 or more.Furthermore, the above-mentioned merging bits are It is necessary to satisfy the rule that the number of consecutive “0”s inserted between
, ) and a numerical value (B2) indicating the number of "O" at the end as an address, a bit pattern excluding combinations that do not satisfy the above rules is selected. Furthermore, the above merging bit is inserted between the preceding and succeeding data signals,
In order not to match the above-mentioned 24-bit sync pattern, if the patterns of the preceding and succeeding data signals are any of the following 11 patterns, the combinations of the respective merging bits marked with an X are excluded. Note that the merging bits are shown for all cases selected by the above numerical values (Fl) and (at).

merging bit sync pattern sync pattern merging bit merging and merging and merging bit merging bit merging bit merging bit merging bit merging bit merging bit merging bit merging bit merging bit merging bit
Merging bit The above 11 bit patterns are:
Discrimination can be made based on the current data, the previous data, the two previous data, and the previous merging bit. In this embodiment, the read-only memory (1
7) outputs all merging bits for the above numerical values (Fl) and (Bz), and also outputs the above numerical values (Fl) and (Bz) for the above 11 cases from the read-only memory (18). In contrast, merging bits excluding the combinations marked with an X are output.

Furthermore, the above registers (12), (13), (
14) and the register (4) to be described later.
The previous merging bit held in 2) is supplied to a detection circuit (19), and the above-mentioned 11 cases are detected by this detection circuit (19). The above detection circuit (
19), the read-only memory (17) is normally selected, and in the 11 cases described above, the read-only memory (18) is selected.

In this embodiment, the read-only memory (17
), the merging bit output from (18) is
It is supplied to the selector (20). Further, numerical values from 0 to 3 are sequentially supplied to the selector (21) from the system control '11 circuit (15). This selector (21)
initially selects the system control circuit (15) side, and gives a value from O to 3 from the system control circuit (15) to the selector (20). Thereby, the selector (20) selects the input, ie, the merging bit, according to the numerical value [0 to 3] from the system control circuit (15).

The merging bit selected by the selector (20) is supplied to the address of the read-only memory (22), and the digital sum variation (DSV) of the digital signal constituting the merging bit is supplied to the read-only memory (22). ) and polarity signals are formed. Further, the data signal of the register (12) is supplied to the address of the read-only memory (23),
A digital sum variation (DSV) and polarity signal of the digital signal constituting the data signal are formed in the read-only memory (23). In addition, the DSV and polarity signals of this data signal and merging bit are stored in DSV registers (24) and (25), respectively.
, polarity registers (26), (27).

Signals from the DSV registers (24) and (25) are supplied to one input (A) of the addition/subtraction circuit (28). The other input CB of the addition/subtraction circuit (28) is supplied with a signal from the cumulative DSV register (29). Furthermore, the polarity registers (26) and (2
The signal from 7) and the signal from the cumulative polarity register (30) are supplied to a combinational logic circuit (31), and the output of this logic circuit (31) is sent to the addition/subtraction circuit (28).
The addition and subtraction of is controlled.

The output signal of the above addition/subtraction circuit (2nd) is the register (32
), (33) as well as the absolute value circuit (
34) to registers (35) and (36).

Further, the output signal of the register (36) is supplied to one input (A) of the addition/subtraction circuit (28).

Furthermore, the above registers (32), (33), (
The output signal of 35) is supplied to the other input (B) of the addition/subtraction circuit (28), and the output signal of the cumulative DSV
It is supplied to the register (29).

Further, the signal from the logic circuit (31) is transmitted to the selector (3
7). Furthermore, the polarity register (38)
A signal from is supplied to the selector (37),
This selector (37) is controlled by a signal from the addition/subtraction circuit (28), and the signal from this selector (37) is supplied to the polarity register (38).

The signal from the polarity register (3 days) is then supplied to the cumulative polarity register (30).

Further, the numerical value supplied from the system control circuit (15) to the selector (21) is also supplied to the selector (39). The selector (39) is supplied with a signal from the indicator (40), and this selector (39) is supplied with a signal from the indicator (40).
39) is controlled by the signal from the addition/subtraction circuit (28), and the signal from this selector (39) is supplied to the indicator (40). Further, a signal from the indicator (40) is supplied to the selector (21).

These circuits are the system control circuit (15).
Controlled by signals from the
The optimal combination of merging bits for suppressing the C component is selected. In order to output a set of signals consisting of a 14-bit data signal and 3-bit merging bits in series, zt+3=17. If 17 clock periods are required and all the above data are processed in parallel,
As shown in FIG. 3, processing is performed at timings 0 to 16 using 17 time slots A to R, and a new 14-bit pattern is input at the next timing 0.

That is, first, at timing 0, the above register (12)
Set any 14-bit data to .

Then, in period (A), each read-only memory (1
7), (1B), (20), and (23), and further accesses the read-only memory (22) using the first merging bit selected by the selector (20).

Next, at timing 1, the read-only memory (22
), (23) and the DSV and polarity of the first merging bit are stored in the register (24).
), set to (27). Then, in period (B), the outputs of the registers (25) and (29) are selected and supplied to the addition/subtraction circuit (28), and the logic circuit (31) selects the outputs of the register (30). is extracted as it is and supplied to the above addition/subtraction circuit (2nd), and when the polarity is negative ('0'), addition (^1B) is performed, and when the polarity is positive (B), subtraction (A-8) is performed. .

The calculation result from the above addition/subtraction circuit (28) is calculated at timing 2.
At the same time, the absolute value of this value is set in the register (35).

Then, in period (C), the above register (32),
The output of (24) is selected and supplied to the adder/subtracter circuit (28), and the logic circuit (31) takes out the exclusive OR of the outputs of the registers (30) and (27) to determine the polarity. v control of the addition/subtraction circuit (28) is performed.

The calculation result and absolute value by the addition/subtraction circuit (28) are set in the registers (32) and (35) at timing 3, and the above exclusive OR output by the logic circuit (31) and the above register (26) are set. The exclusive OR with the contents of is extracted and set in the register (38), and the indicator (40) is set to 0.

Also, during this period (C), the second merging bit is selected by the selector (20), and the output of the above-mentioned only memory (22) is sent to the registers (25) and (26) at timing 3. ). Then, in period (D), the outputs of the registers (25) and (29) are sent to the addition/subtraction circuit (28), and an operation according to the polarity of the register (30) is performed on the addition/subtraction circuit (28).
).

The calculation result and absolute value by the addition/subtraction circuit (28) are set in the registers (33) and (36) at timing 4. And 1. During the period (E), the outputs of the registers (33) and (24) are applied to the addition/subtraction circuit (28).
) and registers (30) and (26) above.
The above addition/subtraction circuit (
28).

The calculation result and absolute value by the addition/subtraction circuit (28) are set in the registers (33) and (36) at timing 5. Then, period CF) is set to the above register (
35) and (36) to the above addition/subtraction circuit (2B)
, and the calculation (B-A) is carried out by the addition/subtraction circuit (28).
).

At timing 6, when the calculation result by the addition/subtraction circuit (28) is positive, the register (32)
Since the absolute value of the contents of is larger than the absolute value of the contents of the register (33), the contents of the register (33) are transferred to the register (32), and at the same time, the contents of the registers (30) and (26) are transferred to the register (32). ) and the contents of the register (27) are extracted and set in the register (38), and 1 is set in the indicator (40).

In addition, the third merging bit is added to this intercostal space (F) by the selector (20), and the output of the read-only memory (22) is sent to the registers (25) and (26) at timing 6. cent.

Similarly, the calculation process for the third merging bit is performed during periods (G) to (1), and the calculation result is set in the indicator (40) at timing 9.

Furthermore, the fourth merging bit is set at timing 9, and the arithmetic processing for this is performed from period (J) to (L).
Line 1. s, and sets the calculation result to the indicator (40) at timing 12.

Then, during the period (M), the selector (21) is switched to the indicator (40) side, and the selector (20) is switched according to the contents of this indicator (40), and the optimal merging selected at timing 13 is performed. The bits are supplied to the register (41). Also, at this time, the contents of the registers (32) and (3B) are the cumulative DS corresponding to the optimal merging bits described above.
V and polarity, set these values in the registers (29) and (30).

Furthermore, the contents of the register (41) are transferred to the register (42) at the next timing O, and the contents of the register (41) are transferred to the register (42) at the next timing O.
) and the above register (13
) are combined and a 17-bit signal is supplied to a shift register (43) for parallel-to-serial conversion. The contents of the shift register (43) are read out according to the system clock signal (Sc), the exclusive OR circuit (44) restores the sync pattern, and the contents are sent to the output terminal (45) via the flip-flop (45). 46).

In this embodiment, by resetting the registers (29) and (30) that hold the cumulative DSV and polarity every 98 frames, that is, every l subblock, the independent DSVO control n is performed for each subblock. Then, recording data is created in which merging bits of a bit pattern corresponding to the DSV value are inserted between the n (n=14) bits of data. Since the recorded data is controlled by an independent DSV on a sub-block basis, it can be recorded and reproduced while being managed individually as block data in which each sub-block is one sector.

One subblock (one sector) of data block thus obtained is recorded, for example, on an optical disk (101) as shown in FIG.

In FIG. 4, which schematically shows an enlarged view of the whole and a part of the data recording medium according to the present invention, an optical disk (10
In 1), a magneto-optical disk in which a perpendicularly magnetized film having a magneto-optic effect is formed on a transparent substrate is used as a recording medium, and a pre-group (102
) is used as a recording track (103), and for example, the above-mentioned CD obtained by the modulation circuit shown in FIG.
-Block data completed in 2 bytes according to the data format of the ROM is magneto-optically recorded on the recording track (103).

The recording track (103) has addresses whose track width is changed in a burst pattern at equally spaced positions corresponding to the synchronization signal (SYNC) part or the error correction signal (FCC) part in the data format of the CD-ROM. Areas (4) are provided, and address information of, for example, 19 bits is prerecorded in each address area (104) depending on the change in track width. The signal spectrum of the address information due to the change in track width is designed to have components above the servo band.

The optical disc (101) also has a lead-in area (107) on the inner circumferential side of the data area (6) where data is recorded.
) is provided, and lead-in information indicating the recording status of the data area (106) is provided in the lead-in area (107).
It is now recorded in .

As described above, an optical disc (lot) has a recording track (103) in which predetermined bits of address information are recorded in advance in each address area (104) by changing the track width.
In a disk device that uses a disk as a data storage, for example, each detector (A) and (B) as shown in FIG. 5 is used as an optical pickup for reading data.
, (C), (D), each output (SA), ( Ss).

The data signal (RF) can be detected as an addition output signal (SA + So + S (+ So) obtained by adding (Sc) and (So) in an adder (111), and
Each of the above-mentioned day tickers (A) and (B
), each output (SA), (sm) multiplier (112)
Multiplication output (SAM) by
, (D) and the multiplication output (SCD) from the multiplier (113) of (so) are subtracted by the subtracter (l1
4), that is, the subtracted output signal (S□-5C!l) that is the subtracted output signal (S□-5C!l), that is, the above-mentioned digital output signals (A) arranged in the width direction (Yi' direction) of the above-mentioned recording trunk (103).
Address information (^OR) can be detected as the push-pull outputs of the outputs (SA), (Ss), (Sc), and (So) of the outputs (SA), (Ss), (Sc), and (So) of the outputs (SA), (Ss), (So), and the outputs (SA), (Ss), and (So) of the outputs (SA), (Ss), (So), and the outputs (SA), (Ss), and (SO) of the outputs (SA), (Ss), (SO), and B), respectively.

In this optical disc (101), the recorded data is l
Recorded data subjected to independent DSV control on a sub-block basis can be recorded and reproduced by individually managing each sub-block as one sector of block data.

〔Effect of the invention〕

In the method of the present invention, merging bits with a bit pattern corresponding to the DSV value of the recording data are inserted between the n-bit data, and the DSV value is reset and inserted in units of predetermined data blocks. Data DS
V is controlled independently in units of data blocks, and recording data is written or recalled in units of data blocks. Furthermore, in the data recording medium according to the present invention, since the DSV of the recorded data is independently controlled by the data block level, even if recorded data is written or rewritten in data block units, the recorded data of other data blocks does not affect the content of

Therefore, according to the present invention, m-bit data is converted into n-bit data larger than this m-bit data, p-bit merging bits are inserted between these n-bit data, and these n-bit data A data recording method in which data is recorded by modulating such that the number of consecutive "0" bits in an alternating series of merging bits of p bits is at least a predetermined number d and at most a predetermined number greater than d. Furthermore, in a data recording medium such as a CD-WO or CD-RAM on which the above data is recorded, data can be written or rewritten in blocks, and data can be efficiently managed in blocks.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a modulation circuit used to carry out the method of the present invention, FIG. 2 is a schematic diagram showing the relationship between each signal in the modulation circuit, and FIG. 3 similarly shows the operation of the modulation circuit. FIG. 4 is a schematic plan view of an optical disc to which the data recording medium according to the present invention is applied, and FIG. 5 is a diagram showing the optical and linkup configuration for reading data from the optical disc. It is a schematic diagram. FIG. 6 is a schematic diagram showing the data format of a compact disc (CD), and FIG. 7 is a schematic diagram showing the data format of a CD-ROM. 101...Optical disc 103...Recording trunk

Claims (2)

[Claims] (1) Convert m-bit data to n-bit data larger than this m-bit data, and p
In addition to inserting a merging bit of bits, the number of consecutive "0" bits in the alternating series of these n-bit data and p-bit merging bits is a predetermined d or more and k larger than this d. In a data recording method that records data by modulating it as follows, digital sum variation (DSV:
A data recording method characterized by inserting merging bits of a bit pattern according to the value of the DSV (Digital Sum Variation) between the n-bit data, and resetting the DSV value in units of predetermined data blocks. (2) m-bit data is converted to n-bit data larger than this m-bit, and p-bit merging bits of a bit pattern according to the DSV value of the recording data are inserted between the n-bit data. , modulated such that the number of consecutive "0" bits in the alternating series of n-bit data and p-bit merging bits is at least a predetermined number d and at most k greater than this d, A data recording medium on which data is recorded by resetting the DSV value in units of predetermined data blocks.