RU2089045C1 - Pulse train decoder - Google Patents

Abstract

FIELD: computer engineering; coding data blocks. SUBSTANCE: in coding data blocks, the latter having, for example, m data bits are converted into blocks of n bit channels (n > m). Blocks of thus obtained data bits should satisfy, for example, condition of (d, k)-constraints. Number of sequential zeroes in (d,k)-constrained trains is limited by d minimum and k maximum of zeroes placed between each pair of sequential ones. According to invention, separation block is inserted between each block containing n data bits. If format is not assigned by (d,k)-constraints, bit separation is chosen so that low-frequency spectrum and, particularly, DC current unbalance were as low as possible. EFFECT: reduced low-frequency spectrum and DC current unbalance. 2 cl, 8 dwg

Description

The invention relates to the creation of pulse sequence decoders used to process sequences of bits of binary data that are decoded into a sequence of bits of binary channels, wherein the sequence of data bits is divided into sequential private blocks, each of which contains m information bits. These blocks are encoded into partial blocks of (n ₁ + n ₂ ) channel bits (n ₁ + n ₂ > m). Each of these channel bit blocks contains a block n ₁ information bits and a block n ₂ dividing bits, so that each partial block of information bits is always separated by one block of dividing bits. Two consecutive channels of bits of the first type, type "1", are separated by at least d consecutive bits of the second type, type "0", and the number of consecutive channel bits of the second type does not exceed k. In digital transmission or in magnetic or optical recording / reproduction, information consists mainly of symbols, in particular binary (binary) symbols. One character, for example, “1,” can be written in the NRZ-M code as a transition between two states of magnetization or focusing on a magnetic disk, tape, or optical disk. Another character "0" is written as the absence of such a transition.

 As a rule, restrictions are imposed on sequences of characters. For example, some systems require self-tapping. This makes it necessary to have sufficient intervals in symbol sequences to generate synchronization signals in them. A further requirement may be that some symbol sequences should not appear in information signals, since these sequences are intended for special purposes, for example, for synchronization. Simulation of synchronization sequences by information signals violates the uniqueness of the synchronization signal. Further, a requirement may arise that the transitions do not occur too close to each other so that intersymbol interference does not occur.

In the case of magnetic or optical recording, restrictions can be associated with the density of information on the recording medium, since with increasing a certain minimum distance between two consecutive transitions on the recording medium, the corresponding minimum time interval (T _Min ) of the recorded signal increases and, accordingly, the information density increases. In addition, the minimum bandwidth (B _Min ) correlates with the minimum distance T _Min (B _Min 1/2 T _Min ).

 When using information channels that do not conduct direct current, as is usually the case with magnetic recording, there is a requirement that the character sequences in the information channels contain the smallest possible component of the direct current.

Decoding of the genus described in the first paragraph of the present description is disclosed in the literature [1]
This article relates to block codes based on q-bit character blocks limited in d, k or (d, k) q-blocks, which blocks satisfy the following requirements:
a) restriction on d: two characters of type "1" are separated by a chain of at least d consecutive characters of type "0",
b) restriction on k: the maximum length of a string of characters of type "0" is k.

A sequence of, for example, binary data bits is distributed into consecutive adjacent blocks, each of which has m data bits. These blocks of m data bits are encoded into blocks of n information bits (n> m). Since n> m, the number of combinations with n information bits exceeds the number of possible blocks of data bits (2 ^m ). If, for example, blocks of information bits are superimposed with a restriction on d before transmission or recording, the location of 2 ^m blocks of data bits in the same number of 2 ^m blocks of information bits (out of a possible number of 2 ⁿ blocks) is such that only those blocks of information bits that satisfy the requirement that is superimposed.

При связывании блока информационных бит в некоторых случаях не удается удовлетворить требованию (в примере, по d-ограничению) без принятия дополнительных мер. В статье предлагается включать разделительные биты между блоками информационных бит. Для случая d-ограничения кодирования достаточен один блок разделительных бит, содержащих d-бит "0" типа. В предыдущем примере, где d=1, один разделительный бит (один нуль) достаточен. В этом случае каждый блок из 3-х бит кодируется 5-ю (4+1) канальными битами. Этот метод кодирования отличается тем недостатком, что имеет значительную низкочастотную составляющую в спектре потока канальных бит (включающую и постоянный ток). Другим недостатком является сложность элементов преобразователя кодов, в особенности демодулятора.It is known from [1] how many different blocks of information bits can have depending on the length of the block (n) and the requirements of the constraint on d. So, there are 8 blocks of information bits having a length n 4 provided that the minimum distance is d 1. Therefore, blocks of data bits having a length m 3 (2 ³ 8 data words) could be represented by blocks of information bits having a length n 4, wherein two adjacent symbols of type “1” in blocks of information bits will be separated by at least one symbol of type “0”. For this example, the encoding will be like this (a two-way arrow indicates the transition of one block to another and vice versa):

When linking a block of information bits in some cases, it is not possible to satisfy a requirement (in the example, by d-constraint) without taking additional measures. The article proposes to include separation bits between blocks of information bits. For the case of d-coding restriction, one block of dividing bits containing a d-bit of type "0" is sufficient. In the previous example, where d = 1, one dividing bit (one zero) is sufficient. In this case, each block of 3 bits is encoded by 5 (4 + 1) channel bits. This encoding method has the disadvantage that it has a significant low-frequency component in the spectrum of the channel bit stream (including direct current). Another disadvantage is the complexity of the elements of the code converter, especially the demodulator.

 Regarding the first drawback, it is indicated in [2] that the imbalance of the direct current (d, k) -bounded codes can be limited by interconnections of channel bit blocks using so-called inverting or non-inverting connections. The sign of the contribution of the current block of channel bits to the DC imbalance is selected to reduce the DC imbalance of the previous block of channel bits. However, with a (d, k) -bounded code, blocks of information bits can be formed without conflict with (d, k) -limitations, so bit separation is not required.

 The aim of the invention is to simplify the decoder.

 This goal is achieved by the fact that the pulse sequence decoder containing the code converter, the outputs of which are the decoder outputs, includes a shift register, a pulse counter, a clock generator and an OR element, the output of which is connected to one of the inputs of the shift register, the outputs of which are connected to the corresponding inputs of the AND element, the second input of the OR element is combined with the input of the delay element and is the input of the decoder, the output of the element and the driver is connected to the start stroke pulse counter whose output is connected to the clock input of storage register, the shift register outputs are connected to corresponding transducer input codes, clock inputs of the shift register and the pulse counter are combined and connected to the output of the synchronization element that is directly connected to an input of the decoder.

 In FIG. 1 shows some bit sequences to illustrate the implementation of an encoding format; 2, some other channel coding format embodiments that should be used to reduce DC imbalance; figure 3 block diagram of the coding; in Fig.4 block synchronization bits; 5 is a diagram of a demodulator for decoding data bits; 6 is a diagram of the implementation of the pulse shaper; 7 is a diagram of the implementation of the frame format; on Fig proposed device.

 Corresponding elements in the drawings are denoted by the same reference numerals.

 Figure 1 shows some bit sequences for illustrating a method for encoding a binary data bit stream (Fig. 1a) into a binary channel bit stream (Fig. 1b). The data bit stream is divided into consecutive VD blocks. Each block of data bits contains m data bits. For example, in the further presentation, m = 8 was used; other values of m are also possible.

 For many reasons, such a sequence of bits is not suitable for direct optical or magnetic recording.

Such bit sequences are not very suitable for direct optical or magnetic recording for several reasons. Namely, when two characters of type “I” immediately follow each other and are recorded, for example, on a recording medium in the form of transitions from one direction of magnetization to another, or as a transition to a dimple, these transitions should not be too close to each other due to their mutual influence. This limits the density of information. At the same time, the minimum frequency band B _Min , which is required to transmit or record a bit stream, increases if the minimum distance T _Min between successive transitions B _Min = 1 / 2T _Min ). Another requirement that is often imposed on data transmission and optical or magnetic recording systems is that the bit sequences must have enough transitions to isolate the synchronization signal from which the synchronization can be performed. A block in which m zeroes, before which, in the worst case, passed a block ending with many zeros, and after which there is a block with many zeros at the beginning, would make it difficult to isolate synchronization pulses.

 Information channels that do not allow direct current, such as magnetic recording channels, must further satisfy the requirement that the data stream to be recorded has a DC component as small as possible. For optical recording, it is desirable that the low-frequency part of the data spectrum be as suppressed as possible for servo control. In addition, demodulation is simplified when the DC component is relatively small.

For the above and other reasons, the so-called channel coding of data bits is performed before transmitting them over the channel or before recording them. In the case of block coding (literature D (1)), blocks of data bits, each of which contains m bits, are encoded as blocks of information bits, each of which contains n ₁ information bits. FIG. 1 shows how a block of data bits BD _{i is} converted to a block of information bits BI _i . For example, the value of n _{1 is} chosen equal to 14, which is used in the further description and drawings. Since n _{1 is} greater than m, not all combinations that can be formed from n ₁ bits are used: those combinations that do not fit well with the channel used are discarded. So, in this example, you need to select only 256 layers from the possible number of more than 16,000 channel words or the required translation of one to one data words into channel words. Consequently, additional requirements can be imposed on channel words. However, such a requirement is that between two adjacent information bits of the first type “I” there would be at least d consecutive neighboring information bits of the second type “0” in the same block of n ₁ information bits. Table 1 on p. 439 of the literature D (1) shows how many such binary words are available, depending on the value of d. The table shows that for n ₁ 14 there are 277 words with at least two (d = 2) bits of type zero between adjacent bits of type "I". When coding blocks of eight data bits, which may be 2 ⁸ = 256 combinations into blocks of 14 channel bits, the restriction d = 2 can be satisfied with a margin.

However, connecting a chain of blocks of information bits BI _{i is} impossible without further measures, if the requirement of restriction on d applies not only within the block, but also between neighboring blocks. To eliminate this, literature D (1) suggests (p. 451) to include one or more separation bits between channel bit blocks.

It is easy to replace that if the number of dividing bits of the zero type is at least equal to d, then the constraint on d is satisfied. Figure 1 shows that the block of channel bits BC _i consists of a block of information bits BI _i and a block of separation bits BS _i . The block of separation bits includes n ₂ bits, so that the block of channel bits BC _i includes n ₁ + n ₂ bits. For example, take n ₂ = 3.

To make the generation of synchronization pulses as reliable as possible, an additional requirement will be that the maximum number of neighboring bits of type “0” between adjacent bits of type “I” within one block of information bits would be limited to a predetermined value k. In the example where m = 8, n ₁ 14 of the 277 words that satisfy the requirement d = 2, we can drop those words, for example, that have a very large value of k. It turns out that k can be limited to ten. Therefore, a set of 2 ⁸ (in the general case 2 ^m ) blocks of data bits of 8 bits each (in the general case m) is translated into a set of 2 ⁸ (generally 2 ^m ) blocks of information bits, which information bits were selected from 2 ¹⁴ (in the general case, 2 ⁿ¹ ) possible blocks of information bits, which is partially the result of the following conditions being imposed: d = 2 and k = 10 (in the general case, limited by d, k). There is still freedom in choosing which block of data bits to associate with which block of information bits. In the above literature D (1), the translation from data bits to information bits is uniquely defined and mathematically determined. Although you can basically use this translation, you should prefer another way of combining, which will be explained in more detail below.

Connection in a chain of BI _i channel words bounded further on by k _{i is} possible only, which is also true for d constraints, only when dividing blocks are inserted between the BI _i information bit blocks. In principle, you can use the same dividing blocks of n ₂ bits each, since the requirements of the restriction on d and k do not contradict each other, but rather complement each other. When, therefore, the sum of the number of bits of the zero type preceding this separation block exceeds the number of values following this separation block and the bits of the separation block itself exceed the value k, then at least one of the values of the bit of the zero type in the separation block must be replaced bit of a single type to separate a chain of zeros in a sequence, each of which is no more than k bits in length.

 In addition to their function of satisfying the requirements of the constraints on (d, k), the separation blocks may be in such a format that they can also be used to reduce DC imbalance. This is based on the understanding of the fact that for some connections of blocks of information bits a predetermined format of the block of separation bits is prescribed, but that in a large number of cases, either no requirements are imposed on the format of the block of separation bits, or these requirements are very limited. And the degree of freedom that arises in this way is used to reduce current imbalance.

The appearance and increase in DC imbalance can be explained as follows. The BI _I information bit block, as shown in FIG. 1b is recorded on a recording medium, for example, in the form of an NRZ-mark format (NRZ is non-reverse that zero, a record where the parameter has a positive and negative value, but does not have a zero value). In this case, the format “I” is marked by the transition of the parameter at the beginning of the corresponding bit cell and becomes zero if there is no transition in the record. The bit sequence shown in BI _I takes the form shown by the WF line, and in this form this sequence is recorded on the recording medium. This sequence has an imbalance in direct current, since for this sequence a positive level lasts longer than a negative one. A measure for DC imbalance, which is often used, is the digital amount, abbreviated as English d-es-vi. Taking the levels of the polygonal line wF +1 and -1, respectively, the di-es-vi is then equal to the current integral of the polygonal line wF, and is + 6T in the example shown in Fig. 1, if T is the length of the bit interval. If such sequences are repeated, the DC imbalance will increase. In general, this DC imbalance produces a zero line offset, which reduces the effective signal-to-noise ratio and, therefore, the reliability of detection of the recorded signal.

The block of separation bits BS _{i is} used to limit the imbalance in direct current as follows.

A block of data bits BD _i is currently being supplied. This block of data bits BD _{i is} converted into a block of information bits BI _i , for example, according to a table stored in memory. After that, a set of possible blocks of channel bits containing (n ₁ + n ₂ ) bits is formed. All these blocks have the same block of information bits (bit positions from 1 to 14 inclusive, fig. 1b), supplemented by possible bit combinations of the separation block n ₂ (bit positions 15, 16 and 17, fig. 1b). Therefore, in the example shown in FIG. 1b, a set of 2 ⁿ 2 8 channel bit blocks is obtained. After that, the following parameters of each of the possible blocks of channel bits are determined, in principle, in any sequence:
a) for a given possible block of channel bits, taking into account the previous block of channel bits, it is determined whether the restrictions on d and k are fulfilled with the format of this block of separation bits,
b) defining a dvs for a given possible block of channel bits.

 The first indication signal is generated for those possible channel bit blocks that satisfy the requirements of the d and k constraint. The choice of encoding parameters ensures that such an indication will be issued for at least one of the possible blocks of information bits. Finally, from the possible channel bit blocks for which the first indication signal was issued, that channel block block is selected which, for example, in the absolute sense has the smallest ds-vi. However, an even better way is to memorize the previous channel block blocks of the DBS and select from the blocks of channel bits to be transmitted the next time, such a block that will cause a decrease in the absolute value of the accumulated DSC. The word selected in this way is transmitted or recorded.

Fig. 2a schematically shows the sequence of blocks of channel bits BC _i-1 , BC _i , BC _{i + 1} , and these blocks have a predetermined number of bits (n ₁ + n ₂ ). Each block of channel bits has blocks of information bits, consisting of n ₁ bits, and blocks of separation bits BS _i-2 , BS _i-1 , BS _i , BS _{i + 1} . each consists of n ₂ bits.

In this embodiment, the DC imbalance is determined by several blocks, for example, as shown in FIG. 2a, by two blocks with channel bits BC _i and BC _{i + 1} . The DC imbalance is determined in the same way as described for the embodiment of FIG. 1, provided that possible superblock formats are generated for each superblock SBC _i , that is, information bit blocks for block BC _i and blocks BC _{i + 1} are supplemented with all possible combinations, which can be formed with n ₂ separation bits of blocks BS _i and block BS _{i + 1} . A combination that reduces DC imbalance is then selected from this set. This method has the advantage that the residual DC imbalance is more uniform, since more than one block of channel bits is previously considered and the intervention will be optimal.

An advantageous variant of this method has a distinctive feature in that the superblock SBC _i (Fig. 2a) is shifted by one block of channel bits only after the DC unbalance has been minimized. This means that the block BC _i (in FIG. 2a), which is part of the superblock SBC _i , is processed and that the subsequent superblock SBC _{i + 1} (not shown) contains blocks BC _{i + 1} and BC _{i + 2} (not shown), for which the above operation is carried out to minimize imbalance in direct current. Thus, the block BC _{i + 1} is part of both the superblock SBC _i and the subsequent block SBC _{i + 1} . Then it is quite possible that the (initial) selection of the separation bits in the BS _{i + 1} block made in the SBC _i superblock is different from the final selection made in the SBC _{i + 1} superblock. Since each block is examined several times (twice in this example), the DC imbalance and, therefore, the additional noise are further reduced.

FIG. 2b shows a further embodiment in which the DC imbalance is determined for several blocks at the same time (SBC _j ), for example, for the case of four blocks of channel bits BC _j ⁽¹⁾ , BC _j ⁽²⁾ , BC _j ^{( 3)} and BC _j ⁽⁴⁾ . Each of these channel bit blocks contains a predetermined number n ₁ information bits. However, the number of separation bits may be 2 for each block and 6 for block BS _j ⁽⁴⁾ . The determination of DC imbalance is performed similarly to that described for the embodiment of FIG. 2a.

 5 shows an embodiment of a demodulator that demodulates blocks of 8 data bits from blocks of 14 information bits. 5 shows a block diagram of a code converter demodulator.

The demodulator includes logic circuits AND from 17-0 to 17-51 inclusive, and each has one or more inputs. Each of the inputs is supplied with one of the 14 bits of information bit blocks, the inputs of the direct and inverting types. FIG. 5b shows in column C _i how this is done. Column 1 represents the smallest bit in position C _{1 of the} 14-bit information block, column 14 the highest bit C ₁₄ , and intermediate columns 2-13 inclusive, respectively, show the remaining bit positions according to their size. Lines 0-51 inclusively refer to the numbers of the logical circuits AND, that is, line 0 refers to the input format of the logical circuit AND 17-0, line 1 refers to the input format of the logical circuit And 17-1, etc. The symbol 1 in the i-th column of row j means that the j-th logic circuit And 17 is written through a non-inverting input with the content of the i-th bit position B ₁ . The symbol 0 in the i-th column of row j means that the j-th logic circuit And 17 is fed through the inverting input by the content of the first bit position (C _i ). Therefore, (line 0) the inverting input of the logic circuit And 17-0 is connected to the i-th bit position (C ₁ ), and the non-inverting input is connected to the fourth bit position (C ₄ ), line 1 is the non-inverting input of the logic circuit And 17-1 connected to the third position (C ₃ ), etc.

The demodulator further includes 8 logic circuits OR from 18-1 to 18-8 inclusive, the inputs of which are connected to the outputs of the logic circuits AND 17-0 - 17-51 inclusive. FIG. 5b shows in column A _i how this is implemented. Column A ₁ refers to the logic OR 18-1, column A ₂ refers to the logic OR 18-2. to and column A ₈ refers to OR 18-8. The letter A in the i-th column of the j-th row indicates that the output of the logic circuit And 17-j is connected to the input of the logic circuit OR 18-i.

 For logic circuits And 17-50 and 17-51, the circuit is changed as follows. The inducing outputs of both logic circuits AND 17-50 and 17-51 are each connected to the input of another logic circuit AND 19. The output of the logic circuit OR 18-4 is connected to another input of the logic circuit And 19.

 Each output of the logic circuits OR 18-1, 18-2, 18-3 and 18-5 18-8 inclusive, as well as the corresponding output of the logic circuit And 19 is issued to the output 20-i. A decoded block of 8 data bits, therefore, is available in parallel at these outputs.

 The demodulator shown in Fig. 5 can be performed alternatively in the form of a so-called programmable logic circuit assembly FPLA (field programmable loggie errey), for example, a Signetics type bipolar assembly 82S100 / 82S101.

 The demodulator shown in FIG. 5, due to its simplicity, is extremely suitable for read-only optical recording systems.

6 shows a pulse shaper. The received signal is fed to the input of terminal 21. The signal has the format NRZ-M (ark). This signal is directly fed to the first input of the OR element 22 and to the second input of the OR element 22 through the delay element 23. The so-called NRZ-I signal is received at the output of the OR element 22, which is fed to the input of the shift register 24. The shift register contains a certain number of sections, which corresponds to the number of bits contained in the block of synchronization bits. In the example used below, the shift register must contain 23 sections in order to accommodate the sequence 10000000000100000000001. Each tap is connected to the input of the AND element 25, which (input) can be inverting or non-inverting. When there is a synchronization sequence at the inputs of the And 25 element, a signal will be generated at the output 26 of this And element, which means the detection of synchronization pulses. Using this signal, the bitstream is divided into two blocks of (n ₁ + n ₂ ) bits in each. These blocks of channel bits are shifted one after another in a shift register. The most significant n ₁ bits are read in parallel and fed to the inputs of AND element 17, as shown in FIG. Less significant bits n _{2 are} not essential for demodulation.

 In FIG. 8 shows a device that is a combination of devices shown in the previous drawings. First of all, it contains a driver of clock pulses from elements 21-26. The element 26 is connected to the start input of the counter 29, while the shift in the shift register 24 is synchronized by the bit synchronization element 31, which is directly connected to the input of the decoder 21. As a result, each bit is advanced by one counter cell and the shift register is shifted by one bit . When the counter reaches state 17, it sends a clock pulse to storage register 30. Block 32 is the code converter shown in FIG. 5. Inputs C1.C14 and outputs 20-1-20-8 are shown. Upon receipt of a clock pulse, the storage register 30 stores the decoded bits for use in other equipment not shown.

The encoded signal, for example, can be recorded on an optical recording medium. The signal has the form shown in fig.1b. The signal is fed to a storage device in a spiral information structure. The structure consists of a number of superblocks, for example, of the type shown in FIG. 7. The superblock SB _i includes a block of synchronization bits SYN _I , which is made as shown in figure 4, and a number (33 in embodiment) of blocks of channel bits, each of which has (n ₁ + n ₂ ) bits BC ₁ , BC ₂ .BC ₃₃ . Channel bits of type "I" are represented by a transition in the recording medium, for example, a transition from the absence of a hole to a hole; a channel bit of type "0" is reflected on the recording medium by the absence of a transition. The spiral information path is subdivided into unit cells, bit cells. On the recording medium, these bit cells form a spatial structure, each corresponding to the division in time (period of one bit) of the channel bit stream.

 Regardless of the content of the information and separation bits, a large number of details can be seen on the recording medium. For media, the k constraint means that the maximum distance between two adjacent transitions will be (k + 1) bit cells. The longest hole (or absence of a hole) thus has a value (k + 1) of bit cells. A restriction on d means that the minimum distance between two adjacent transitions is d + 1. The shortest hole (or the absence of a hole) will thus have a length (d + 1) of bit cells. Further, at equal distances there will be pits of maximum length, after which (or before which) there will be no pit of maximum length. This structure is part of a block of bit synchronizations.

In a preferred embodiment, k 10, d 2, and superblock SB _i contain 588 channel bit cells. Superblock SB _i includes a block of synchronization bits of 27 bit cells and 33 blocks of channel bit cells, each has 17 (14 + 3) channel bit cells.

 A modulator, a transmission channel, for example, of an optical recording medium, and a demodulator can together be part of a system, for example, a system for converting analog information (music, speech) into digital information, which information is recorded on an optical recording medium. Information recorded on the recording medium (or a copy thereof) can be reproduced by means of a device that is suitable for reproducing information that has been recorded on the information medium.

 The conversion circuit includes, in particular, an analog-to-digital converter for converting the analog signal (music, speech) to be recorded into a digital signal of a predetermined format (source encoding). In addition, the conversion scheme may include part of an error correction system. In the conversion circuit, the digital signal is converted to the desired format by which errors, which are especially encountered during reading from the recording medium, can be corrected in the device for reproducing the signal. An error correction system that is suitable for this purpose is disclosed in a patent application filed by Sony Corporation in Japan under the number 14539 on May 21, 1980 and June 5, 1980, respectively.

 The digital and error-protected signal is then supplied to the modulator described above (channel coding), for conversion into a digital signal that is adapted to the properties of the channel. Additionally, a synchronization pattern is supplied and the signal is reduced to the correct frame format. The signal obtained in this way is used to generate a control signal, for example, for a laser (NRZ-mark format), by means of which a spiral structure of information is applied to the recording medium in the form of successive holes and their absence of a predetermined duration.

 The recording medium or its copy can be read using a device for reproducing bits of information received from the recording medium. For this purpose, the device has a demodulator, which has already been described in detail, the decoding part of the error correction system and a digital-to-analog converter to restore the form of the analog signal that has been fed to the conversion circuit.

Claims (2)

 1. A pulse sequence decoder containing a code converter, the outputs of which are the outputs of a decoder, characterized in that it contains a shift register, a pulse counter and a pulse shaper containing an OR element, the output of which is connected to the input of the shift register, the outputs of which are connected to the corresponding inputs of the element And moreover, the first input of the OR element is connected directly, and the second input of the OR element is connected through a delay element to the input of the decoder, the output of the And element of the shaper and pulse is connected to the start output of the pulse counter, the output of which is connected to the clock input of the storage register, in which the outputs of the shift register are also connected to the corresponding inputs of the code converter, the synchronization inputs of the shift register and the pulse counter are combined and connected to the output of the synchronization element of the single-bit register, which directly connected to the decoder input.  2. The decoder according to claim 1, characterized in that the code converter contains the first and second gupps of the AND elements, the first eighth OR element and the AND element, the direct inputs of the AND elements of the first and second groups are connected to the corresponding inputs of the OR elements, the inverse outputs of the elements AND the second groups are connected respectively with the first and second inputs of the AND element, the third input of which is connected to the output of the fourth OR element, the outputs of the OR elements, except for the fourth, and the output of the AND element are the corresponding outputs of the converter, corresponding to The inputs of the elements of both the first and second groups are combined and are inputs of the code converter.

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