NL8004028A - METHOD FOR CODING A SERIES OF BLOCKS OF BILINGUAL DATA BITS AS A SERIES OF BLOCKS OF DUAL CHANNEL BITS AND APPARATUS FOR DECODING THE DATA CODED BY THE METHOD. - Google Patents

Description

'"" "" "" "" "..........." i 5 ». r PHQ 80.007 1 NV Philips' Gloeilampenfabrieken in Eindhoven" Method for coding a series of blocks of binary data bits as a series of blocks of binary channel bits and apparatus for decoding the data bits encoded by the method ".

A. Background of the invention.

A (1) Field of the invention.

The invention relates to a method for encoding a series of binary data bits into a series of bilingual channel bits, which series of data bits is divided into contiguous and consecutive blocks of each m data bits, which blocks are encoded in successive blocks of ( n ^ + n2) channel bits (n1 + n2> m), which blocks of channel bits each contain a block of nj information bits and a block of n2 separation bits such that successive blocks of information bits are separated by one block of separation bits each, two consecutive channel bits of a first type, type "1", are separated by at least d consecutive and contiguous bits of a second type, type "0" and the number of consecutive and contiguous channel bits of the second type is at most k.

15. In digital transmission or magnetic and optical recording / reproducing systems, the information to be transferred or to be recorded is usually in the form of a series of symbols. These symbols together form the (often bilingual) alphabet. In case it is a bilingual alphabet (furthermore this alphabet is represented by the symbols "1" and "0") the one symbol, for example the "1", according to the NRZ-mark code, can be placed on the magnetic plate, band or optical plate as a transition between two states of magnetization or focus. The other symbol, the "0", is fixed by the absence of such a transition.

25 In practice, due to certain system requirements, restrictions are imposed on the sequences of symbols that may occur. For example, in some systems the requirement of self-clocking is imposed.

This means that the sequence of symbols to be transmitted or to be recorded must contain enough transitions to generate a clock signal required for detection and synchronization from the sequence of symbols. Another requirement may be that certain symbol sequences in the information signal should be avoided because these sequences are reserved for special purposes, for example as a synchronization sequence. Imitation 800 4 0 28 FHO 80.007 2 * * tation of the sync sourceization sequence by the information signal destroys the uniqueness of the sync signal and thus its suitability for that purpose. A further requirement may be not to make the transitions follow too closely to limit the intersymbol interference.

In the case of magnetic or optical recording, this requirement can also be related to the information density on the record carrier. After all, if at a given minimum distance between two successive transitions on the record carrier the corresponding carlo-corresponding minimum time interval (T. N) of the signal to be recorded can be increased, the information density is increased to the same extent. The minimum bandwidth (Bmir |) required is also related to the minimum distance T. between transitions (B. = -) minus 15 If use is made of information channels that do not transmit DC current, as is often the case with magnetic recording channels, this leads to the requirement that the symbol sequences in the information channel have the least possible (or possibly no) DC component. contain.

A (2) Description of the prior art.

A method of the type described in the opening paragraph is known from reference D (1). The article concerns block coding, based on d-, k- or (d, k) - bounded q-numbered block symbols, which blocks meet the following requirements: (a) d-bounded: two type "Τ" symbols are separated by a series of at least d consecutive type "0" symbols, (b) k-limited: the maximum length of a series of consecutive symbols of type "0" is k.

For example, a series of binary data bits is divided into contiguous and consecutive blocks of m data bits each.

These blocks of m data bits are encoded in blocks of n information bits (n> m). Because n> m, the number of combinations with n. information bits greater than the number of possible blocks of data bits (2). If the requirement of, for example, d-limits is imposed on the blocks of information bits to be transferred or registered, the mapping of the block-35 data bits on also 2111 blocks of information bits (from a possible number of 2n blocks) is chosen such that only cut on those blocks of information bits that meet the set requirement.

Table I on page 439 of reference D (1) shows 800 4028 i 1c PHQ 80.007 3 how many different blocks of information bits there are, depending on the length of the block (s) and the requirement for d. For example, there are 8 blocks of information bits with a length n = 4 under the condition that the minimum distance d = 1. Therefore, blocks of data bits with a length m = 3 3 5 (2 = 8 data words) could be represented by blocks of information bits with a length n = 4, wherein in the blocks of information bits two consecutive type "1" symbols are separated by at least one type "0" symbol. The coding is then for this example (the character <- * · stands for displaying from one block to another and vice versa) ï 10 000 0000 001 0001 010 0010 011 0100 100 0101 15 101 1000 110 <- »1001 111« - »1010.

When the information words are concatenated, however, in some cases the stated requirement (the d requirement in the example 20) cannot simply be met. In the said article it is proposed to include separation bits between the blocks of Information bits. In the case of d-limited encoding, a block of "0" type separation bits containing d bits is sufficient. In the example given above with d = 1, one separation bit (one zero) is therefore sufficient. Each block 25 of 3 data bits is then encoded with 5 (4 + 1) channel bits.

A drawback of this coding method is that the share of the low frequencies (including d-c) in the frequency spectrum of the stroon channel bits is quite high. A further drawback is that the code converters (modulator, demodulator) and in particular the demodulator are complicated.

With regard to the first objection, it should be noted that in reference D (2) it is indicated that the DC unbalance of (d, k) -coded encodings can be limited by using the blocks of channel bits by a so-called inverting or a non-inverting link. connections. Thus, the contribution of the current block of channel bits to the DC unbalance is chosen to reduce the DC unbalance of the previous blocks of channel bits. However, this concerns a (d, k) -limited coding of which the blocks can be contiguous 800 0 0 28 PHQ 80.007 4 Γ Γ *% mation bits without conflicting with the (d, k) requirement, so that the addition of separation bits is therefore unnecessary.

B. Summary of the invention.

The object of the invention is to provide a method of the type mentioned in the opening paragraph for encoding a series of binary data bits into a series of binary channel bits that improves the low-frequency spectrum properties of the signal to be derived from the channel bits and which method provides a simple demodulator.

The method according to the invention is characterized in that the method comprises the following steps: 1. converting blocks, containing m bits, data bits into n, bit-containing blocks of information bits; 2. generating a set of possible sequences of channel bits, which sequences each contain at least one block of information bits and one block of separation bits and which possible sequences each contain the blocks of information bits supplemented with one of the possible bit combinations of the blocks of separation bits; 3. determining the DC unbalance of each of the possible sequence of channel bits determined in the previous step; 4. determining for each of the possible sequences channel bits of the son of the number of the separation bits and the number of consecutive and successive information bits of the type "0" immediately preceding a bits of the type "1" and the son of the number that follows a bit of type "1", which bit is part of one of the blocks of separation bits, and the son of the number of separation bits and the number of consecutive and successive information bits of "0" type immediately preceding and following on that block of separation bits; 5. generating a first indication signal for those channel bit sequences for which the values of the sums determined in the previous step are greater than 2d and at most equal to k; 6. Selecting from the channel bit sequences which led to the first indication signal of that channel bit sequence which minimizes the DC imbalance.

C. Brief description of the drawings.

The exemplary embodiments of the invention and their advantages will be explained in more detail with reference to the drawings. Thereby 800 4028 H EHQ 80.007 5 * ï.

shows:

Figure 1 shows some bit sequences illustrating an embodiment of the encoding format according to the invention;

Figure 2 shows some further embodiments of the format of the channel coding as used in the reduction of the DC balance according to the invention;

Figure 3 shows a flow chart of an embodiment of the method according to the invention;

Figure 4 illustrates a block of synchronization bits 10 for use in the method according to the invention;

Figure 5 shows an embodiment of a demodulator according to the invention for decoding the data bits encoded according to the method.

Figure 6 shows an exemplary embodiment of the means for detecting a sequence of synchronization bits according to the invention;

Figure 7 shows an exemplary embodiment of a frams format applicable to the method according to the invention.

Corresponding elements in the figures are indicated by the same reference symbols.

20 25 30 35 800 4028 * * FHQ 80.007 6 i D. References (1) Tang, DT, Bahl, LR, "Block codes for a class of constrained noiseless channels", Information and Control, Vol 17, nr. 5, Dec .

1970, pp. 436-461.

5 (2) Patel, A.M., "Charge-constrained byte-oriented (0.3) code", IBM

Technical Disclosure Bulletin, Vol 19, No. 7, Dec. 1976, pp. 2715-2717.

E. Description of the embodiments.

Figure 1 shows some bit sequences illustrating the method of encoding a series of binary data bits (Figure 1a) into a series of binary channel bits (Figure 1b). The series of data bits is divided into contiguous and consecutive blocks BD; Each block of data bits contains m data bits. By way of example, the choice m = 8 will be used in the further description and in the figures. However, the corresponding applies to any other value of m. A block of m data bits BD ^ generally contains one of 2111 possible bit sequences.

Such bit sequences are less suitable for direct optical or magnetic recording for various reasons. Namely, if two data symbols of the type "1", which, for example, are recorded on the record carrier as a transition from one magnetization direction to the other or as a transition to a dimple, immediately follow each other then these transitions can be related to each other. with the mutual influence not to be situated too close to each other. The information density is thereby limited. Also, the minimum bandwidth B becomes. which is required to transfer or register the bitstrcm over min. increased If the minimum distance Tmin between consecutive transitions (B ^ = 1 / (2Tmin) is small. Another requirement that is often made in systems for data transmission and optical or magnetic recording is that the bit sequences have enough over-30 transitions to recover from the transmitted signal a clock signal capable of achieving synchronization A word with m zeros, in worst case cases, preceded by a word ending qp a number of zeros and followed by a word beginning with a number of zeros would compromise the clock extraction.

In addition, information channels that do not transmit direct current, such as magnetic recording channels, are required to have the data stream to be recorded contain as little direct current component as possible. With optical recording it is desirable that the low-frequency part 300 40 28 1 t PHQ 80.007 7 of the data spectrum be suppressed as well as possible, in connection with the servo controls. In addition, demodulation is simplified if the DC component is relatively small.

For the above and other reasons, so-called channel coding 5 is applied to the data bits before transmitting or registering them via the channel. In block encoding (ref. D (1)), the blocks of data bits, each containing m bits, are encoded as blocks of information bits, each containing n ^ bits of information. Figure 1 shows how the block of data bits DB ^ is converted into a block of information bits BI ^. By way of example, the choice n.j = 14 will be used in the further description and in the figures. Since n-j is greater than m, not all combinations which can be formed with n-bits are also used: those combinations which only fit the channel to be used are not used. Thus, in the example given, of the more than 16,000 possible channel words, only 256 words need to be selected for the required one-to-one mapping of data words to channel words. Therefore, some requirements can be imposed on the channel words. A requirement is that between two consecutive information bits of a first type / type "1" within the same block of nj information bits at least d consecutive and contiguous information bits of a type, the type "O" are located. page 439 of reference D (1) shows how many bilingual words there are depending on the value of d. The table shows that for n ^ = 14 there are 277 words with at least two (d = 2) bits of the type "0" between consecutive bits (of the

O

25 type "1"). When coding blocks of eight data bits, of which 2 = 256 combinations can occur, as blocks of 14 channel bits, the requirement d = 2 is amply met.

Connection of the blocks of information bits BL is not, however, readily possible if the same requirement of d-limited is imposed. not only within a block of n <| bits but also counted beyond the boundary of two consecutive blocks. For this purpose, it is proposed in reference D (1) (p. 451) cm to include one or more separation bits between the blocks of channel bits. It is easy to see that if at least a number of "0" type separation bits are included that are equal to d, then the requirement of d-bound is met for the entire sequence of channel bits. Figure 1 shows that a block of channel bits B (k consists of the block of information bits and a block of separation bits. The block of separation bits contains bits, so that the block 800 4028 PHQ 80007 contains 8 channel bits BCi + n2 bits. For example, in the further description and in the figures, unless otherwise indicated, the choice n2 = 3 is used.

In order to make clock generation as possible as possible, the requirement can also be imposed that the maximum number of type "o" bits that may continuously occur between two consecutive type "1" bits within one block of information bits is limited to a given value k. Thus, in the example m - 8 and n ^ = 14 given, those words which have a very high value for k can be eliminated from the 277 words satisfying d = 2. It turns out that k can be limited to 10. Therefore, a set of 8 τ-η of 2 ° (general T) blocks of data bits of 8 bits each (general nt) 8 is now mapped to a set of also 2 (general 2) blocks information bits which information bits have been selected from 214 (generally 2n1) possible blocks of information bits, partly by setting the requirement and d = 2 and k = 10 (generally d, k - bounded). The association of each of the blocks of data bits with one of the blocks of data bits is in itself still free to choose. In said reference D (1), the translation of data bits to data bits is unambiguously determined in mathematically closed form. While this translation is useful in principle, as will be further explained, another association is preferred.

Concatenation of the additionally k-bounded channel words BL · is, also as was the case for only d-bounded blocks, only possible if separating blocks are arranged between the blocks of information bits BL ·. In principle, the same separation blocks of each n2 bits can be used for this purpose, because the requirements d - limited and k - limited are not set but rather are complementary. Therefore, if the son of the number of bit values of the type "0" going before-30 on a given separation block, the number of qp following that separation block and the n2 bits of the separation block itself exceed the value k, then at least one of the bit values of the type "0" of the sizing block to be replaced by a bit value of the type "1" in order to break the series of zeros qp into strings each of which is at most k long.

In addition to ensuring that the requirements of (d, k) boundary are met, the partition blocks can be dimensioned so that they can be additionally used for the mini 800 4028 EBQ 80.007 9 t

* V

malformation of the DC balance. This is based on the insight that, although for some concatenations of blocks of information bits, a specific format of the block of separation bits is prescribed, but that in a large number of cases there are either no requirements or only 5 limited requirements for the format of the block of separation bits. The space thus created is used to minimize the DC imbalance.

The emergence and accretion of the DC imbalance can be explained as follows. The block of information bits B1 according to FIG. 1b is recorded on the record carrier in the form of an NRZ mark format, for example. In this format, a "1" is marked by a transition at the beginning of the respective bit cell and an "O" is registered as no transition. The bit sequence shown in Blh then assumes a form represented by WF. which form this bit sequence is recorded on the record carrier. This sequence has a DC inconvenience because in the present sequence the positive level exceeds the negative level in length.

A measure that is often used for the DC balance is the digital sum value, abbreviated d.s.v. The d.s.v. is, assuming that the levels of the waveform WF +1 resp. -1, then equal to the running integral of the waveform WF and is shown in FIG. 16 shown + 6T, where T is the length of one bit interval. If such sequences are repeated, the DC imbalance will grow.

This DC unbalance generally results in a base-25 line movement in Bet and reduces the effective signal-to-noise ratio and thus the reliability of the detection of the recorded signals.

The block of separation bits BS ^ is used to limit the DC imbalance as follows. At a given moment a block of data bits BD ^ is offered. This block of data bits BD ^ is converted, for example, by means of a table stored in a memory into a block of information bits B1. Then, a collection of possible (n ^ + n2) bits containing blocks of channel bits is generated. These blocks all contain the same block of information bits (bit cells 1 through 14,

Fig. 1b) supplemented with the possible bit combinations of the n2 separation 35 bits (bit cells 15, 16 and 17, Fig. 1b). Therefore, in the example of FIG. 1b a collection consisting of 2n2 = 8 possible blocks of channel bits. The following parameters of each of the possible blocks of channel bits are then given, in a random arbitrary 800 4028

Jr «r:« EHQ 80.007 10 sequence, determined: a) determine whether for the relevant possible block channel bits, seen. the preceding block of channel bits, the requirement of d-bounded and the requirement of k-bounded does not conflict with the format of the present block of separation bits; b) determine what the d.s.v. is for the relevant possible block of channel bits.

For those possible blocks of channel bits, which do not conflict with the requirement of d-bounded and k-bounded, a first indication signal is generated. The selection of the encoding parameters where it is ensured that at least one of the possible blocks of information bits such an indication signal is generated. Finally, from the possible blocks of channel bits for which a first indication signal has been generated, for example, the block of channel bits is selected which, in absolute value, has the smallest d.s.v. has. A better method is however the d.s.v. from the previous blocks of channel bits and select from the blocks of channel bits that are eligible as sequential feeds the block that the accumulated d.s.v. in absolute value will decrease. The word thus selected is transferred or registered.

An advantage of this method is that the separation bits, which are already necessary for other purposes, can also be used in a simple manner to limit the DC imbalance. A further advantage is that the intervention in the signal to be transmitted is limited to the blocks of separation bits and does not extend to the blocks of information bits (apart from the polarity of the waveform to be transmitted or recorded). The demodulation of the read out, recorded signal then only needs to relate to the information bits; the separation bits can be disregarded.

Some further embodiments of the method are shown in FIG. 2 is shown. Fig. 2a schematically shows the series of blocks of channel bits ..., BCt, BCt, ... which blocks contain a given number of (n ^ + n2) bits. The blocks of channel bits contain blocks of information bits each of n ^ bits, and blocks of separation bits ... BS ^ _2, BS ^ _ ^, BS ^, Bt + .j ... of n2 bits each.

The DC monbalance is determined in this exemplary embodiment over several blocks simultaneously, for example as in Fig. 2a is shown over two blocks of channel bits BCt and BCt + .j.

800402a PHQ 80.007 11

The DC monbalance is determined in a manner similar to that described for the exemplary embodiment of FIG. 1 with the proviso that per superblck SBCi the possible formats of super-blocks are generated, ie the blocks of information bits for block 5 BCk and block BCi + .j are supplemented with all the possible caribations which are made with the separation bits of block BS ^ and block BS ^ +. ^ to be formed. The combination that minimizes the DC unbalance is then selected from this collection. An advantage of this method is that the residual DC monbalance has a more uniform character, because it is considered which intervention is optimal over more than one block of channel bits.

Fig. 2b shows a further exemplary embodiment where the DC unbalance is determined over several spots simultaneously (SBCj), for example as in FIG. 2b is shown over four blocks of 15 channel bits BCj ^, BCj ^, BCj ^ and BCj ^. These blocks of channel bits each contain a given number of n ^ information bits. However, the number of separation bits containing the blocks of separation bits BSj ^, BSj ^, BSj ^ and BSj ^ is not the same for every block of channel bits. For example, the number of information bits can be 14 and the number of separator bits 20 for the blocks BSj, BSj ^ and BSj ^ can be 2 for each and for (41 block BSj for the number 6). Determining the DC balance separated similarly as described for the exemplary embodiment of Fig. 2a.

An advantage of this method - in addition to the aforementioned advantages, which also apply to this - is that the availability of a relatively long block of separation bits increases the possibilities of limiting the DC monbalance. Specifically, the residual DC monbalance of a series of channel bits in which each block of channel bits contains an equal number of, for example, 3 bits is greater than the residual DC mono balance of a series of channel bits whose blocks of separation bits contain an average of 3 bits divided into 2-2 -2-6 bits.

It is noted that the time sequences of functions and associated states of the method described are realized in universal sequential logic circuits such as commercially available microprocessors with associated memories and peripheral equipment. A flow chart of such a realization is 8004028 I t PHQ 80.007 12 shown in FIG. 3. The inscriptions of the geanetric figures explaining the functions and states of the time coding method include the following explanatory texts.

Column A shows the reference symbol, column B the inscription and column C shows the text that explains the corresponding geometric figure.

A B _ [_ C_ 1 DSV: = 0; The digital sum value (d.s.v.) of the pre-i: = 0; Going blocks of channel bits are given the value zero at the start of the method. The first d ± a word BD is given the rank number i = 0. Continued with geometric figure 2; 2 BD ^ From a memory, the block of data bits of m bits with the rank number i is chosen. 15 is continued with geometric figure 3; 3 BL · (BD ^) The block of data bits with the rank nuirmer i (BD ^) is converted using one table stored in memory in a block of information bits of n bits (BI.); continued with geometric figure 4; 4 j: = 0 A parameter j is initialized to a value of 0; the parameter j is the rank number of one of the q blocks of channel bits of n ^ -m ^ bits that may be eligible for transmission or registration; continued with geometric figure 5; 5 j: = j + 1 The parameter j is incremented by 1; continued geometric figure 6.

6 y ^ Q? If the relevant parameters of all Q possible blocks of channel bits 30 'have been determined, the operation which is indicated with geometric figure 13 is continued. In geometric figure 6 this is indicated by the connection N. If j ^ Q, then the operation which is indicated by geometric figure 7 is continued; 7 BCp: = ΒΙ £ Η3ςΡ your possible block of channel bits BCh-3 is formed by filling the block of information bits BL at 800 40 28 PHQ 80.007 13 with the combination of the block separating bits BS- ^; continued with geometric figure 8; 8 DSV - * =? The d.s.v. of your possible block of channel bits 5 is determined; continued with geometric figure 9; 9> kj ^? It is tested whether the possible block channel bits, when connected to the previous block channel bits BCh ^, meets the k-bound 10. If this is fulfilled, the operation which is indicated with geometric figure 10 continues (connection N). If this requirement is not met, then the operation which is indicated with geometric figure 11 continues (connection Y) {"1) 0 10 <d ^ y? It is tested whether the possible block channel bits when concatenated with the preceding block channel bits BCh ^ meets the requirement d - limited If this is satisfied, then the operation is indicated with the geometric designation shown in figure 12. (connection N) If this requirement is not met, the operation is also continued. is indicated with geometric figure 11 (connection Y); 25 11 DSV ^; = Max The dsv of the channel block bits is given such a high value (Max) that this block can certainly not be selected, to be continued with geometric figure 12; 12: = © S ^ - ^ + The dsv of your block channel bits (dsv ^)

3.CC

30 DS ¥ is added to the accumulated dsv acc (dsv) of the predecessor blocks of channel bits acc to obtain a new accumulated value of the d.s.v. (dsvf ^ b; acc is continued with geometric figure 5; 35 13 min / DS ^ / = DS ¥ '^^^ The minimum value of the dsv of the q possible blocks of channel bits is determined; this is shown by the dsv of the le block channel bits.

800 4 0 28 EHQ 80.007 14

Continued with geometric figure 14; 1 e 14 BCb The 1 block of channel bits is selected from the q possible blocks; Continued with geometric figure 15; 5 15 DSV __: = DSV ^ The accumulated value of the d.s.v. (DSV) is made equal to the accumulated value of the d.s.v. of the selected le block of information bits; continued with geometric figure 16; 10 16 i: = i + 1 The rank of the blocks of data and information bits is increased by 1. Continued with geometric figure 2; The cycle is now run through again for the next, the (i + 1) th block of data bits.

15 ___

The flow chart shown above applies to the exemplary embodiment of FIG. 1. For the exemplary embodiments of FIG. 2, taking into account the modifications already described there, apply corresponding flow charts.

In order to be able to distinguish between the information bits and the separation bits when demodulating the transmitted or recorded stream of channel bits, synchronization bits are included in the stream of channel bit blocks (n3 + n4), namely n3 synchronization information bits si n ^ sync separation bits. Βΐμ is stesfena ® give 25 number of blocks of information and separator bits a block. synchronization bits inserted. After detection of this drake, it can then be unambiguously determined in which bit positions information bits and in which bits separation bits are present. It should therefore be prevented that the synchronization word can be imitated by certain bit sequences in the information and separation blocks. To this end, for example, a unique block of synchronization bits, i.e., not contained in information and separation bit sequences, can be selected. Sequences that do not meet the requirement of d-bound or k-bound are less attractive for this because the information density or the self-clocking properties are then adversely affected. However, within the group of sequences that meet the requirements (d, k) - limited, the choice is very limited.

Another way is proposed. For example, the block of synchronization bits has at least twice consecutive and 800 800 28

"V

PHQ 80.007 unilaterally has a sequence which has two bits of type "0" between two consecutive bits of type "1". Preferably s is equal to k. In FIG. 4, a block of synchronization bits SYN is shown.

The block contains a sequence 5 (10000000000, 1 followed by 10 zeros) twice, consecutively and consecutively, represented by SYMP2, respectively. This sequence can also precede the flow of channel bits, namely for sequences with k = 10. To prevent the sequence from being sequentially and consecutively twice outside the block of synchronization bits, the first indication signal is suppressed if the scm of the number of separation bits and the number of consecutive and consecutive "0" bits of information immediately preceding a bit of the type "TV", the latter being part of the block separating bit, equal to k and also equal to the sum of the number of consecutive and successive information bits of type "0" immediately following said bit of type "1" "The block, already indicated, would be to use 2 times a sequence 100OOOOOOOOOO, T followed by 11 zeros. The block of synchronization bits also contains a block of synchronization separation bits. The function of the separation bit block is entirely similar to the function of the separation bit block between described above sen the blocks of information bits. (Therefore, they serve to meet the requirements of (d, k) limited and limited DC monbalance). The measures taken to prevent the synchronization pattern in the series of channel bits from being imitated by appearing twice consecutively and consecutively, these measures also prevent this pattern from appearing three times before or after the block of synchronization bits.

The method described above, which can also be referred to as modulation or encoding, is in the reverse direction i.e.

30 greatly simplified when demodulating or decoding. The limitation of the DC balance has been effected without influencing the information bit blocks, so that the information in the separation blocks is irrelevant for demodulating. Furthermore, the choice made on the modulator side of which m bits long data bits is associated with which n bite long block of information bits is important not only for the modulator but also for the demodulator. The complexity of the demodulator depends on this choice. In magnetic recording systems, the complexity of modulator and S00 4 0 28 EHQ 80.007 16 demodulator of equal length and that both are generally present in the device. In optical recording systems, the recording carrier is of the "read-only" type, whereby the consumer device need only contain a demodulator. In the latter case, it is therefore especially important to minimize the complexity of the demodulator, even at the expense of the complexity of the modulator.

In Pig. 5 an embodiment of a demodulator is shown, which demodulates the blocks of 8 data bits from blocks of 14 information bits. Pig. 5a shows the block diagram of the demodulator 10 and FIG. 5b shows in schematic form part of the method of wiring.

The demodulator contains AND gates 17-0 to soot 17-51 each with one or more inputs. At each of the inputs, which may or may not be inverted, one of the 14 bits of the blocks of information bits is supplied. In FIG. 5b shows how this is done under kalcm C. Column 1 represents the least significant bit position of the 14-bit information block, column 14 the most significant bit position, and intermediate columns 2 to 13 represent the other significant bit positions corresponding to their bit position. Lines 0 to 51 relate to the rank of the AND gate, ie line Q concerns the input format of AND gate 17-0, line 1 concerns the entry format of AND gate 17-1, etc. .

A symbol 1 in cfe iekoLcmqp_ line j means that the your AND gate 17 cp a non-inverting input is presented with the content of the ie bit position. A symbol 0 in the ith column on line j means that the j AND gate 17 is offered the contents of the i bit position (Ci) on an inverting input. Therefore (line 0) an inverting input of AND gate 17-0 is connected to the 1st bit position (C ^) and a non-inverting input is connected to the 4th bit position (C ^); (line 1) is a non -inverting input of AND gate 17-0 connected to the 3rd bit position 30 (Cg); etc.

The demodulator further includes 8 OR gates 18-1 through 18-8 whose inputs are connected to the outputs of AND gates 17-0 through 17-51. In FIG. 5b shows how this has been achieved under column. Kolcm refers to AND gate 18-1, 35 column Ag refers to AND gate 18-2 .... and column Ag refers to AND gate 18-8. A letter A in the it column of the your line indicates that the output of AND gate 17-j is connected to the input of 800 h0? 8 PHQ 80.007 17 OR gate 18-i.

For EN gates 17-50 and 17-51, the connection is changed as follows. An inverting output from both AND gate 17-50 and 17-51 are each associated with an input from a further AND gate 19. An output from OR circuit 18-4 is associated with a further input from AND gate 19 .

The outputs of the OR gates 18-1, 18-2, 18-3 and 18-5 through 18-8 and an output of AND gate 19 are each connected to an output 20-i. The decoded block of 8 data bits is therefore available in parallel form at this output.

The demodulator according to FIG. 5a can also be performed by means of a so-called FPIA (field programmable logic array, for example the Signaetics bipolar FPIA type 82S100 / 82S101. The table according to Fig. Sb forms the programming table for this.

The demodulator according to FIG. 5, because of its simplicity, is ideally suited for bead-only optical recording systems.

The block of synchronization bits can be detected by the means shown in FIG. 6 are shown. The transmitted or read registered signal is applied to a. input terminal 21. The signal is in the NRZ-M (ark) format. This signal is applied directly to a first input of an OR gate 22 and through a delay member 23 to a second input of OR gate 22. A so-called NRZ-I signal is then available at the output of OR gate 22, which is connected to the input of a shift register 24, 25. The shift register contains a number of sections, each with a branch, which number is equal to the number of bits containing the block of synchronization bits. In the example already used in the previous example, the shift register will have to contain 23 sections, namely to be able to contain the sequence 30 10000000000100000000001. Each branch is connected to an input or an inverting input of an AND gate 25. If the synchronization sequence is present at the inputs of AND gate 25, a signal will be generated at an output 26 of this AND gate, which indication signal for detecting the synchronization pattern can serve. Using this signal, the flow of bits is divided into blocks of (n ^ + n2) bits each. These blocks of channel bits are successively shifted into a further shift register.

800 4 0 28 r PHQ 80.007 18

The most significant n bits are read in parallel and applied to the inputs of the AND gates 17 as shown in FIG. 5a. The least significant n2 bits are irrelevant for demodulation.

The encoded signal is, for example, recorded on an optical record carrier. The signal has a form given by WF in Fig. 1b The signal is applied to the record carrier in a spiral-shaped information structure. The information structure contains a sequence of a number of superblocks, for example of the type shown in FIG. 7. A superblock SB ^ contains a block 10 of synchronization bits SY1St which has been built up as shown in FIG.

4, and a number of (33 in the exemplary embodiment) blocks of channel bits of each (n ^ + n2) bits BC.j, BC2, .... BC ^. A channel bit of the type "1" is represented by a transition in the record carrier, for example a transition from a non-well to a well or well; a channel bit of the type "0" is represented on the record carrier in the absence of a transition. The spiral information track is divided into elementary cells, the bit cells. These bit cells form on the record carrier a spatial structure which corresponds to a time division (period time of one bit) of the channel bit stream.

Regardless of the contents of the information and separation bits, a number of details can be recognized on the record carrier. The requirement of k-bound means for the carrier that the maximum distance between two consecutive transitions is k + 1 bit cells 25. The longest well fc.g. = non-pdrp) thus has a length of (k + 1) bit cells. The requirement of d - limited means that the minimum distance between two successive transitions is d + 1. It. shortest well (or non-well) therefore has a length of (d + 1) bit cells. Furthermore, at regular intervals, a well of the maximum length occurs, followed by (or preceded by) a non-well of the maximum length. This structure is part of the block of the sync bits.

In a preferred embodiment, k = 10, d = 2 and contains a superblock SB ^ 588 channel bit cells. The superblock SB ^ contains a 35 bLok synchronization bits of 27 bit cells and 33 blocks of channel bit cells of 17 (14 + 3) channel bit cells each.

A modulator, a transfer channel, for example an optical record carrier, and a demodulator can be part of a system 8004028 PHQ 80.007 19, for example a system for the conversion of analog information (music, speech) to digital information, which information is recorded qp an optical record carrier. The information recorded on this record carrier (or a copy thereof) can be reproduced by using a device suitable for displaying the type of information recorded on the record carrier.

In particular, the converter includes an analog-to-digital converter for converting the analog signal 10 (music, speech) to be recorded into a digital signal of a given format (source encoding). Furthermore, the conversion device may include part of an error correction system. In the conversion device, the digital signal is converted into a format with which the errors which can be corrected, in particular when the record carrier is read, can be corrected in the device for reproducing the signals. An error correction system suitable for this is described in the patent applications filed by Sony Corporation in Japan under number 14539 on May 21, 1980 and June 5, 1980, respectively.

The digital error-protected signal is then applied to the modulator (channel coding) described above for converting to one of the channel properties adjusted digital signal. Also, the synchronization pattern is supplied and the signal is brought into a suitable frame format. The signal thus obtained is used to generate a control signal, for example for a laser qp (NRZ-crazy format) with which a spiral information structure in the form of a sequence of pits / non-pits of given length is applied to the record carrier.

The record carrier or a copy thereof can be read with a device for displaying the information bits extracted from the record carrier. To this end, the device comprises a modulator already described in detail, the decoder part of the error correction system and a digital / analog converter for the recovery of a. replica of the analog signal presented to the conversion device.

800 40 28

Claims (15)

A method for encoding a series of binary data bits into a series of binary channel bits, which series of data bits is divided into contiguous and consecutive blocks of each ra data bits, which blocks are encoded in consecutive blocks of 5 (n ^ + n ^) channel bits (n ^ + n2)> m, which blocks of channel bits each contain a block of n ^ information bits and a block of n2 separation bits such that successive blocks of information bits are separated by one block of separation bits each, two consecutive channel bits of a first type, the type "1", are separated by at least 3 consecutive and contiguous bits of a second type, type "0" and the number of consecutive and contiguous channel bits of the second type is at most k, characterized in that the method comprises the following steps contains: -1- converting the blocks, containing m bits, data bits into n ^ 15 bit containing blocks of information bits; -2- generating a collection of possible sequences of channel bits, which sequences each contain at least one block of information bits and one block of separation bits and which possible sequences each contain the blocks of information bits supplemented with one of the 20 possible bit combinations of the blocks of separation bits; Determining the DC balance of each of the possible channel bit sequences determined in the previous step; - determining for each of the possible sequence channel bits the sum of the number of the separation bits and the number of contiguous 25 and consecutive information bits of the type "0" immediately preceding a bit of the type "1" and the son of the number following a bit of the type "1", which bit is part of one of the blocks of separation bits, and the son of the number of separation bits and the number of contiguous and consecutive information bits of the type "0" immediately precedes and follows that block of separation bits; Generating a first indication signal for those channel bit sequences for which the values of the sans determined in the previous step are greater than 2d and at most equal to k; Selecting from the channel bit sequences which led to the first indication signal of that channel bit sequence which minimizes the DC balance. 800 40 28 η * EHQ 80.007 2T r Method according to claim 1, characterized in that the fifth step further comprises the following step: -5a suppressing the first indication signal for that sequence of channel bits for which the son of the number of the separation bits determined in the fourth step and the number of consecutive and, successively, the information bits of the type "0" immediately preceding a bit of the type "1" of the block of separation bits are equal to the son of the number of separation bits and the number of consecutive and also determined in the fourth step consecutive information bits of type "0" immediately following a bit of type "Τ" of the block of separating bits and equal to; and the method further comprising the steps of: -7- splitting a sequence of blocks of (n ^ + n2) channel bits in contiguous and consecutive frames of each p blocks; inserting a block of synchronization channel bits between each two consecutive frames, which block of synchronization channel bits contain a given block of n ^ synchronization information bits, which block contains at least twice consecutively and consecutively a sequence containing between two consecutive bits of type "1", s bits of type "0" and further a block of n The sync separation bits contain which block of separation bits is determined by performing steps -2 to -6 with respect to the block of sync channel bits. Method according to claim 2, characterized in that s = k. Method according to any one of the preceding claims, characterized in that the sixth step further comprises the steps: - determining the accumulated DC unbalance of the preceding blocks of channel bits; - determining the absolute value of the sum of the accumulated DC unbalance and the DC unbalance of each of the channel bit sequences which led to the first indication signal. Method according to any one of the preceding claims, characterized in that the sequence channel bits contain four blocks of information bits of 35 n ^ bits each and four blocks of separation bits, that three blocks of separation bits have a first length n2 'and one block has a length n2' ' and that n2 ''> '. 800 4 0 28 PHQ 80.007 22 * ψ «* Method according to claim 5, characterized in that n ^ = 14, n2 '= 2, n2'1 = 6 and m = 8. Method according to any one of the preceding claims 1 to 4, characterized in that the sequence of channel bits contains one block of information bits of n ^ bits and one block of separation bits of n ^ bits. Method according to claim 7, characterized in that n ^ = 14, n2 = 3 and m = 8. Demodulator for decoding the data bits encoded in accordance with the method according to any one of the preceding claims 2 to 8, characterized in that the demodulator comprises: - means for detecting the synchronization pattern; means for dividing the series of channel bits into blocks. of each (n ^ + n2) channel bits; - means for separating the blocks from n. information bits of the ie blocks of n2 separation bits; means for converting a block of n data bits into a block of m data bits. Demodulator according to claim 9, characterized in that the means for converting contain AND gates, each AND gates 20 each having inputs for parallel feeding the information bits from at least one given bit position of the block of information bits, the means further comprising OR gates which are provided with inputs which are connected in a given manner to the outputs of the AND gates and which OR gates further contain outputs for outputting the decoded m data bits in parallel. 11. Record carrier provided with an information structure containing channels of channel bit cells, which channel bit cells each contain a / data bit represented by whether or not a level transition at the beginning of the bit cell, characterized in that the maximum distance between two consecutive transitions is equal to the length of (k + 1) bit cells, that the minimum distance between two consecutive transitions is equal to the length of (d + 1) bit cells, that are at most sequences of twice the maximum distance of (k + 1) To pre-select bit cells, said QC sequences are part of a synchronization sequence. Record carrier according to claim 11, characterized in that k = 10; d = 2; that the record carrier between two successive successions with the maximum distance is a frame with 561 channel bit cells 800 4 0 28 V 'i. PHQ 80.007 23, which frame contains 33 blocks of 17 channel bit cells each and the synchronization sequence contains 27 channel bit cells. A modulator for performing the method of encoding a series of binary data bits into a series of binary 5 channel bits according to any one of claims 1 to 8. Conversion device provided with a modulator according to claim 13. 15. Device for displaying the information bits 10 extracted from a transmission channel, in particular a record carrier, provided with a demodulator according to claim 9 or 10. 15 20 25 30 35 800 4 0 28