JPS5570922A - Demodulation system of digital signal - Google Patents

Demodulation system of digital signal

Info

Publication number
JPS5570922A
JPS5570922A JP14448978A JP14448978A JPS5570922A JP S5570922 A JPS5570922 A JP S5570922A JP 14448978 A JP14448978 A JP 14448978A JP 14448978 A JP14448978 A JP 14448978A JP S5570922 A JPS5570922 A JP S5570922A
Authority
JP
Japan
Prior art keywords
data
signal
sub
bit
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14448978A
Other languages
Japanese (ja)
Other versions
JPS623497B2 (en
Inventor
Teruo Furukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP14448978A priority Critical patent/JPS5570922A/en
Publication of JPS5570922A publication Critical patent/JPS5570922A/en
Publication of JPS623497B2 publication Critical patent/JPS623497B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Error Detection And Correction (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE: To prevent the lowering of data transmission amount and long time transmission of data in error, by detecting the specific bit pattern information included in normal data and matching the synchronism of sub-data based on the detected signal.
CONSTITUTION: The "00" pattern included in 5-bit data of output of serial-parallel shift register 41 is detected at the detection circuit 5. Further, based on the "00" pattern detection output, conversion clock signal and sub-data synchronizing signal, reset signal is produced from the signal generation circuit 6 and it is fed to the 1/4 frequency division circuit 46 to match the synchronizing timing of the sub-data synchronizing signal to the data. On the other hand, the 5-4 conversion data of ROM42 addressed with 5-bit parallel data of the register 41 is read out as 4-bit parallel data and fed to the parallel serial shift register 43. Thus, the demodulation data latched is obtained from the output from the circuit 46.
COPYRIGHT: (C)1980,JPO&Japio
JP14448978A 1978-11-21 1978-11-21 Demodulation system of digital signal Granted JPS5570922A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14448978A JPS5570922A (en) 1978-11-21 1978-11-21 Demodulation system of digital signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14448978A JPS5570922A (en) 1978-11-21 1978-11-21 Demodulation system of digital signal

Publications (2)

Publication Number Publication Date
JPS5570922A true JPS5570922A (en) 1980-05-28
JPS623497B2 JPS623497B2 (en) 1987-01-26

Family

ID=15363510

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14448978A Granted JPS5570922A (en) 1978-11-21 1978-11-21 Demodulation system of digital signal

Country Status (1)

Country Link
JP (1) JPS5570922A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5837828A (en) * 1981-08-31 1983-03-05 Nec Home Electronics Ltd Audio signal reproducer
JPH02243024A (en) * 1980-07-14 1990-09-27 Sony Corp Binary coding and decoding device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02243024A (en) * 1980-07-14 1990-09-27 Sony Corp Binary coding and decoding device
JPS5837828A (en) * 1981-08-31 1983-03-05 Nec Home Electronics Ltd Audio signal reproducer

Also Published As

Publication number Publication date
JPS623497B2 (en) 1987-01-26

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