JPH02243024A - Binary coding and decoding device - Google Patents

Abstract

PURPOSE:To simplify a decoder by dividing a binary code series into channel blocks with (n1+n2) channel bit length comprising an information block and a separated block based on a detected synchronizing signal. CONSTITUTION:A sent signal or a reproduced recording signal is fed to a terminal 21, and fed directly to an OR gate 22 and fed to the OR gate 22 via a delay element 23. Then a so-called NRZ-1 signal is outputted from a gate 22. The signal is fed to an AND gate 25 through a shift register 24. When a synchronizing series is fed to the gate 25, a signal is outputted from an output terminal 26 of the gate 25. The signal is able to be in use as a detection signal of a synchronizing pattern and the binary code series is divided into channel blocks with (n1+n2) channel bit length comprising an information block and a separated block based on the detected synchronizing signal.

Description

[Detailed description of the invention] The present invention relates to a binary encoding/decoding device.

A binary data bit sequence is divided into consecutive blocks of data bits, each having m bits, and the consecutive blocks of data are divided into (n++nz
) channel bits (where n1+n2>m), which consists of an information block consisting of n+ information bits and a separation block consisting of n2 separation bits, and this information block is separated into Conversion is performed so that each block is separated one by one, and continuous channel bits of the first code "1" are separated by at least d consecutive channel bits of the second code "0". In particular, the present invention relates to a decoding device for decoding channel bits obtained by binary encoding conversion in which the number of consecutive channel bits with a second code "0" does not exceed k. This is intended to simplify the process.

In digital transmission and magnetic and optical recording and reproducing systems, information is typically transmitted or recorded as a sequence of symbols. Together, these symbols constitute an alphabet (often a binary alphabet; a code). In the case of binary symbols, one symbol, e.g. “1”
is recorded on a magnetic disk or tape as a transition between two magnetization states by an NRZM (NRZ-mark) code, or on an optical disk as a transition between two focus states. And the other symbol “0”
is recorded as the absence of such a transition.

As a result of certain system requirements, some rules are actually imposed on the sequences of symbols that occur.

Some systems require self-clocking, so that the sequence of symbols transmitted or recorded is
Sufficient transitions must be transmitted and recorded to generate clock signals used for detection and synchronization. In addition, certain symbol sequences have special purposes,
For example, since it is used as a synchronization signal, it is required to prevent such a symbol sequence from occurring in the information signal. The occurrence of spurious synchronization sequences in the information signal makes the synchronization signal unclear and thus unsuitable for synchronization purposes. Additionally, it is also required that transitions be not spaced too closely to limit inter-symbol interference.

In the case of magnetic and optical recording, the requirements on the spacing between transitions are also related to the information density of the recording medium.

This is because, at a given minimum distance between two adjacent transitions on a recording medium, if the minimum time interval Tlll1n corresponding to the signals recorded thereon increases, the information density also increases in the same proportion. The required minimum bandwidth Bmin is also the minimum distance between transitions.If the information channel does not transmit direct current, as in the case of a general magnetic recording channel, the symbol sequence in the information channel should contain almost no direct current component. There is a need to.

By the way, the first mentioned method is based on the first reference (Tan
g, D, T,, Bahl, L, R, + “Bloc
k codes for a class of con
strained noiseless channel
ls.

Infor++ation and Control+
Vol.1? , no, milk Dec.

1970, pp. 436-461. )It is described in. This paper is concerned with block codes based on q-valued symbol blocks of d-rule, k-rule or d-rule. Here, such a block satisfies the following requirements.

(a) d rule: Two "l"s are separated by at least a string of d consecutive "0pas."

(b) k rule: The maximum length of a string of consecutive "0"s is k.

For example, a sequence of binary data bits is divided into consecutive blocks. Each of these blocks has m bits. These data blocks of m bits are converted into information blocks of n information bits (where n>m).

Here, since n>m, the number of combinations consisting of n information bits is the number of possible data blocks,
For example, if the d rule is required for an information block to be transmitted or recorded, the 2 part
The correspondence between 2''' data blocks and similar 2''' information blocks selected from 2''' possible realizations is
Information blocks that satisfy the rules are selected to be associated with each other.

According to Table 1 on page 439 of the first reference mentioned above, it can be seen how many information blocks there are depending on the length of the block (n) and the imposed request d. Under the condition that the minimum distance d is 1, there are 8 information bit blocks with length n of 4.

As a result, a data block of length m 3 (23-8 data words) is represented by the following information block. That is, it is an information block having length n of 4 information bits, in which at least one "0" symbol is arranged between adjacent "1" symbols. Such a coding is as follows, where the arrow → indicates that one block corresponds to the other block and vice versa.

000→0000 001→0001 010→0010 011→0100 100 Holol 101H1000 110→1001 111H1010 By the way, sometimes when you connect information blocks,
Certain requirements, such as those of the d-rule, may not be met without using other means.

Therefore, in the above-mentioned paper, it is proposed to provide separation bits between information blocks. If the d rule is required, a separator block consisting of d bits "0" is valid. In the above example where d is 1, one separator bit ("0") is sufficient. A data block consisting of three data bits may be transformed using (4+1) channel bits.

Such a conversion method is disadvantageous in that the low frequency components (including DC components) of the frequency spectrum of the channel bit string are rather large. Another drawback is that the converters (modulators and demodulators), especially the demodulators, become complex.

Regarding the first problem, see the second reference (Patel
, A, M, +”Charge-constraine
d byte-oriented(0,3)code”
, IBM Technical Disclosure
Bulletin.

Vol, 19. Nr, 7. Dec, 1976, p.
p, 2715 2717. ), connecting channel blocks with so-called inverting or non-inverting connections results in
It has been shown that it is possible to limit the DC unbalance of the d-regular code. In this case, the current polarity of the channel block is selected to reduce the current DC unbalance of the channel block.

However, since a rule code can be considered for d- that allows information blocks to be combined with d- without violating the rules, there is no need to add a separation bit to d- for the rule.

The present invention has been made in consideration of these circumstances, and allows for a simple configuration of a decoding device used to decode binary decoding in which a binary data bit sequence is converted into a binary channel bit sequence. It is intended to do so.

Hereinafter, one embodiment of the present invention will be described with reference to FIG.

FIG. 1 shows a series of several bits to explain a method of converting a binary data bit string into an example binary channel bit. In this Figure 1, binary data and
The bit string is divided into consecutive blocks. Each of these data blocks consists of m bits. In this example, m is selected to be 8 in the following description and drawings. The same thing can be applied to other values of m. A data block BDi of m bits is generally one of 2-possible bit sequences.

Such bit sequences are unsuitable for direct optical or magnetic recording, and are also unsuitable for several other reasons. That is, two symbols "1" are recorded on the recording medium, for example, as a transition from one direction of magnetization to the other direction of magnetization, or as a transition to a bit, and such symbols "1'' When back and forth, the transitions must not be too close together in terms of mutual interference, which limits the information density.At the same time, the minimum spacing between successive transitions Twi
The smaller n is, the greater the minimum bandwidth Bn+in required to transmit or record the bit string (
Bmin = 1/2 Tll1in) must also be taken into consideration. Another requirement placed on data transmission and optical or magnetic recording systems is that the bit sequence must have enough transitions to allow the transmitted signal to recover the clock used to perform synchronization. That's what it means. In the worst case where one block has m °“0°°, the previous block ends with a large number of “0′°”, and the next block starts with a large number of “0’°”, extract the clock. There is a possibility that it cannot be done.

For example, an information medium that does not transmit direct current, such as a magnetic recording medium, further needs to satisfy the requirement that the data string to be recorded has as few direct current components as possible. In optical recording, from the viewpoint of servo control, it is required that low frequency components of the data spectrum be suppressed to the maximum extent possible. In addition, demodulation can be simplified as the DC component is reduced.

For the reasons mentioned above and others, so-called channel coding is performed on the data bits before they are transmitted over a medium or recorded. In the case of block coding (first reference), data blocks each containing m bits are coded as information blocks each containing n1 information bits.

FIG. 1 shows a data block BD, how it is converted into an information block BI+. In this example, nl is selected to be 14 in the following description and figures.

Since,n,is greater than,m,not all combinations that can be formed with,n,bits are used. Inappropriate combinations are not used in media applications, and because of the one-to-one correspondence from data words to channel words required in this example, there are 16,000 possible
Only 256 words are selected from the transmission words exceeding . Therefore, several demands can be placed on the channel word. One request includes at least d consecutive second codes, i.e., between two adjacent first codes, i.e., "1" information bits, within the same block consisting of n1 information bits. There is an information bit of “0”.Table 1 on page 439 of the first reference.
indicates how many such binary words there are depending on the value of d. According to this table, it is clear that for n+-14, there are 277 words that have at least two "0" bits between adjacent "1" bits.

When encoding a block of 8 data bits,
The combination of these data bits is 256 (=2')
It is. Since it is a block of 14 channel bits, the requirement that d=2 is fully satisfied.

Concatenating blocks of information bits without any other method if similar d-rule requirements are imposed not only within blocks of n bits, but also at the boundaries of two adjacent blocks. I can't. To this end, the first reference sentence type proposes on page 451 to include one or more separation bits between channel blocks. It is easy to understand that the d rule is satisfied if at least the same number of "0" separation bits as d are included. FIG. 1 shows that the channel block BC is the information block B1.
The separate block BSz consists of n2 bits. Therefore, the channel block BCi consists of (n i +''n z) bits. In this example, unless otherwise specified, n2 is chosen to be 3 in the following description and figures.

In order to generate the clock as accurately as possible, the maximum number of consecutive "0" bits between two adjacent "l" bits in one information block must be determined in advance. is required to remain at the value k. m to 8
, n is 14, it is possible to delete, for example, a word for which k is very large from the 277 words satisfying d=2. It is clear that k can be kept to 10. Therefore, a set of 2Il (generally 21) blocks each consisting of 8 (generally m) data bits corresponds one-to-one to a set of 2' (generally 2''') information blocks. These information blocks are selected from among 2'4 (typically 21) possible information blocks.This means, in part, that
This is due to the fact that conditions such as d=2 and d=10 are imposed (generally, the rule is d-). It remains a matter of choice which data blocks correspond to which information blocks. In the first reference cited above, the number conversion from data bits to information bits is explicitly determined in a mathematically closed form. I see, such a conversion can be adopted in principle.

However, in this example, a different relationship is selected as will be explained further below.

Information block B1. Channel blocks B1 .
can be linked. This also applies to the d rule. Since the requirements of the d-rule and the d-rule are not mutually exclusive, but rather complementary, one and the same separate block of 02 bits each can in principle be used to achieve such a purpose.

Therefore, when the sum of the number of “0” bits preceding a certain separated block, the number of “0” bits following that separated block, and the nt bits (“0”) of the separated block itself exceeds the value of k, , in order to divide the series of "0" into a series of no more than 2 bits, at least one of the "0" bits of the "separation bits" must be replaced with a "1" bit.

In addition to its role in ensuring that the requirements of the regulations are met,
Isolation blocks can be used to reduce DC unbalance. This means that when concatenating information blocks, a block with a predetermined format is specified in some cases, but in many cases no conditions are imposed on the format of separate blocks. , or that only limited conditions are imposed, it is easy to understand. The degrees of freedom created in this way are used to reduce DC unbalance.

The occurrence and increase of DC unbalance is explained as follows. Assume that an information block Bit as shown in FIG. 1 is recorded on a recording medium in, for example, an NRz mark format. In this format, "l" is marked as a transition at the beginning of the corresponding bit cell. When it is "0", no transition is recorded.

The bit sequence indicated by Bl has the shape indicated by WF. Then, the bit sequence is recorded in such a shape on the recording medium. In the series under consideration, the positive level is longer than the negative level, so this series has DC unbalance. digital sum vat
ue) is often used as a guideline for determining DC unbalance. If the levels of the waveform are WF+1 and -1, respectively, the digital sum is equal to the waveform integrated along the series. In the example shown in Figure 1B, the digital sum +6
It becomes T. However, T is the length of the bit interval. If such a series were to be repeated, DC unbalance would occur. Generally, this DC unbalance causes fluctuations in the baseline and reduces the effective S/N. And S/N
As a result of this decrease, the accuracy of detection of the recorded signal decreases.

In order to limit the DC unbalance, the separation block BS is utilized as follows. Currently, a certain digital block B
Suppose that D is supplied. This data block BD,
For example, the information block Bl is determined by a table recorded in a recording device.

is converted to After this, -sets of possible channel blocks are generated.゛This block is (nl
+nz) bits. All these blocks are similar information blocks (bit cells (1) in Figure 1B).
~(14) ), n! The bit cells (15), (16), (17) of FIG. As a result, in the example shown in FIG. 1B, a set of 8 (=2fii) possible channel blocks is formed. After this, as an essentially arbitrary procedure, the following parameters are determined for each possible channel block:

a) Determine whether the requirements of the d rule and the 2 rule are consistent with the format of the current separation block from the perspective of the preceding channel block for the current possible channel block.

b) Determine the digital summation for the possible channel block.

A first display signal is generated for each possible channel block consistent with the requirements of the d-rule and the d-rule. The code parameters can be selected to generate such an indication signal for at least one possible information block.

Finally, among the possible channel blocks in which the first display signal is generated, for example, the channel block with the smallest absolute value of the digital sum is selected. However, a better method is to accumulate digital sums of previous channel blocks. Then, a block in which the absolute value of the accumulated digital sum decreases is selected from among the optimal channel blocks for next transmission. The words selected in this way are transmitted or recorded.

One of the advantages of this method is that isolation bits needed for other purposes can simply be used for the purpose of limiting DC unbalance. In addition, there is the advantage that the interference of the transmitted signal is limited to the isolated block and does not propagate to the information block (ignoring here the polarity of the waveform to be transmitted or recorded). Demodulation of the read recording signal is performed only for information bits.

There is no need to consider the separation bit.

Next, another embodiment of the code conversion method according to the present invention will be described. FIG. 2 shows some other embodiments of this method. Figure 2 A is a channel block...
These blocks are each predetermined (n
+ + n t) bits. Each channel block consists of an information block consisting of nl bits and a separate block consisting of n2 bits...
,BShBS! and h...

In this example, the DC imbalance is determined over several blocks. For example, as shown in FIG. 2A, it is determined between two channel blocks BCi, BC, . This DC unbalance is determined in a manner similar to that described for the example of FIG. However, the format of the super block that can be realized is different from each super block S B C
! provided that it is formed separately. That is, block BCz.

BC! In the information block about +1, the block BSl
, BS+-g are added. After this, the combination that minimizes the DC unbalance is selected from such a set. This method has the following advantages. That is, the residual DC unbalance becomes more uniform because one or more previous channel blocks are taken into account and the adjustment is optimal.

A more preferred variant of this method has notable features. A feature of this is that the super block S B C4 (FIG. 2A) is shifted by one channel block only after the DC unbalance has been minimized. This means that block BC4 (FIG. 2A) forming part of super block 5BC1 is processed and the next super block S B Cz. (not shown) is a block BC+ in which DC unbalance is minimized as described above. , and block B C
rt (not shown). And Fukuchi Nk B
C+Y is a super block SBC and the next super block SBC! , 1. Therefore, block BSi for super block 5BCi
,.

The provisional selection of separation bits of super block SB
The final selection for C, , , can be completely different. Since each of the blocks is evaluated several times (twice in this example), the effects of DC unbalance and noise are further reduced.

FIG. 2B shows another embodiment. In this embodiment, the DC unbalance is determined for several blocks (SBCr) at the same time. For example, as shown in FIG. 2B, four channel blocks 13C, +1130-〇), BC, (3)
, BC, +1+. These channel blocks have a predetermined number of information bits, n1.

However, for each of the channel bits, the separate blocks BS,(1)BSj''),BS,'',BS,'')1
7) The number of separated blocks 133j(+), B3.(D, 733Jtf
The number of separation bits of f) can be two, and the number of separation bits of separation block 33j(4) can be six. DC unbalance is determined in the same manner as described for example FIG. 2A.

The advantages mentioned above can also be obtained in this case.

In addition to this advantage, this example has the advantage that the DC unbalance can be reduced by using a relatively long separation block.

More specifically, the residual DC unbalance of a channel bit sequence in which each channel block has an equal number of bits, e.g.
bits, but larger than the residual DC unbalance of a channel bit sequence with bits divided 2:2:2:6.

It should be noted that the above-described time series of functions and associated states of the method of the present invention can be realized by common sequential logic circuits, for example microprocessors available on the market and corresponding recording devices and peripheral devices. FIG. 3 shows a flowchart of such an operation. In the following description, step annotations are used to indicate the roles and states of the coding method in chronological order. A4'ljl indicates a reference symbol, B! ! llI indicates annotation, and column C indicates an explanatory bone for the corresponding step.

The flowchart described above is applied to the example shown in FIG. The corresponding flowchart can then also be applied to the example of FIG. 2, if the changes already mentioned are taken into account.

In this example, (nff+n4) bits are included in the channel block sequence in order to distinguish between information bits and separation bits when demodulating the transmitted or recorded channel bit sequence. here 03
n4 are synchronization information bits, and n4 are synchronization separation bits. A synchronization block is inserted, for example, every predetermined number of information blocks and separation blocks. After this word is detected, it is possible to know in which bit positions the information bits are located and in which bit positions the separation bits are located.

Therefore, it is necessary to somehow prevent the synchronization word from being confused with the predetermined bit sequences of the information block and the separation block. To achieve this purpose, the synchronization bit,
That is, it is possible to select a special block consisting of synchronization bits that are not found in the information bit series or the separation bit series. d
Sequences that do not satisfy the rules are not very useful in achieving this purpose. This is because in such a case, information density and self-clocking characteristics are adversely affected. However, such selection is restricted within the group of sequences that satisfy the d-rule or the d-rule.

Therefore, another method is proposed. 2 bits “
A synchronization block is composed of, for example, at least two consecutive sequences containing S bits of "0" between "1"s. Preferably, S is made equal to k.Fourth
The figure shows a synchronization block SYN. This block is husband #
Series (10000
000000, 1 followed by 10 O's) is repeated twice in succession.

Such a sequence can be a channel bit sequence, ie a =10 sequence. However, in order to prevent this sequence from occurring twice in a row in a synchronized block, if a '1' bit forms part of an isolated block, the immediately preceding bit of that '1' bit is The sum of the number of separated bits of “0” and the number of consecutive information bits of “0” is equal to k, and the consecutive bits immediately after the “l” bit are
The first when it is also equal to the sum of the number of information bits of “°0”
display signal is suppressed. We have already shown measures to prevent synchronized blocks from being mixed in with other blocks, but this
ooooooooooooo, that is, 11 O's followed by l is repeatedly generated twice.

Furthermore, the synchronization block also has a synchronization isolation block. This separation block has the same role as the separation block between information blocks.

Therefore, their purpose is to satisfy the d-rule and the d-rule, as well as the requirement to limit DC unbalance. A method similar to the method used to prevent a pseudo synchronization pattern from appearing in the channel bit string when the synchronization pattern occurs twice in succession is
Also, prevent the synchronization pattern from occurring three times before or after the synchronization block.

The method described above can of course be applied to modulation and encoding. However, this method is much simpler in the reverse case, ie, during demodulation and decoding. Information bit
Since the DC unbalance can be limited without affecting the blocks, the information between the separated blocks is not important when demodulating the information. The selection of which information bits to correspond to is important not only for the modulator but also for the demodulator. That is, making such a selection complicates the configuration of the demodulator. In a magnetic recording system, both a modulator and a demodulator are built into the device, so both the modulator and the demodulator are complicated. In optical recording systems, since the recording medium is read-only, the user's equipment need only include a demodulator. In the case of optical recording systems, it is therefore particularly important to simplify the construction of the demodulator as much as possible, even if this means making the modulator more complex.

FIG. 5 shows an example of a demodulator. This demodulator demodulates a block of 8 data bits from a block of 14 information bits. FIG. 5A shows a block diagram of the demodulator, and FIG. 5B schematically shows part of its circuitry. This demodulator uses an AND gate (17-0
) to (17-51).

These AND gates (17-0) to (17-51> each have one or more input terminals. One of the 14 bits of the information block is applied to each input terminal. These input terminals are Figure 5B shows how this is done in columns C. The first column shows the least significant bit position C1 of a 14-bit long information block; The 14th column shows the bit position CI 4 of the least significant digit.The 2nd to 13th columns in between each show the remaining digits in relation to the bit position.Lines 10 to ls, respectively,
Corresponds to the number of the AND gate. In other words, the line!
. corresponds to the input terminal of the AND gate (17-0),
Line 11 corresponds to the input terminal of the AND gate (17-1).

The same applies to others. The code 1 in line lj of the i-th column means that the content of the first bit position B, via the non-inverting input terminal, is fed to the j-th AND gate (17). do. The symbol O on the i41st line 2j means that the first bit position Ci is supplied to the jth AND gate (17) via the inverting input terminal. This results in an and gate (
The inverting input terminal of 17-0) is the first bit position CI
and the non-inverting input terminal is connected to the fourth bit position C
4 (line 2°). Also, and gate (
The non-inverting input terminal of 17-1) is at the third bit position C.
1 (line I!, I). The same applies to others.

The demodulator further includes eight OR gates (18-1) to (1
8-8). These or game 1- (1B-1
) to (18-8) are AND gates (17-
0) to (17-51). Figure 5 A is A
, we show how this is achieved in the column .

Column A1 corresponds to (18-1) (or game). A2
The column corresponds to the or gate (18-2). And A
, the same goes for the following columns, and finally column A8 is the or gate (
18-8). The letter A in the jth At column is
AND gate (17-j) is OR gate (1B-i
).

The circuit configuration of the AND gate (IT-50) and (17-51) is changed as shown below. and·
The inverting output terminals of the AND gates (17-50) and (17-51) are respectively connected to the input terminals of the other AND gate (19).

The output terminal of the OR gate (18-4) is connected to the other input terminal of the AND gate (19).

Or Gate (18-1), (1B-2), (
18-3), (18-5).

The output terminal of (18-8) and the output terminal of AND gate (19) are respectively connected to the output terminal (20-i). This decoded 8-bit data block is then taken out as parallel data from this output terminal.

The demodulation shown in FIG. 5A can be modified with a so-called PPLA (Field Programmable Logic Array). For example, Synnetics bipolar PPLA82S100/82S101 can be used.

The table shown in FIG. 5 is programmable because of this array.

Due to its simplicity, the demodulator shown in FIG. 5 is well suited for read-only optical recording systems.

Synchronous blocks are detected by the circuit shown in FIG. The transmitted signal or the reproduced recorded signal is supplied to the input terminal (21). This signal is in MRZ-M format. This signal is or game 1- (22
) is supplied directly to the first input terminal of the OR gate (22) via the delay element (23). Then, the so-called NRZ-1
A signal is output from the output terminal of the OR gate (23). The output terminal of the OR gate (23) is the shift register (
24). This shift register (24) consists of a number of bit cells. Each of these bit cells is provided with a tap. In the above example, the number of bit cells is equal to the number of bits making up the synchronization block, the sequence toooooooooooooo
ooooo.

It has 23 bit cells to be able to record 00001. Each tap is an and gate (25
) is connected to the input terminal. And...gate (2
The input terminal of 5) is an inverting type or a non-inverting type.

When the synchronization sequence is supplied to the input of the AND gate (25), the output terminal (
A signal is output from 26). This signal can be used as a synchronization pattern detection signal. Based on this detection signal, the bit sequence is divided into blocks each having a length of (n++nz) bits. These divided channel blocks are sequentially shifted in other shift registers. The upper n1 digit bits are read out as parallel data, and as shown in the fifth prisoner (and game) (17)
is transferred to the input terminal of The lower 11 bits are not used in demodulation.

The coded signal is recorded, for example, on an optical recording medium. This signal has the form shown in FIG. 1B.

This signal is recorded on the recording medium in a spiral trajectory (.

This information form consists of a series of multiple super blocks as shown in FIG. 7, for example. The super block SB consists of a synchronization block 5YN1 and a large number (33 in this example) of channel blocks. Synchronous block SY
N.

is constructed as shown in FIG. channel pro 7
ri B C1+ B Ct, "" B C33 are respectively (
n, +nz) bits. A channel bit of "1" is represented as a transition in the recording medium.

For example, as a transition from a state with no bits to a state with bits. “On” channel bits appear as transitionless states on the recording medium. The spiral information track is subdivided into constituent cells, or bit cells. On the recording medium, these bit cells are spatially divided into A structure is formed, which corresponds to the subdivision of channel bits into bit time intervals.

Regardless of the content of the information bits and separation bits, numerous details are identified in the recording medium. In this recording medium, the k rule means that the maximum distance between two adjacent transitions is (k
+1) bit cell length. The longest bit (the part with no bits) therefore consists of (k+1) bit cells. The d rule means that the minimum distance between two adjacent transitions is (d+1) bit cell length. Additionally, at every regular interval, there is a longest bit after or before the longest no-bit portion. This form is part of the synchronization section.

In another example, k=10. d=2 and super block SBi consists of 588 channel bit cells. This super block SB.

consists of a synchronization block of 27 (14+3) bit cells and 33 channel blocks. Each channel block has (14+3) channel bit cells.

It goes without saying that the present invention can be applied to a conversion circuit that converts an analog signal into a digital signal and a playback device.

That is, the modulator, the transmission path, such as the optical recording medium, and the demodulator form part of an integrated system.

This system converts, for example, analog information (music, speech) into digital information.

This digital information is recorded on an optical recording medium.

Information recorded on a recording medium or a copy thereof can be reproduced by a device suitable for reproducing information recorded on the recording medium.

In this case, this conversion circuit in particular comprises an analog/digital converter in order to convert the analog signal to be recorded (music, speech) into a digital signal of a predetermined pattern (source coding). . moreover,
In this conversion circuit, the digital signal is converted into a format that allows errors that occur when reading from the recording medium to be corrected in a device that reproduces the signal. An error correction system suitable for this purpose has already been proposed by Sony Corporation (Japanese Patent Application No. 55-67).
No. 608).

The error-corrected digital signal is then fed to the above-mentioned modulator for conversion into a digital signal suitable for the characteristics of the medium. Additionally, a synchronization pattern is provided and this signal is placed in the appropriate frame pattern. The signal obtained in this way is used, for example, to obtain a laser control signal (NRZ-M format).
- This control signal makes it possible to apply a spiral information format to the recording medium as a predetermined sequence of presence/absence of bits.

This recording medium or a copy thereof is read by a device for reproducing the information bits obtained from the recording medium. To achieve this purpose, the device comprises a modulator, a decoder of an error correction system and an analog/digital converter for regenerating a replica of the analog signal supplied to the conversion circuit.

Note that this decoder has already been described in detail.

[Brief explanation of drawings]

FIG. 1 is a diagram illustrating an example of a method for converting a binary stroke symbol to a binary stroke symbol, which is applied to the present invention, and FIG. 2 is a diagram showing another method for converting a binary stroke symbol to a binary stroke symbol, which is applied to the present invention. FIG. 3 is a flow chart for explaining the example in FIG. 1, FIG. 4 is a diagram showing an example of a synchronization block used when demodulating a channel bit sequence, and FIG. A diagram showing an embodiment of the invention decoding device, FIG. 6 is a configuration diagram showing an example of a circuit for detecting a synchronized bit sequence, and FIG. 7 is a frame of a method of converting a binary code to a binary code applied to the present invention. - It is a diagram showing a format example. (17-0), (17-1)...(17-51
) are and gates, (1B-1) and (18-
2)...(18-8) are or gate, (19
) is an and gate, (20-1), (20-2)
...(20-8) is an output terminal. Agent Hidemori Matsukuma Figure 4 Figure 6 Figure 3 Figure 11-5 BCi - 11 Figure 2 Broom Figure 7

Claims (1)

[Claims] From a data block consisting of m bits, a “1” channel bit is separated by d (d≧1) or more consecutive “0” channel bits, and the number of consecutive “0” channel bits is within k. An information block is formed consisting of n_1 channel bits (where n_1>m) set to At the connection part via the separation block, the "1" channel bit is separated by d or more consecutive "0" channel bits, and the number of consecutive "0" channel bits is within k. Decoding a binary code sequence in which a separation block that reduces the DC balance of the information block and the separation block that are selected from the corresponding separation blocks and that are continuous, and further has a synchronization signal arranged at a predetermined position. a decoding device that detects the synchronization signal;
The method further comprises means for dividing the value code sequence into channel blocks having a length of n_1+n_2 channel bits, each consisting of the above information block and the above separation block, and means for converting the upper n_1 channel bits of the channel block into a data block consisting of the above m bits. 2 characterized by
Value code decoding device.