GB2083322A

GB2083322A - Method of coding a sequence of blocks of binary data bits into a sequence of blocks of binary channel bits and arrangement for decoding the data bits coded in accordance with the method

Info

Publication number: GB2083322A
Application number: GB8121289A
Authority: GB
Original assignee: Philips Gloeilampenfabrieken NV
Current assignee: Koninklijke Philips NV
Priority date: 1980-07-14
Filing date: 1981-07-10
Publication date: 1982-03-17
Also published as: NO161150C; SE456708B; FI812189L; ATA310781A; JP2547299B2; NL8004028A; JPH0614617B2; FI74565B; AT404652B; YU43025B; ZA814164B; JPH02243024A; NL186790C; IT1137613B; RU2089045C1; ES8403679A1; NO161150B; ES522839A0; MX155078A; YU184983A

Abstract

In a run length limited block coding method in which blocks of m data bits are converted to blocks of n1 information and n2 separation bits (n = n1 + n2>m). The blocks of bits satisfying the requirement of being (d, k) run length limited, the blocks of separation bits BSi between each of the blocks of n-information bits Bli are chosen, in those cases where the format is not prescribed by the (d, k)-constraint, such that the low-frequency spectrum and particularly the direct current unbalance is as low as possible. The direct current unbalance may be minimized within each block independently or cumulatively over a series of blocks. A demodulator for decoding data encoded as above is described. <IMAGE>

Description

SPECIFICATION Method of coding a sequence of blocks of binary data bits into a sequence of blocks of binary channel bits, arrangement for demodulating the data bits coded in accordance with the method, and recording medium having an information structure containing sequences of blocks of binary channel bits The invention relates to a method of coding a sequence of binary data bits into a sequence of binary channel bits, the sequence of data bits being divided into consecutive and sequential blocks, each comprising m data bits, these blocks being coded into sequential blocks of (n1 + n2) channel bits, (n1 + n2 > m), each of these blocks of channel bits comprising a block of n1 information bits and a block of n2 separation bits such that sequential blocks of information bits are separated each time by one block of separation bits, two sequential channel bits of a first type, the type "1", are separated by at least d sequential and consecutive bits of a second type, the type "0", and the number of sequential and consecutive channel bits of the second type being not more than k The invention further relates to a modulator for carrying out the method of coding a sequence of binary data bits into a sequence of binary channel bits; to a conversion circuit comprising the modulator; to a demodulator for decoding the data bits coded in accordance with the method; to a recording medium having an information structure comprising sequences of channel bit cells and to an arrangement for reproducing information bits derived from a transmission channel, for example, a recording medium.

In digital transmission or magnetic and optical recording/reproduction systems the information to be transmitted or to be recorded is usually in the form of a sequence of symbols. These symbols together form the (often binary) alphabet. In this case a binary alphabet (in the further course of this description this alphabet is represented by the symbols "1" and "0"), one symbol, for example the "1", can be recorded in accordance with the NRZ-mark code as a transition between states of magnetization or focus on the magnetic disc, tape or optical disc.

The other symbol, the "0", is recorded by the absence of such a transition.

As a result of certain system requirements, constraints are imposed in practice on the sequences of symbols which may occur. Some systems are required to be self-clocking. This implies that the sequence of symbols to be transmitted or to be recorded should have sufficient transitions to generate from the symbol sequence a clock signal which is required for detection and synchronization. A further requirement may be that certain symbol sequences must not occur in the information signal as these sequences are intended for special purposes, for example as a synchronizing sequence. Imitation of the synchronizing sequence by the information signal cancels the unambiguity of the synchronizing signal and, consequently, its suitability for that purpose.It may further be required that the transitions do not follow too closely after each other in order to limit the intersymbol interference.

In the case of magnetic or optical recording this requirement may also be related to the information density on the recording medium, as, when at a predetermined minimum distance between two consecutive transitions on the recording medium the minimum time interval (Tmin) corresponding therewith of the signal to be recorded may be increased, the information density is increased to the same extent. Also the required minimum bandwidth (Bmjn) is correlated to the minimum distance Tm,n between transitions (Bm,n = 1 /2Tm,n).

When use is made of information channels which do not transmit direct current, as is usually the case with magnetic recording channels, this results in the requirement that the symbol sequences in the information channel comprise the lowest possible (possibly no) direct current component.

A method of the type described in the opening paragraph is disclosed in a prior art reference Tang D.T., Bahl L.R., "Block codes for a class of constrained noiseless channels". Information and Control, Vol. 17, No. 5, Dec. 1970, pp 436-461. The article relates to block codes, based on d-, k- or (d, k)-constrained q-nary blocks of symbols, which blocks satisfy the following requirements: (a) d-constraint: two "1 "type symbols are separated by a run of at least d consecutive symbols of the "0" type; (b) k-constraint: the maximum length of a run of consecutive symbols of the type "0" is k A sequence of, for example, binary data bits is divided into consecutive and sequential blocks, each having m data bits. These blocks of m data bits are coded into blocks of n information bits (n > m).Since n > m, the number of combinations with n information bits exceeds the number of possible blocks of data bits (2m). If, for example, the constraint requirement is imposed on the blocks of information bits to be transmitted or to be recorded, mapping of the 2m blocks of data bits onto likewise 2m blocks of information bits (out of a possible number of 2n blocks) is chosen so that mapping is only carried out on those blocks of information bits which satisfy the requirement imposed.

Table I on page 439 of Information and Control reference identified above shows how many different blocks of information bits there are, depending on the length of the block (n) and the requirement imposed on d. So, there are 8 blocks of information bits having a length n = 4 at the condition that the minimum distance d = 1. Consequently, blocks of data bits having a length m = 3 (2 = 8 data words) could be represented by blocks of information bits having a length n = 4, two consecutive "1 "type symbols in the blocks of information bits being separated by at least one "O"-type symbol.For this example, coding then is

indicates mapping of one block onto the other block and vice versa):

When linking up the blocks of information bits it is in some cases, however, not possible to satisfy the requirement (in the example the d-constraint) without taking further measures. In the said article it is proposed to include separation bits between the blocks of information bits. For the case of d-constraint coding one block of separation bits, comprising#bits of the "O"-type is sufficient. In the above-mentioned example, where d= 1, one separation bit, (one zero) is therefore sufficient. Each block of 3 data bits is then encoded by 5 (4 + 1) channel bits.

This coding method has the disadvantage that the contribution of the low frequencies (including d.c.) to the frequency spectrum of the stream of channel bits is rather high. A further disadvantage is that the coding converters (modulator, demodulator), the demodulator in particular, are complicated.

As regards the first disadvantage it should be noted that a prior art reference Patel, A.M., "Charge-constrained byte-oriented (0,3) code", IBM Technical Disclosure Bulletin, Vol. 19 No.

7, Dec. 1976, pp 2715-2717 indicates that the direct current unbalance of (d, k)-constrained codes can be limited by interconnecting the blocks of channel bits by means of a so-called inverting or a non-inverting link. Acting thus, the sign of the contribution of the instantaneous block of channel bits to the direct current unbalance is chosen so that the direct current unbalance of the preceding blocks of channel bits is reduced. However, here a (d, k)-constrained code is concerned whose blocks of information bits can he linked-up without coming into conflict with the (d, k)-constraint, so that the addition of separation bits for reasons of (d,k)constraining is not neccessary.

It is an object of the invention to provide 3 method of coding of a sequence of binary data bits into a sequence of binary channel bits which improves the iow-frequency spectrum properties of the signal to be derived from the channel bits and which method enables the use of a simple demodulator.

According to the present invention there is provided a method of coding a sequence of binary data bits into a sequence of binary channel bits, this sequence of data bits being divided into consecutive and sequential blocks each comprising m data bits, these blocks being coded into sequential blocks of In, + n2) channel bits where (n + n2) > m, each of these blocks of channel bits comprising a block of n, informtion bits and a block of n2 separation bits such that sequential blocks of information bits are separated by each time one block of separation bits, two sequential channel bits of a first type are separated by at least d sequential and consecutive bits of a second type and the number of sequential and consecutive channel bits of the second type being not more than k, wherein the method comprises the following steps: -1- converting blocks containing ambits of data bits into blocks containing n, bits of information bits; -2- generating a set of possible sequences of channel bits, each sequence comprising at least one block of information bits and one block of separation bits and these possible sequences each comprising the blocks of information bits supplemented by one of the possible bit combinations of the blocks of separation bits; -3- determining the direct current unbalance of each of the possible sequences of channel bits determined in the preceding step; ; -4- determining for each of the possible sequences of channel bits the sum of the number of separation bits and the number of consecutive and sequential information bits of the second type which immediately precede a bit of the first type and the sum of the number following after a bit of the first type, this bit forming part of one of the blocks of separation bits, and the sum of the number of separation bits and the number of consecutive and sequential information bits of the second type immediately preceding and following after that block of separation bits; -5- generating a first indication signal for those channel bit sequences the values of the sums determined in the preceding step of which are higher than dand not more than equal to k;; -6- selecting from the sequences of channel bits which resulted in the first indication signal that sequence of channel bits which minimizes the direct current unbalance.

Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings.

In these drawings: Figure 1 shows some bit sequences for illustrating an embodiment of the coding format in accordance with the invention, Figure 2 shows some further embodiments of the format of the channel coding to be used in the reduction of the direct current unbalance in accordance with the invention, Figure 3 is a flow chart of an embodiment of the method in accordance with the invention, Figure 4 illustrates a block of synchronizing bits for use in the method in accordance with the invention, Figures 5a and 5b show an embodiment of a demodulator in accordance with the invention for decoding the data bits which were coded in accordance with the method, Figure 6 shows an embodiment of the means for detecting a sequence of synchronizing bits, Figure 7 shows an embodiment of a frame-format for use in the method in accordance with the invention.

Corresponding elements in the Figures have been given the same reference symbols.

Fig. 1 shows some bit sequences to illustrate the method of coding a run of binary data bits (Fig. 1 a) into a run of binary channel bits (Fig. 1 b). The run of data bits is divided into consecutive and sequential blocks BD. Each block of data bits comprises m data bits. By way of example, the choice m = 8 will be used in the further course of this description and in the Figures. The same applies, however, for any other value of m. A block of m data bits BD; generally comprises one of the 2m possible bit sequences.

Such bit sequences are not so suitable for direct optical or magnetic recording and that for several reasons. When namely two data symbols of the "1" type, which are for example recorded on the recording medium as a transition from one magnetizing direction to the other or as a transition to a pit, immediately follow after each other, then these transitions must not be too close to each other in view of their mutual interaction. This limits the information density. At the same time the minimum band width Bmjn which is required to transmit or record the bit stream is increased when the minimum distance Tmjn between consecutive transitions (Bm; n = 1 /(2Tm~") is small.Another requirement which is often imposed on data transmission and optical or magnetic recording systems is that the bit sequences must have a sufficient number of transitions to recover from the transmitted signal a clock signal with which synchronization can be carried out. A block having m zeroes, preceded in worst case situations by a block ending in a number of zeroes and followed by a block beginning with a number of zeroes, would endanger the clock extraction.

Information channels which do not transmit direct current, such as magnetic recording channels must further satisfy the requirement that the data stream to be recorded comprises a direct current component which is as small as possible. With optical recording it is desirable that the low-frequency portion of the data spectrum is suppressed to the best possible extent for the benefit of ensuring the proper operation of the servo controls. In addition, the demodulation is simplified when the direct current component is relatively small.

For the above and other reasons a so-called channel coding is performed on the data bits before they are transmitted via the channel or before they are recorded. In the case of block coding (see prior art Information and Control reference) the blocks of data bits which each contain m bits are coded as blocks of information bits which each comprise n1 information bits.

Fig. 1 shows how the block of data bits BD is converted into a-block of information bits B11. By way of example, the choice n, = 14 will be used in the further course of this description and in the Figures. As n1 is greater than m, not all the combinations which can be formed with n1 bits are utilized: those combinations which do not fit in well with the channel to be utilized are not used. So, in the example given only 256 words need to be selected from the more than 16,000 possible channel words for the required one-to-one mapping of data words onto channel words.

Consequently, some requirements may be imposed on the channel words. One requirement is that between two consecutive information bits of a first type, the "1" type, at least d sequential and consecutive information bits of a second type, the "0' 'type, are situated within the same block of n1 information bits. Table I on page 439 of prior art Information and Control reference shows how many such binary words there are, depending on the value of d. It appears from the table that for N1 = 14 there are 277 words with at least two (d = 2) bits of the "0" type between consecutive bits (of the "1" type). When coding blocks of eight data bits, of which there may be 28 = 256 combinations, as blocks of 14 channel bits the requirement d = 2 can therefore be amply satisfied.

Catenation of the blocks of information bits Bli is, however, not possible without further measures when the same requirements of d-constraint is not only imposed within a block of n, bits but also extends over the boundary between two consecutive blocks. To this end, the prior art Information and Control reference proposes (page 451 ) to include one or more separation bits between the blocks of channel bits. It can be easily seen that when a number of "O"-type separation bits at least equal to d is included, that the d-constraint is satisfied. Fig. 1 shows that a block of channel bits consist of the block of information bits and a block of separation bits.

The block of separation bits comprises n2 bits so that the block of channel bits BCi comprises n, + n2 bits. By way of example the choice n2 = 3 will be used in the further course of the description and in the Figures, unless indicated differently.

In order to make the clock generation as reliable as possible a further requirement may be that the maximum number of "0" type bits which may occur uninterruptedly between two consecutive "1" type bits within one block of information bits is limited to a predetermined value k. In the example where m = 8 and n1 = 14 it is possible to eliminate from the 277 words which satisfy d = 2, those words, for example, which have a very high value for k It appears that k may be limited to 10.Consequently, a set of 28 (in general 2") blocks of data bits of 8 bits each (in general m) is mapped onto a set of also 28 (in general 2") blocks of information bits, which information bits have been selected from 214 (in general 2"1) possible blocks of information bits, which is partly the result of the fact that the following requirements have been imposed: d = 2 and k = 10 (in general d,k-constrained). It is still at one's option which one of the blocks of data bits is to be associated with one of the blocks of information bits. In the above-mentioned prior art Information and Control reference a number translation from data bits to information bits is unambiguously determined in a mathematically closed form.Although this translation can, in principle, be used, preference is given to a different association as will be further explained hereinafter.

Catenation of the k-constrained channel words Bli is only possible when separation blocks have been arranged between the blocks of information bits BI,, this also applies for the S constrained blocks. In principle the same separation blocks of n2 bits each can be used for this purpose as the requirements for d-constrained and k-constrained blocks are not each other's opposite, but rather are complementary.When, consequently, the sum of the number of bit values of the "0" type preceding a given separation block exceeds the number of values following after that separation block and the n2 bits of the separation block itself exceed the value k, then at least one of the bit values of the "0" type of the separation block should be replaced by a bit value of the "1" '' type in order to split the sequence of zeroes into sequences which are each not more than k bits long.

In addition to their function of ensuring that the requirements of (d, k)-constraint are satisfied, the separation blocks can be dimensioned so that they can also be utilized for minimizing the direct current unbalance. This is based on the recognition of the fact that for some catenations of blocks of information bits a predetermined format of the block of separation bits is indeed prescribed but that in a large number of cases either no requirements or only limited requirements are imposed on the format of the block of separation bits. The degree of freedom created thus is used for minimizing the current unbalance.

The coming into existence and the growth of the direct current unbalance can be explained as follows. The block of information bits Bl, as shown in Fig. 1 b is recorded on the recording medium, for example in the form of a NRZ-mark format. With this format a "1" is marked by a transition at the beginning of the relevant bit cell and becomes a "0" when no transition is recorded. The bit sequence shown in Bl, then assumes a shape which is denoted by WF, in which shape this bit sequence is recorded on the recording medium. This sequence has a direct current unbalance, as for the present sequence the positive level has a length which is longer than the negative level. A measure which is often used for the direct current unbalance is the digital sum value, abbreviated to d.s.v.Assuming the levels of the wave form WF to be + 1 and - 1, respectively, the d.s.v. is then equal to the running integral of the wave form WF and is + 6T in the example shown in Fig. 1 b, T being the length of one bit interval. When such sequences are repeated, the direct current unbalance will grow. Generally, this direct current unbalance results in a base line movement and reduces the effective signal-to-noise ratio and, consequently, the reliability of the detection of the recorded signals.

The block of separation bits BS; is used as follows to limit the direct current unbalance. At a given instant a block of data bits BD, is supplied. This block of data bits BD; is converted into a block of information bits Bull, for example by means of a Table stored in a store. Thereafter, a set of possible blocks of channel bits, containing (n, + n2) bits is generated. All these blocks comprise the same block of information bits (bit cells 1 to 14, inclusive, Fig. 1 b) supplemented by the possible bit combinations of the n2 separation bits (bit cells 15, 16 and 17. Fig. 1 b).

Consequently, in the example shown in Fig. 1 b a set consisting of 2n = 8 possible blocks of channel bits is produced. Thereafter the following parameters are determined from each of the possible blocks of channel bits, in principle in an arbitrary sequence: a) it is determined for the relevant possible block of channel bits, in view of the preceding block of channel bits, whether the requirement of d-constraint and the requirement of k-constraint do not conflict with the format of the present block of separation bits; b) determination of the d.s.v. for the relevant, possible block of channel bits.

A first indication signal is generated for those possible blocks of channel bits which do not conflict with the d-constraint and k-constraint requirements. The choice of the coding parameters guarantees that such an indication signal is generated for at least one of the possible blocks of information bits. Finally, from the possible blocks of channel bits for which a first indication signal has been generated that block of channel bits is, for example, selected which has in an absolute sense the lowest d.s.v. However, a still better method is the accumulation of the d.s.v.

of the preceding blocks of channel bits and to select from the blocks of channel bits which are eligible for the next-coming transmission that block which will cause the absolute value of the accumulated d.s.v. to decrease.The word selected thus is transmitted or recorded.

An advantage of this method is that the separation bits which are already necessary for other purposes can now also be utilized in a simple manner for the limitation of the direct current unbalance. An additional advantage is that the intervention in the signal to be transmitted is limited to the blocks of separation bits and does not extend to the blocks of information bits (ignoring the polarity of the wave form to be transmitted or recorded). The demodulation of the read, recorded signal then only relates to the information bits. The separation bits may be left out of consideration.

Fig. 2 shows some further embodiments of the method. Fig. 2a shows schematically the sequences of blocks of channel bits .., BC#1, BC1, BC. . . ., these blocks comprising a predetermined number of (n, + n2) bits. Each block of channel bits comprises blocks of information bits consisting of n, bits, and blocks of separation bits... BS1#2, BSi-r, BSj, BS1+1..., each consisting of n2 bits.

In this embodiment the direct current unbalance is determined across several blocks, for example as shown in Fig. 2a across two blocks of channel bits BC; and BCj+,. The direct current unbalance is determined in a similar manner as described for the embodiment of Fig. 1, on the proviso that the possible formats of superblocks are generated for each superblock SIC1, that is to say the blocks of information bits for block BC, and blocks BCj+, are supplemented by all the possible combinations which can be formed with the n2 separation bits of block BS; and BS1+1.

That combination which minimizes the direct current unbalance is thereafter selected from this set. This method has the advantage that the remaining direct current unbalance has a more uniform character as more than one block of channel bits in advance are considered which intervention is optimum.

An advantageous variant of this method has the distinctive feature that the superblock SBC (Fig. 2a) is shifted one block of channel bits only after the direct current unbalance has been minimized. This means that block BC, (in Fig. 2a), which is part of the superblock SIC1, is processed and that the subsequent superblock SBC,+1 (not shown) contains the blocks By1+1 and BC,+2 (not shown) for which the above-described direct current unbalance minimizing operation is performed.So the block BCj+, is part of both the superblock SBC, and the subsequent block SBCj; ,. It is then perfectly possible that the (provisional) choice for the separation bits in block BSj+1, made in superblock SBC, differs from the ultimate choice made in superblock SBC1+1. As each block is assessed several times (twice in the present example) the direct current unbalance and consequently the noise contribution is further reduced.

Fig. 2b shows a further embodiment in which the direct current unbalance is determined for several blocks simultaneously (SBCj), for example as shown in Fig. 2b for four blocks of channel bits BCj(", BCj'2), BCj(3', and BCj'4). Each of these blocks of channel bits comprises a predetermined number of n, information bits. However, the number of separation bits comprised in the blocks of separation bits BSj"'. BSj'2', BSj'3' and BSj(4) is not the same for each block of channel bits.The number of information bits may, for example, amount to 14 and the number of separation bits for the blocks BSj"', BSj'2) and BSj'3' may be 2 for each block and 6 for block BSj4#. Determining the direct current unbalance is carried out in a similar manner as described for the embodiment of Fig. 2a.

In addition to the advantages already mentioned in the foregoing and which also apply here, this method has the advantage that the availability of a relatively long block of separation bits increases the possibilities of reducing the direct current unbalance. More specifically, the remaining direct current unbalance of a sequence of channel bits in which each block of channel bits comprises an equal number of, for example, 3 bits is larger than the remaining direct current unbalance of a sequence of channel bits the blocks of separation bits of which comprise an average of 3 bits, divided, however, into 2-2-2-6 bits.

It should be noted that the described time sequences of functions and associated states of the method can be realized by means of universal sequential logic circuits such as commercially available microprocessors with associated stores and peripheral equipment. Fig. 3 shows a flow chart of such an implementation. The following explanatory texts are associated with the legends of the geometrical figures which illustrate, time-sequentially, the functions and states of the coding method. Column A shows the reference symbol, B the legend and column C the explanatory text associated with the relevant geometrical Figure.

A B C 1DSCacc the the digital sum value (d.s.v.) of the i: = 0; preceding blocks of channel bits is given the value zero at the start of the method.

The first data word BD is given the number i = O. Proceed to geometrical Fig.

2; 2 BD The block of data bits of m bits of the number i is selected from a store.

Proceed to geometrical Fig. 3; 3 Blj (BD1) The block of data bits having number i (BD,) is converted into a block of information bits consisting of n, bits (Blj) by means of a Table stored in the store; proceed to geometrical Fig. 4; 4 j: = O A parameter j is initiated at a value 0; the parameter j is the number of one of the q blocks of channel bits consisting of nl + n2 bits which is possibly eligible for transmission or recording; proceed to geometrical Fig. 5; 5 j: = j + 1 The parameter j is increased by 1; proceed to geometrical Fig. 6; 6 jsQ? When the relevant parameters have been determined of all the q possible blocks of channel bits, operations are continued by the operation indicated by geometrical Fig. 13. In geometrical Fig. 6 this is indicated by the link N.When j#Q, operations are continued by the operation indicated by geometrical Fig. 7; 7 BOi=BI#+8# The jth possible block of channel bits BOis formed by supplementing the block of information bits Bli by the j'h combination of the block of separation bits BSi; proceed to geometrical Fig. 8; 8 DSVi=? The d.s.v. of the jth possible block of channel bits is determined; proceed to geometrical Fig. 9; 9 > gax? It is checked whether the jlh possible block of channel bits on catenation with the preceding blocks of channel bits BC, 1 satisfies the k-constraint requirement. If this requirement is satisfied, operations are continued by the operation indicated in geometrical Fig. 10 (link N). If this requirement is not satisfied, then the following step is the operation indicated by geometrical Fig. 11 (link Y).

10 < da)in? It is checked whether the jth possible block of channel bits on catenation with the preceding block of channel bits By,~, satisfies the d-constraint requirement. If this requirement is satisfied the following step is the operation indicated by geometrical Fig. 12(link N).When this requirement is not satisfied, then the operation is continued by the step indicated by geometrical Fig. 11 (link Y); 11 DSV ): = max The d.s.v. of the jth block of channel bits is given such a high value (max) that this block can definitely not be selected; proceed to geometrical Fig. 12; 12 DSV#c : = DSVa) + DSVacc The d.s.v. of the jth block of channel bits (DSV~) is added to the accumulated dsv (DSVaCc) of the preceding blocks of channel bits to obtain a new accumulated value of the d.s.v. (DSVta)Cc); proceed to geometrical Fig. 5; 13 min#/DSV: = DSV(e) The minimum value of the dsv of the q possible blocks of channel bits is determined.This appears to be the d.s.v. of the first block of channel bits (Proceed to geometrical Fig. 14); 14 BC, The first block of channel bits is selected from the q possible blocks; proceed to geometrical Fig. 15; 15 DSVacc: = DSV(1) The accumulated value of the d.s.v.

(DSVaCc) is made equal to the accumulated value of the d.s.v. of the selected first block of information bits; proceed to geometrical Fig. 16.

16 i: = i + 1 The number of the blocks of data and information bits is increased by one.

Proceed to geometrical Fig. 2; the cycle is now repeated for the next, the (i + 1 )th block of data bits.

The flow chart shown above is applicable to the embodiment shown in Fig. 1. For the embodiments of Fig. 2 the corresponding flow charts hold, taking the modifications already described into consideration.

In order to enable a distinction when demodulating the transmitted or recorded stream of channel bits between the information bits and the separation bits, (n3 + n4), namely n3 synchronizing information bits and n4 synchronizing separation bits, are included in the stream of channel bits blocks. A block of synchronizing bits is, for example, inserted after each predetermined number of blocks of information and separation bits. After detection of this word it can then be unambiguously determined in which bit positions information bits and in which bit positions separation bits are present. Measures should therefore be taken to prevent the synchronization word from being imitated by certain bit sequences in the information and separation blocks.To this end a unique block of synchronizing bits, that is to say synchronizing bits which are not present in information and separation bit sequences, can be chosen.

Sequences which do not satisfy the requirement of being d-constrained or k-constrained are not so attractive for this purpose as the information density or the self-clocking properties are then affected negatively. However, the choice is very limited within the group of sequences which satisfy the (d, k)-constraint requirements.

A different method is therefore proposed. The block of synchronizing bits includes, for example, at least two times in succession and consecutively a sequence which comprises S bits of the "O"-type between two sequential bits of the "1 "type. Preferably, S is equal to k Fig. 4 shows a block of synchronizing bits SYN. The block comprises two times in succession and consecutively a sequence (10000000000, 1 followed by 10 zeroes) denoted by SYNP1 and SYNP2, respectively. This sequence may also be present in the channel bit stream, namely for sequences where k= 10.However, to prevent the sequence from occurring twice in succession and consecutively outside the block of synchronizing bits, the first indication signal is suppressed when the sum of the number of separation bits and the number of sequential and consecutive information bits of the "0" type immediately preceding a bit of the "1" type, the latter forming part of the block of separation bits, is equal to k and also equal to the sum of the number of consecutive and sequential information bits of the "0" type which immediately follows after the said bit of the "1" '' type of the block of separation bits. The other, already indicated way to prevent imitation would be to use twice in succession the sequence 100000000000 thus 1, followed by 11 zeroes.

In addition, the block of synchronization bits also comprises a block of synchronization separation bits. The function of the block of separation bits is exactly the same as the function described in the foregoing of the block of separation bits between the blocks of information bits.

(Consequently they have for their purpose to satisfy the (d, k))-constraint and a limited direct current unbalance requirement. The measures which are taken to prevent the synchronizing pattern from being imitated in the run of channel bits as it occurs twice in succession and consecutively, these same measures also prevent this pattern from occurring three times before or after the block of synchronizing bits.

The above-described method, which may also be referred to as modulating or encoding, is of a considerably simpler character in the opposite direction, that is to say during demodulation or decoding. Limitation of the direct current unbalance is effected without affecting the blocks of information bits, so that the information in the separation blocks is irrelevant for demodulating the information. In addition, the choice taken at the modulator end as to which m bit long block of data bits is associated with which n, long block of information bit is of importance not only for the modulator but also for the demodulator. Namely, the complexity of the demodulator depends on this choice. In magnetic recording systems the complexity of modulator and demodulator are of equal importance as they are in general both present in the apparatus.In systems for optical recording, the recording medium is of the "read-only" type so that the consumer equipment need only comprise a demodulator. So, in this latter case it is particularly important to reduce the complexity of the demodulator as much as possible, even at the cost of the complexity of the modulator.

Figs. 5a and 5b show an embodiment of a demodulator which demodulates the blocks of 8 data bits from blocks of 14 information bits. Fig. 5a shows the block schematic circuit diagram of the demodulator and Fig. 5b shows in tabular form the patterns of connections to the AND and OR gates of the demodulator shown in Fig. 5a. The demodulator comprises AND-gates 17-0 to 17-51, inclusive, each having one or more inputs. One of the 14 bits of the blocks of information bits is applied to each input, which are of the inverting or non-inverting type. Fig.

Sb shows in column C how this is carried out. Column 1 represents the least significant bit position C1 of the 14-bit information block, column 14 the most significant bit position C14 and the intermediate columns 2 to 13, inclusive, represent the remaining, corresponding with the bit position, significant bit positions. The lines 0 to 51, inclusive, relate to the number of the ANDgate, that is to say line 0 relates to the input format of AND-gate 17-0, line 1 relates to the input format of AND-gate 17-1, etc. A symbol 1 in the ith column of line jsignifies that the Jth AND-gate 17 is supplied via a non-inverting input with the content of the ith bit position B1.A symbol 0 in the ith column of line j signifies that the jlh AND-gate 17 is supplied via an inverting input with the content of the ith bit position (Cj). Consequently, (line 0), an inverting input of AND-gate 1 7-0 is connected to the lh bit position (C1), and a non-inverting input is connected to the 41h bit position (C4); (line 1) a non-inverting input of AND-gate 17-0 is connected to the 3rd bit position, (C3); etc.

The demodulator further comprises 8 OR-gates 18-1 to 18-8, inclusive, the inputs of which are connected to the outputs of the AND-gates 17-0 to 17-51, inclusive. Fig. 5b shows in column A, how this is realized. Column A, relates to AND-gate 18-1, column A2 relates to ANDgate 18-2.. and column A8 relates to AND-gate 18-8. A letter A in the ith column of the jth line indicates that the output of AND-gate 1 7-j is connected to the input of OR-gate 18-i.

For the AND-gates 17-50 and 17-51 the circuit is modified as follows. An inverting output of both AND-gate 17-50 and 17-51 are each connected to an input of a further AND-gate 19.

An output of OR-circuit 18-4 is connected to a further input of AND-gate 19.

Each output of the OR-gates 18-1, 18-2, 18-3 and 18-5 to 18-8, inclusive, and an output of AND-gate 19 are connected to an output 20-i. The decoded block of 8 data bits is consequently available in parallel form at this output.

The demodulator shown in Fig. 5a may, alternatively, be in the form of a so-called FPLA (field programmable logic array), for example the Signetics bipolar FPLA type 82S100/82S101. The Table shown in Fig. 5b is the programming table for this array.

The demodulator shown in Fig. 5a is, because of its simplicity, eminently suitable for optical recording systems of the "read-only" type.

The block of synchronizing bits can be detected with the means shown in Fig. 6. The transmitted or read recorded signal is applied to an input terminal 21. The signal is in the NRZ M(ark) format. This signal is applied directly to a first input of an OR-gate 22 and to a second input of the OR-gate 22 via a delay element 23. A so-called NRZ-I signal is then available at the output of the OR-gate 22, which is connected to the input of a shift register 24. The shift register comprises a number of sections, each having a tap, which number is equal to the number of bits comprised in the block of snychronizing bits.In the example used in the foregoing, the shift register must have 23 sections, namely in order to be able to contain the sequence 10000000000100000000001. Each tap is connected to an input of an AND-gate 25, which input is either an inverting or a non-inverting input. When the synchronization sequence is present at the inputs of AND-gate 25, a signal will then be generated at an output 26 of this AND-gate which may be used as an indication signal for the detection of the synchronizing pattern. By means of this signal the bit stream is divided into two blocks of (nl + n2) bits each. These blocks of channel bits are shifted, one after the other, in a further shift register.The most significant n1 bits are read in parallel and applied to the inputs of the ANDgates 17, as shown in Fig. 5a. The least significant n2 bits are irrelevant for the demodulation.

The coded signal is, for example, recorded on an optical recording medium. The signal has a form denoted to WF in Fig. 1 b. The signal is applied on the recording medium in a helical information structure. The information structure comprises a sequence of a number of superblocks, for example of the type shown in Fig. 7. A superblock SB, comprises a block of synchronizing bits SUN1, this block being implemented as shown in Fig. 4, and a number (33 in the embodiment) of blocks of channel bits, each having (nj + n2) bits BC1, BC2,... BC33. A channel bit of the "1" type is represented by a transition in the recording medium, for example a transition from no-pit; a channel bit of the "0" type is represented on the recording medium by the absence of a transition.The helical information track is subdivided into elementary cells, the bit cells. On the recording medium these bit cells form a spatial structure, which corresponds to a subdivision in the time (period time of one bit) of the stream of channel bits.

Independent of the content of the information and separation bits, a number of details can be distinguished at the recording medium. For the medium the k-constraint implies that the maximum distance between two consecutive transitions is k + 1 bit cells. The longest pit (or nopit) has therefore a length of (k + 1) bit cells. The d-constraint implies that the minimum distance between the two consecutive transitions is d + 1. The shortest bit (or no-pit) gas therefore a length of (d + 1) bit cells. Furthermore, at regular distances there is a pit of the maximum length followed by (or preceded by) a no-pit of the maximum length. This structure is part of the block of the synchronization bits.

In a preferred embodiment k = 10, d = 2 and a superblock SBi comprises 588 channel bit cells. The superblock SB, comprises a block of synchronization bits of 27 bit cells and 33 blocks of channel bit cells, each having 17 (14 + 3) channel bit cells.

A modulator, a transmission channel, for example an optical recording medium, and a demodulator may together be part of a system, for example a system for the coversion of analog information (music, speech) into digital information, which information is recorded on an optical recording medium. The information recorded on the recording medium (or a copy thereof) can be reproduced by means of an arrangement which is suitable for the reproduction of the type of information which has been recorded on the recording medium.

The conversion circuit comprises in particular an analog-to-digital converter for converting the analong signal (music, speech) to be recorded into a digital signal of a predetermined format (source coding). In addition, the conversion circuit may include a portion of an error-correction system. In the conversion circuit the digital signal is converted into a format by means of which the errors which particularly occur during reading of the recording medium can be corrected in the arrangement for the reproduction of the signals. An error correction system whic is suitable for this purpose is disclosed in a Patent Application which has been filed by Sony Corporation in Japan under number 67608 on 21st May, 1980.

The digital, error-protected signal is thereafter applied to the modulator described in the foregoing (channel coding) for conversion into a digital signal which is adapted to the channel properties. In addition, the synchronization pattern is supplied and the signal is brought to a suitable frame format. The signal thus obtained is used to generate a control signal, for example for a laser (NRZ-mark format) by means of which a helical information structure is applied on the recording medium in the form of a sequence of pits/no pits of a predetermined length.

The recording medium or a copy thereof can be read by means of an arrangement for the reproduction of the information bit derived from the recording medium. To this end, the arrangement comprises a modulator, which has already been described in detail, the decoder portion of the error correction system and a digital/analog converter for reconstituting a replica of the analog signal which is applied to the conversion circuit.

Claims

CLAIMS:

1. A method of coding a sequence of binary data bits into a sequence of binary channel bits, this sequence of data bits being divided into consecutive and sequential blocks, each comprising m data bits, these blocks being coded into sequential blocks of (n1 + n2) channel bits where (n1 + n2) > m, each of these blocks of channel bits comprising a block of n1 information bits and a block of n2 separation bits such that sequential blocks of information bits are separated by each time one block of separation bits, two sequential channel bits of a first type are separated by at least d sequential and consecutive bits of a second type and the number of sequential and consecutive channel bits of the second type being not more than k, wherein the method comprises the following steps:: -1-converting blocks containing ambits of data bits into blocks containing n1 bits of information bits; -2-generating a set of possible sequences of channel bits, each sequence comprising at least one block of information bits and one block of separation bits and these possible sequences each comprising the blocks of information bits supplemented by one of the possible bit combinations of the blocks of separation bits; -3-determining the direct current unbalance of each of the possible sequences of channel bits determined in the preceding step;; -4-determining for each of the possible sequences of channel bits the sum of the number of separation bits and the number of consecutive and sequential information bits of the second type which immediately precede a bit of the first type and the sum of the number following after a bit of the first type, this bit forming part of one of the blocks of separation bits, and the sum of the number of separation bits and the number of consecutive and sequential information bits of the second type immediately preceding and following after that block of separation bits; -5-generating a first indication signal for those channel bit sequences the values of the sums determined in the preceding step of which are higher than d and not more than equal to k;; -6-selecting from the sequences of channel bits which resulted in the first indication signal that sequence of channel bits which minimizes the direct current unbalance.

2. A method as claimed in Claim 1, wherein the fifth step comprises the steps of suppressing the first indication signal for that sequence of channel bits for which the sum, determined in the fourth step, of the number of separation bits and the number of consecutive and sequential information bits of the second type immediately preceding a bit of the first type of the block of separation bits is equal to the sum, which was also determined in the fourth step, of the number of separation bits and the number of consecutive and sequential information bits of the second type which immediately follows after a bit of the first type of the block of separation bits, this sum being equal to s; and wherein the method further comprises the following steps: -7-dividing a sequence of blocks of (n1 + n2) channel bits into consecutive and sequential frames, each having p blocks; -8-inserting a block of synchronization channel bits between every two sequential frames, this block of synchronization channel bits comprising a predetermined block of n3 synchroniza tion information bits, this block comprising at least twice in succession and consecutively a sequence which comprises, between two sequential bits of the first type, s bits of the second type and furthermore comprising a block of n4 synchronization separation bits, this block of separation bits being determined by carrying out the steps -2- to -6-, inclusive, with respect to the block of synchronization channel bits.

3. A method as claimed in Claim 2, wherein s= k

4. A method as claimed in any one of the preceding Claims, wherein the sixth step includes determining the accumulated direct current unbalance of the preceding blocks of channel bits; and determining the absolute value of the sum of the accumulated direct current unbalance and the direct current unbalance of each of the sequences of channel bits which resulted in the first indication signal.

5. A method as claimed in any one of the preceding Claims, wherein the sequence of channel bits comprises four blocks of information bits each having n1 bits and four blocks of separation bits, and wherein three of the four blocks of separation bits have a first length n21 and the fourth block a length n211 and that n21, > n11.

6. A method as claimed in Claim 5, wherein n1 = 14, n21 = 2, n211 = 6 and m = 8.

7. A method as claimed in any one of the preceding Claims 1 to 4, wherein the sequence of channel bits comprises one block of information bits having n1 bits and a block of separation bits having n2 bits.

8. A method as claimed in Claim 7, wherein n, = 14. n2 = 3 and m = 8.

9. A method as claimed in any one of Claims 1 to 4, wherein the sequence of channel bits is formed by at least two blocks of channel bits and wherein consecutive sequences of channel bits jointly relate to at least one block of channel bits.

10. A method of coding a sequence of binary data bits into a sequence of binary channel bits, substantially as hereinbefore described with reference to Figs. 1 to 4 and 7 of the accompanying drawings.

11. A demodulator for decoding the data bits coded in accordance with the method claimed in any one of the preceding Claims 1 to 10, the demodulator comprising means for detecting the synchronizing pattern; means for dividing the run of channel bits into blocks each having (n1 + n2) channel bits; means for separating the blocks having n1 information bits from the blocks having n2 separation bits; and means for converting a block of n1 information bits into a block of m data bits.

12. A demodulator as claimed in Claim 11, wherein the conversion means comprise ANDgates, each AND-gate having inputs to which there are applied in parallel the information bits coming from at least one predetermined bit position of the block of information bits, and OR gates having inputs which are connected in a predetermined manner to the outputs of the ANDgates and outputs for outputting the decoded AND-data bits in parallel.

13. A demodulator for demodulating data bits coded in accordance with the method claimed in any one of Claims 2 to 10, substantially as hereinbefore described with reference to Figs. 5a, 5b and 6 of the accompanying drawings.

14. A recording medium having an information structure comprising sequences of channel bit cells, these channel bit cells each comprising a binary data bit which is represented by a level transition or no level transition at the beginning of the bit cell, wherein the maximum distance between two consecutive transitions is equal to the length of (k + 1) bit cells, the minimum distance between two consecutive transitions is equal to the length of (d + 1) bit cells, sequences of not more than two times the maximum distance of (k + 1) bit cells are present, and wherein the said sequences are part of a synchronizing sequence.

15. A recording medium as claimed in Claim 14, wherein when k = 10; d = 2; the recording medium comprises between two consecutive sequences which are at the maximum distance from each other, a frame having 561 channel bit cells, this frame comprising 33 blocks each having 17 channel bit cells and wherein the synchronizing sequence comprises 27 channel bit cells.

16. A modulator for carrying out the method of coding a sequence of binary data bits into a sequence of binary channel bits, as claimed in any of the Claims 1 to 10, inclusive.

17. A conversion circuit comprising a modulator as claimed in Claim 16.

18. An arrangement for reproducing information bits derived from a transmission channel, a recording medium in particular, the arrangement comprising a demodulator as claimed in Claim 11, 12 or 13.