JPH05266600A - Binary code recording medium - Google Patents

Abstract

PURPOSE:To enable setting a distance between adjacent transitions within a prescribed range and to reduce a direct current inequilibrium. CONSTITUTION:Separation blocks are separated by (d) or more '0' channel bits which continue '1' channel bits in the connecting section through the separation blocks of adjacent information blocks. Moreover, the continuous pieces of '0' channel buts are selected among the relevant plural separation blocks in which the number of continuous '0' channel bits is within (k) and the separation blocks which are continuous and the separation blocks which reduce direct current inequilibrium of the separation blocks are selected and recorded.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a binary code recording medium.

[0002]

2. Description of the Related Art In digital transmission and magnetic and optical recording / reproducing systems, normal information is transmitted or recorded as a series of symbols. Such symbols together form an alphabet (often a binary alphabet; code). In the case of a binary code, one symbol, for example "1", is NR
The ZM (NRZ-mark) code records on a magnetic disk or tape as a transition between two magnetization states,
Alternatively, it is recorded on the optical disc as a transition between two focus states. Then, record the other symbol "0" as the absence of such a transition.

As a result of some system requirements, some rules are actually imposed on the sequence of symbols generated. Some systems require self-clocking, which is why a sequence of symbols to be transmitted or recorded is generated in order to generate a clock signal used for detection and synchronization.
It must be transmitted and recorded as enough transitions. Besides, it is required to prevent such a symbol sequence from occurring in the information signal, because a certain symbol sequence is used for a special purpose, for example, as a synchronization signal. If a pseudo sync sequence occurs in the information signal, the sync signal becomes ambiguous and as a result becomes unsuitable for the purpose of synchronization. Furthermore, it is also required that the intervals between transitions be as tight as possible to limit interference between symbols.

In the case of magnetic and optical recording, between transitions
The space requirement is also related to the information density of the recording medium.
This is because the predetermined distance between two adjacent transitions on the recording medium.
Corresponds to the signal recorded on it at the minimum distance of
Minimum time interval T_minIf the
This is because the degree also increases. Required minimum bandwidth B
_minIs also associated with the minimum distance between transitions (B_min= 1 / 2T
_min).

When the information channel does not transmit direct current, as in the case of a general magnetic recording channel, it is necessary to make the symbol sequence in the information channel almost free of direct current component.

By the way, the method described at the outset is based on the first reference (Tang, DT, Bahl, LR, "B").
lock codes for a class of
constrained noises ch
Annels. "Information and C
ontrol, Vol. 17, no. 5, Dec. 19
70, pp. 436-461. )It is described in. This paper relates to block codes based on q-valued symbol blocks of the d-rule, k-rule or d-k rule. Here, such a block fulfills the following requirements: (A) d rule: Two “1” s are separated by at least d consecutive “0” strings. (B) k rule: the maximum length of a sequence of consecutive "0" s is k
To be.

For example, a series of binary data bits is divided into continuous blocks. Each of these blocks is m
Have bits. The data block consisting of these m bits is converted into an information block consisting of n information bits (where n> m). Here, since n> m, the number of combinations of n information bits is
The number of data blocks that can be realized exceeds 2 ^m . For example, if the d rule is required for information blocks to be transmitted or recorded, 2 ⁿ data blocks and
The associations between the 2 ^m information blocks, which are also selected from the 2 ^m realizable, are chosen such that the information blocks satisfying the d rule are associated.

Table 1 on page 439 of the above-referenced first reference.
It shows how many information blocks there are, depending on the block length (n) and the demand d imposed. Under the condition that the minimum distance d is 1, the length n
There are 8 blocks of information bits with 4 in each. As a result, a data block of length m 3 (2 ³ = 8 data words) is represented by the next information block. That is, the length n
Is an information block having 4 information bits, and at least one "0" symbol is arranged between adjacent "1" symbols in the information block. For example, such coding is as follows: Here, the arrow ← → indicates that one block corresponds to the other block and vice versa.

000 ← → 0000 001 ← → 0001 010 ← → 0010 011 ← → 0100 100 ← → 0101 101 ← → 1000 110 ← → 1001 111 ← → 1010

By the way, sometimes, when information blocks are connected, a certain request, for example, a request of d rule cannot be satisfied without using other means. Therefore, in the above-mentioned paper, it is proposed to provide a separation bit between information blocks. If the d rule is required, a separate block consisting of d bits of "0" is valid. In the above example where d is 1, one separation bit (“0”) is sufficient. A data block consisting of 3 data bits is assigned to (4 + 1) channels.
It may be converted by bits.

Such a conversion method is disadvantageous in that the low frequency component (including the direct current component) of the frequency spectrum of the channel bit string is rather large. There is also a drawback that the converter (modulator and demodulator), especially the demodulator, becomes complicated.

Regarding the first problem, the second reference (Patel, AM, "Charge-const") is used.
lined byte-oriented (0,3)
code ”, IBM Technical Discl
Osure Bulletin, Vol. 19, Nr.
7. Dec. 1976, pp. 2715-2717. )
In, it is shown that linking the channel blocks by so-called inverting or non-inverting coupling can limit the DC imbalance of the dk rule code. In this case, the polarity of the channel block at that time is selected so as to reduce the direct current imbalance of the channel block. However, here it is said that information blocks can be combined without violating the dk rule.
Since the code of the -k rule is considered, it is not necessary to add a separation bit for the dk rule.

The present invention has been made in consideration of such circumstances, and records the above-mentioned binary code for converting a binary data bit sequence into a binary channel bit sequence.
It is intended to propose a value code recording medium.

[0014]

In the binary code recording medium of the present invention, as shown in the drawing, from a data block consisting of m bits, a channel bit of "1" is continuous d (d ≧ 1).
An information block consisting of n ₁ channel bits (where n ₁ > m), which is separated by more than 0 "0" channel bits and the number of consecutive "0" channel bits is set within k, is the data. A binary code in which each block is formed one-to-one with a block, and a separation block consisting of n ₂ channel bits is arranged between each information block, and the channel code of "1" is recorded as a state transition. In the medium, the separation block separates the "1" channel bit by consecutive d or more "0" channel bits at a connection portion of adjacent information blocks through the separation block, and the "0" channel. This information block is selected from a plurality of corresponding separation blocks whose number of consecutive bits is k or less and which is consecutive. And a separation block for reducing the DC imbalance of the separation block and the separation block are selected and recorded so that the distance between adjacent transitions is set within a predetermined range and the DC imbalance is reduced.

[0015]

According to the present invention, the separation block has d or more "0" consecutive channel bits of "1" in the connection portion of adjacent information blocks via the separation block.
The DC imbalance of the information block and the separation block, which are selected from a plurality of separation blocks corresponding to the number of consecutive "0" channel bits within k, and which are continuous, are selected. Since the separation block to be reduced is selected and recorded, the distance between adjacent transitions can be set within a predetermined range and the DC imbalance can be reduced.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is for explaining a method of converting a binary data bit string into a binary channel bit string, and shows several bit sequences. In FIG. 1, the binary data bit string is divided into continuous blocks. Each of these data blocks consists of m bits. In this example, in the following description and drawings, m
Choose 8. The same applies for other values of m. A data block BDi consisting of m bits is generally one of 2 ^m possible bit sequences.

Such bit sequences are unsuitable for direct optical or magnetic recording and are not suitable for several other reasons. That is, two symbols "1" are recorded on the recording medium as a transition from one magnetization direction to the other magnetization direction or as a transition to a pit, and such a symbol "1" is preceded and followed. If so, then the transitions must not be too close in terms of mutual interference. This limits the information density. At the same time, it is also considered that the smaller the minimum interval T _min between consecutive transitions, the larger the minimum bandwidth B _min required for transmitting or recording a bit string (B _min = 1 / 2T _min ). There is a need to.

Another requirement, imposed in data transmission and optical or magnetic recording systems, is used to achieve synchronization from the transmitted signal. That is, enough transitions are needed in the bit sequence to be able to recover the clock. In the worst case where one block has m "0s", the preceding block ends with many "0s" and the next block starts with many "0s", the clock may not be extracted. is there.

For example, an information medium that does not transmit direct current, such as a magnetic recording medium, must further satisfy the requirement that the data string to be recorded has a direct current component that is as small as possible. In the optical recording, from the viewpoint of servo control, it is required that the low frequency component of the data spectrum be suppressed to the maximum. in addition,
Demodulation can be simplified as the DC component decreases.

For the above and other reasons, before transmitting or recording data bits through the medium,
So-called channel coding is performed on the data bits. In the case of block coating (first reference), data containing m bits each
The blocks are coded as information blocks each containing n ₁ information bits.

FIG. 1 shows how a data block BDi is converted into an information block BIi. In this example, n ₁ is selected as 14 in the following description and drawings. n ₁
Since m is greater than m, not all combinations that can be formed with n ₁ bits are used. Do not use improper combinations when applied to media. Then, in this example, from the requested data word to the channel
Due to the one-to-one correspondence of words, only 256 of the possible 16000+ transmitted words are selected. Therefore, some requirements can be imposed on the channel words. One request is, in the same block of n ₁ information bits, two adjacent first codes, ie at least d consecutive second codes between “1” information bits, That is, there is an information bit of "0". Table 1 on page 439 of the first reference
Shows how many such binary words are present, depending on the value of d. From this table, it is clear that, given that n ₁ = 14, there are 277 words with at least 2 bits “0” between adjacent “1” bits. When coding a block of 8 data bits, the combination of those data bits is 256 (= 2
⁸ ). And since it is a block of 14 channel bits, the requirement of d = 2 is sufficiently met.

If a similar d-rule requirement is imposed not only within a block of n ₁ bits, but also on the boundary of two adjacent blocks, then a block of information bits can be assigned without any other means. Cannot be linked. To this end, the first reference proposes on page 451 to include one or more separation bits between channel blocks. It is easy to understand that the d rule is satisfied if at least as many separation bits as "0" as d are included. FIG. 1 shows that the channel block BCi consists of an information block BIi and a separation block BSi. The separation block consists of n ₂ bits. Therefore, the channel block BCi consists of (n ₁ + n ₂ ) bits. In this example, n ₂ is selected as 3 in the following description and drawings unless otherwise specified.

In order to generate clocks as accurately as possible, two adjacent clocks in one information block should be used.
It is required that the number of consecutive "0" bits between the "1" bits is at most a predetermined value k. In the present example in which m is 8 and n ₁ is 14, it is possible to delete, for example, a word having a very large k from 277 words that satisfy d = 2. It is clear that k can be suppressed to 10. Thus, each 8 consists (generally m) pieces of data bits 2 ⁸ (typically 2 to ^m)
Similarly, each set of blocks has a one-to-one correspondence with the set of 2 ⁸ (generally 2 ^m ) information blocks. These information blocks are selected from the 2 ¹⁴ (generally 2 ⁿ¹ ) information blocks that can be realized. This is due in part to the imposition of conditions such as d = 2 and k = 10 (generally the dk rule). It remains a matter of choice which of the data blocks corresponds to which of the information blocks. In the first reference mentioned above,
The number conversion from data bits to information bits is unambiguously determined in a mathematically closed form. Indeed, such a conversion can be adopted in principle. However, in this example, a relationship different from this is selected, as will be described further below.

Only when the separation block is arranged between the information blocks BIi, the channel blocks BIi can be connected so as to satisfy the k rule. This also applies to the d rule. Since the requirements of the d-rule and the requirements of the k-rule are not mutually exclusive, but rather complementary, in principle the same separation block of n ₂ bits each can be used to achieve such an objective. ..

Therefore, the sum of the number of bits of "0" preceding a certain separation block, the number of bits of "0" following the separation block, and n ₂ bits ("0") of the block itself is k. When it exceeds, in order to divide the "0" sequence into a sequence that does not exceed k bits, the separation bit "0"
Must be replaced with at least one of the "1" bits.

In addition to ensuring that the requirements of the dk rule are met, the isolation block can be used to reduce DC imbalance. This means that when concatenating information blocks, a block of a predetermined format is specified, but in many cases, no condition is imposed on the format of the separated block. Or, if you know that only limited conditions are imposed, you can easily understand. The degrees of freedom thus generated are used to reduce the DC imbalance.

The generation and increase of DC imbalance is explained as follows. It is assumed that the information block BI ₁ as shown in FIG. 1 is recorded on the recording medium in the NRZ mark format, for example. In this format, a "1" is marked as the first transition of the corresponding bit cell. When it is "0", no transition is recorded. The bit sequence in which BI ₁ is indicated has a shape designated by WF.

Then, with such a shape, the bit sequence is recorded on the recording medium. Since the positive level is longer than the negative level in the series under consideration, this series has a DC imbalance. Digital sum (digital sumv)
value) is often used as a standard for determining DC imbalance. Letting the levels of the waveform be WF + 1 and -1, respectively, the digital sum is equal to the integral of the waveform along the sequence. Then, in the example shown in FIG. 1B, the digital sum is + 6T. However, T is the length of the bit interval. If such a sequence is repeated, DC imbalance will occur. In general, this DC imbalance causes fluctuations in the baseline and reduces the effective S / N. As a result of the decrease in S / N, the accuracy of detection of the recorded signal decreases.

To limit the DC imbalance, the isolation block BS is used as follows. Now, assume that a data block BDi is supplied. This data block BDi is converted into an information block BIi by, for example, a table recorded in the recording device. After this, a set of feasible channel blocks is generated. This block has (n ₁ + n ₂ ) bits. All these blocks are similar information blocks (bit cells "1" to "14" in FIG. 1B, n ₂ separate bits (bit cells "15""16""1" in FIG. 1B).
7 ”) is added. As a result, in the example shown in FIG. 1B, a set of 8 (= 2 ⁿⁱ ) feasible channel blocks is formed.

After this, in principle, as an arbitrary procedure,
The following parameters are determined for each feasible channel block. a) Determine whether the requirements of d-rule and k-rule are consistent with the format of the current separation block in terms of the preceding channel block for the feasible channel block. b) Determine the digital summation for the feasible channel block.

The first display signal is generated for each feasible channel block consistent with the requirements of the d rule and the k rule. The choice of code parameters makes it possible to generate such an indication signal for at least one possible information block.

Finally, of the possible channel blocks in which the first display signal is generated, for example, the channel block having the smallest absolute value of the digital sum is selected. However, a much better way is to accumulate the digital sum of the preceding channel blocks. Then, a block in which the absolute value of the accumulated digital sum is reduced is selected from the optimum channel blocks for the next transmission. The words thus selected can be transmitted or recorded.

One of the advantages of this method is that the isolation bits needed for other purposes are also easily used for the purpose of limiting DC imbalance. In addition, there is the advantage that the interference of the transmitted signal is limited to the separation block and does not propagate to the information block (here ignoring the polarity of the waveform to be transmitted or recorded). The demodulation of the read recording signal is performed only on the information bits. Don't worry about separate bits.

Next, other than the code conversion method according to the present invention,
Let's take an example. Figure 2 shows some of the methods
Another example is shown. Figure 2A shows the channel block ... B
Ci _-1, BCi, BCi₊₁, ... Show the series. these
Each block is predetermined (n₁+ N₂) Bits
Have a Each channel block is n₁Bit
Information block consisting of₂Separation block consisting of bits
Lock ... BSi_-1, BSi, BSi₊₁, ... and have
It

In this example, the DC imbalance is determined through several blocks. For example, as shown in FIG. 2A, it is obtained between two channel blocks BCi and BCi _{+ 1} . This DC imbalance is obtained by a method similar to that described for the example in FIG. However, the super block formats that can be realized are different for each super block SBC.
The condition is that each i is formed. That is, a feasible combination that can be generated from the two separation bits of the blocks BSi and BSi ₊₂ is added to the information block for the blocks BCi and BCi ₊₁ . After this, the combination that minimizes the DC imbalance is selected from such a set. This method has the following advantages. That is,
The residual DC imbalance is more uniform because the adjustment is optimal considering one or more of the preceding channel blocks.

A more preferred variant of this method is notable
It has characteristics. This feature minimizes DC imbalance
Only one super block SBCi (Fig. 2A) later
It is to be transferred by the channel block of.
This is part of the super block SBCi.
The lock BCi (Fig. 2A) has been processed and the next super
Lock SBCi₊₁(Not shown) is DC
Block BCi where equity is minimized₊₁And block BCi₊₂
(Not shown). And block BCi ₊₁Is sue
Super block SBCi and the next super block SB
Ci₊₁Be part of both. So super block
Block BSi for SBC₊₁Provisional of the separation bit of
Selection, super block SBCi₊₁About
It can be quite different from the final choice. Of block
Each of them is evaluated several times (twice in this example),
The effects of DC imbalance and noise are further reduced.

FIG. 2B shows another example. In this example, the DC imbalance is determined for several blocks (SBCj) at the same time. For example, as shown in FIG. 2B, four channel blocks BCj ⁽¹⁾ , BCj ⁽²⁾ , BCj ⁽³⁾ ,
For BCj ⁽⁴⁾ . These channel blocks have a predetermined number of n ₁ information bits. However, for each of the channel bits, the number of separation bits of each of the separation blocks BSj ⁽¹⁾ , BSj ^{(2 )} , BSj ⁽³⁾ and BSj ⁽⁴⁾ is not the same. The number of information bits can be as high as 14, for example, the number of separation bits of the separation blocks BSj ⁽¹⁾ , BSj ⁽²⁾ and BSj ⁽³⁾ can be 2, and the separation of the separation block BSj ⁽⁴⁾ can be increased. The number of bits can be six. DC imbalance is determined in the same manner as described for the example of Figure 2A.

The advantages described above can also be obtained in this case. In addition to this advantage, the present example has the advantage that the DC imbalance can be reduced by using a relatively long separation block. More specifically, the residual DC imbalance of a channel bit sequence having an equal number of respective channel blocks, for example 3 bits, is such that each separate block has an average of 3 bits, but 2: 2: 2: 6. It is larger than the residual DC imbalance of the channel bit sequence having bits divided by.

It should be noted that the above-mentioned time series of the roles and related states of the method of this example can be realized by a general sequential logic circuit such as a commercially available microprocessor or a corresponding recording device or peripheral device. FIG. 3 shows a flowchart of such operation. In the following description, the annotations of steps showing the roles and states of the coating method as a time series are used. Column A indicates a reference numeral. Column B shows annotations. Column C shows a description of the corresponding step.

[0040]

[Table 1]

The flowchart described above is applied to the example of FIG. And, taking into account the changes already mentioned,
The corresponding flow chart can also be applied to the example of FIG.

Channels transmitted or recorded
In order to distinguish the information bit and the separation bit when demodulating the bit sequence, (n ₃ + n ₄ ) bits are included in the channel block sequence. Here, n ₃ pieces are synchronization information bits, and n ₄ pieces are synchronization separation bits. The synchronization block is inserted, for example, every predetermined number of information blocks and separation blocks. After this word is detected, it is possible to know in which bit position the information bit is and in which bit position the separating bit is.

Therefore, it is necessary to prevent the synchronization word from being confused with the predetermined bit sequence of the information block and the separation block by some means. to this end,
It is possible to select a special block consisting of synchronization bits, that is, synchronization bits that are not in the information bit series or the separated bit series. Sequences that do not satisfy the d-rule or the k-rule are not very useful in achieving such an objective. This is because the information density and the self-clock characteristic are adversely affected in such a case. However, such choices are restricted to groups of sequences that satisfy the d and k rules.

Therefore, another method is proposed. A synchronization block is configured by including, for example, at least two consecutively generated sequences including s-bit “0” between two consecutive “1” s. Preferably, s is equal to k. FIG. 4 shows the synchronization block SYN. This block is formed by repeating a sequence (10000000000000, 1 followed by 10 zeros) twice consecutively as indicated by SYNP ₁ and SYNP ₂ , respectively. Such a sequence may be a channel bit sequence, ie a sequence with k = 10.

However, in order to prevent this sequence from occurring twice in succession in addition to the synchronization block,
If the "1" bit is part of a separate block,
The sum of the number of separated bits of “0” immediately before the bit of “1” and the number of consecutive information bits of “0” is equal to k,
The first display signal is suppressed when it is also equal to the sum of the number of consecutive "0" information bits immediately after the "1" bit. We have already shown a strategy to prevent the sync block from getting mixed up, but this is the sequence 10000000
That is, 0, that is, 1 followed by 11 0s is repeatedly generated twice.

In addition, the sync block also has a sync separation block. This separation block has exactly the same role as the separation block between information blocks. Therefore, their purpose is to satisfy the d rule and the k rule, and also to satisfy the demand for limiting the DC imbalance. A method similar to the method adopted for preventing pseudo sync patterns from appearing in a channel bit string when sync patterns occur twice consecutively,
Prevent the sync pattern from occurring three times before or after the sync block.

The method described above can of course be applied during modulation and encoding. However, this method becomes much simpler in the opposite case, that is, at the time of demodulation and decoding. The information between the isolated blocks is not important in demodulating the information because the DC imbalance can be limited without affecting the information bit blocks. In addition, it is important not only for the modulator but also for the demodulator that the modulator selects which m-bit-long data bit can correspond to which n-bit-long information bit. That is, making such a selection complicates the configuration of the demodulator. In the magnetic recording system, both the modulator and the demodulator are complicated because both the modulator and the demodulator are built in the device.
In an optical recording system, the user's device need only include a demodulator because the recording medium is read-only. Therefore, in the case of an optical recording system, it is particularly important to simplify the structure of the demodulator as much as possible without complicating the modulator.

5 and 6 show an example of the demodulator. This demodulator has 8 blocks of 14 information bits.
It demodulates a block of data bits. FIG. 5 shows a block diagram of the demodulator, and FIG. 6 schematically shows a part of its circuit. This demodulator has AND gates 17-0 to 17-51. Each of the AND gates 17-0 to 17-51 has one or more input terminals. One of the 14 bits of the information block is supplied to each input terminal. These input terminals are inverting or non-inverting. FIG. 6 shows how this is done in the Ci column. The first column shows the bit position C ₁ of the least significant digit of the 14-bit long information block, and the 14th column shows the bit position C ₁₄ of the least significant digit. The second to thirteenth columns between indicate the remaining digits in relation to the bit positions, respectively. Line l ₀ ~
Each l ₅₁ corresponds to the AND gate number. That is, the line l ₀ corresponds to the input terminal of the AND gate 17-0, and the line l ₁ corresponds to the input terminal of the AND gate 17-1. Others are the same.

If there is a code 1 on the line lj in the i-th column, it is passed through the non-inverting input terminal to the i-th bit position Bi.
Is supplied to the j-th AND gate 17. If there is a code O in the line lj of the i-th column
It receives the ith bit position Ci through the inverting input terminal.
Is supplied to the j-th AND gate 17. As a result, the inverting input terminal of AND gate 17-0 is connected to the _first bit position C ₁ and the non-inverting input terminal is connected to the _fourth bit position C ₄ (line l ₀ ). The non-inverting input terminal of the AND gate 17-1 is connected to the _third bit position C ₃ (line l).
₁ ). The same applies to the other cases.

The demodulator has eight more OR gates 18-
1-18-8. These OR gates 18-1 to 18-1
The input terminal of 18-8 is AND gate 17-0 to 17-
It is connected to 51. Figure 5 shows in the Ai column how this is implemented. Column A ₁ corresponds to the OR gate 18-1. Column A ₂ corresponds to the OR gate 18-2. The same applies to columns A _{3 and} after, and finally A
₈ column corresponds to the OR gate 18-8. Jth A
The letter A in column i indicates that AND gate 17-j is connected to OR gate 18-i.

The circuit configurations of the AND gates 17-50 and 17-51 are changed as follows. and·
The inverting output terminals of the gates 17-50 and 17-51 are connected to the input terminals of the other AND gates 19, respectively.
The output terminal of the OR gate 18-4 is the AND gate 19.
Connected to the other input terminal of.

OR gates 18-1, 18-2, 18-
The output terminals of 3, 18-5 and 18-8 and the output terminal of the AND gate 19 are connected to the output terminal 20-i, respectively. Then, this decoded 8-bit data block is taken out as parallel data from this output terminal.

The demodulator shown in FIG. 5 is a so-called FPL.
A (Field Blogable Logic Array)
You can change it. For example, a signature bipolar FPLA82S100 / 82S101 can be used. The table shown in FIG. 6 is programmable because of this array.

Due to its simplicity, the demodulator shown in FIGS. 5 and 6 is well suited for read-only optical recording systems.

The sync block is detected by the circuit shown in FIG. The transmitted signal or the reproduced recording signal is supplied to the input terminal 21. This signal is in MRZ-M format. This signal is OR gate 22
Is directly supplied to the first input terminal of the OR gate 22 and is also supplied to the second input terminal of the OR gate 22 via the delay element 23. Then, a so-called NRZ-I signal is output from the output terminal of the OR gate 23. The output terminal of the OR gate 23 is connected to the input terminal of the shift register 24.

The shift register 24 has a large number of bits.
It consists of cells. And each of these bit cells is provided with a tap. The number of bit cells is equal to the number of bits that make up the sync block. In the above example, the sequence | 0
It has 23 bit cells in order to be able to record 0000000000000000000000.

Each tap is an input to the AND gate 25
It is connected to the terminal. Input terminal of AND gate 25
Is inverted or non-inverted. Sync series is Andge
When it is supplied to the input of
A signal is output from the output terminal 26 of the port 25. This belief
Signal can be used as a sync pattern detection signal.
It Based on this detection signal, the bit sequence is (n₁+
n₂) It is divided into blocks of bit length. These are divided
Channel blocks stored in other shift registers
Are sequentially shifted. Above n₁Digit bits are parallel
It is read out as data, and as shown in FIG.
It is transferred to the input terminal of the port 17. Lower n ₂Digit bits
Is not used in demodulation.

The coded signal is recorded, for example, on an optical recording medium. This signal has the shape shown in FIG. 1B. This signal is recorded on the recording medium in a spiral locus. This information format is composed of a series of many super blocks as shown in FIG. The super block SBi has a large number of synchronous blocks SYNi (3 in this example).
It consists of (3) channel blocks. The synchronization block SYNi is configured as shown in FIG. Channel blocks BC ₁ , BC ₂ , ... BC ₃₃ are (n ₁ +
n ₂ ) bits. A channel bit of "1" is represented as a transition on the recording medium. For example,
This is as a transition from the state without pits to the state with pits.

The channel bit of "0" is represented as a non-transition state in the recording medium. The spiral information track is subdivided into its constituent cells, or bit cells. On the recording medium, these bit cells form a spatial structure. This structure corresponds to the subdivision of channel bits into bit time intervals.

Regardless of the content of the information bits and the separation bits, numerous details are identified on the recording medium. In this recording medium, the k-rule means that the maximum distance between two adjacent transitions is the length of (k + 1) bit cells. The longest pit (non-pitted portion) therefore consists of (k + 1) bit cells. The d rule implies that the minimum distance between two adjacent transitions is (d + 1) bit cell lengths. In addition, at regular intervals, there is a longest pit after or before the longest pitless part. This form is part of the sync block.

In another example, k = 10, d = 2 and the super block SBi consists of 588 channel bit cells. This super block SBi is 2
It consists of a sync block of 7 (14 + 3) bit cells and 33 channel blocks. Each channel block has (14 + 3) channel bit cells.

It goes without saying that the present invention can be applied to a conversion circuit for converting an analog signal into a digital signal and a reproducing device. That is, the modulator, the transmission path such as the optical recording medium and the demodulator form a part of an integrated system. This system converts, for example, analog information (music, speech) into digital information. This digital information is recorded on the optical recording medium. The information recorded on the recording medium or a copy thereof can be reproduced by a device suitable for reproducing the information recorded on the recording medium.

In this case, this conversion circuit is, specifically,
An analog / digital converter is provided for converting an analog signal (music, speech) to be recorded into a digital signal having a predetermined pattern (source coating). Further, in this conversion circuit, the digital signal is converted into a format for correcting an error generated when reading the digital signal from the recording medium in a device for reproducing the signal. An error correction system suitable for such a purpose has already been proposed by Sony Corporation (Japanese Patent Application No. 55-67608).

The error-corrected digital signal is then supplied to the above-mentioned modulator for conversion into a digital signal suitable for the characteristics of the medium. In addition, a sync pattern is provided and the signal is in the proper frame pattern. The signal thus obtained is used, for example, to obtain a laser control signal (NRZ-M format). With this control signal, a spiral information form as a predetermined pit presence / absence sequence can be applied to the recording medium.

This recording medium or its copy is read by a device for reproducing the information bits obtained from the recording medium. To this end, the device is a modulator,
An analog-to-digital converter for reproducing a copy of the analog signal supplied to the decoder and conversion circuit of the error correction system. The decoder has already been described in detail.

[0066]

According to the present invention, the separation block separates the channel bits of "1" by d or more consecutive "0" channel bits at the connection portion of the adjacent information blocks through the separation block. In addition, a separation block is selected from a plurality of corresponding separation blocks that keep the number of consecutive "0" channel bits within k, and a separation block that reduces the DC imbalance of this information block and separation block that are continuous. Since it is recorded and recorded, there is an advantage that the distance between adjacent transitions can be set within a predetermined range and the DC imbalance can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram for explaining an example of a binary code conversion method.

FIG. 2 is a diagram for explaining another example of the binary code conversion method.

FIG. 3 is a flowchart used to explain FIG.

FIG. 4 is a diagram showing an example of a synchronization block used when demodulating a channel / bit sequence.

FIG. 5 is a diagram showing an example of a decoding device.

6 is a diagram used to explain FIG. 5. FIG.

FIG. 7 is a configuration diagram showing an example of a circuit for detecting a synchronization bit sequence.

FIG. 8 is a diagram showing a frame format example of a binary code conversion method.

[Explanation of symbols]

 BCi channel block BDi data block BIi information block BSi separation block

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kentaro Kodaka 4-14-1, Asahi-cho, Atsugi-shi, Kanagawa Sony Corporation Atsugi Factory

Claims (1)

[Claims] 1. From a data block consisting of m bits,
D (d ≧ 1) or more "0" n _1-channel bit number of successive channel bits "0" while being separated by the channel bit is set within k pieces of channel bits of consecutive "1" (Where n ₁ > m) an information block is formed in a one-to-one correspondence with the data block, and a separation block consisting of n ₂ channel bits is arranged between the information blocks to obtain a binary code. In the recording medium in which the "1" channel bit is recorded as the state transition, the separation block has d or more consecutive "1" channel bits in the connection portion of the adjacent information blocks via the separation block. Among the corresponding separation blocks that are separated by "0" channel bits and the number of consecutive "0" channel bits is within k Is selected from the information blocks and the separation blocks which reduce the DC imbalance of the information blocks and the separation blocks which are continuously formed, the distance between adjacent transitions is set within a predetermined range and the DC imbalance is set. A binary code recording medium having reduced balance.