NZ197683A - Binary data block coding:block conversion according to constraints - Google Patents

Description

t 9768 3 Priority Date{s): [Lj -~7-s>o Complete Specification Filed: Clrss: H®hk*$(w£>. .j. , HQ .Y^.h^mk^kTl Publication Date: P.O. Journal, No: 'i$0"AUGi98i" h-.lk.

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NEW ZEALAND Patents Act, 1953 COMPLETE SPECIFICATION METHOD OF CODING A SEQUENCE OF BLOCKS OF BINARY DATA BITS INTO A SEQUENCE OF BLOCKS OF BINARY CHANNEL BITS, ARRANGEMENT FOR DEMODULATING THE DATA BITS CODED IN ACCORDANCE WITH THE METHOD, AND RECORDING MEDIUM HAVING AN INFORMATION STRUCTURE CONTAINING SEQUENCES OF BLOCKS OF BINARY CHANNEL BITS WE, N.V. PHILIPS' GLOEILAMPENFABRIEKEN, a Limited Liability Company, organized and established under the laws of the Kingdom of The Netherlands and residing at Pieter Zeemanstraat 6, Eindhoven, The Netherlands, do hereby declare the invention, for which. we pray that a Patent may be granted to us , and the method by which it is to be performed, to i>e particularly described in and by the following statement _ 1 - ff- 1 9768 no nnf- _ 1 ft - % 1 <? 19HO "Method of coding a sequence of blocks of "binary data bits into a sequence of blocks of binary channel bits, arrangement for demodulating the data bits coded in accordance with the method, and recording medium having an information structure containing sequences of blocks of binary channel bits." A. Background of the invention.

A( 1) Field of the invention.

The invention relates to a method of coding a sequence of binary data bits into a sequence of binary 5 channel bits, the sequence of data bits being divided into consecutive and sequential blocks, each comprising m data bits, these blocks being coded into sequential blocks of (n^+n^) channel bits (n^+n^ } m), each of these blocks of channel bits comprising a block of n^ information bits and 10 a block of separation bits such that sequential blocks of information bits are separated by each time one block of separation bits, two sequential channel bits of a first type, the type "1" are separated by at least d sequential and consecutive bits of a second type, the type "0", and 15 the number of sequential and consecutive channel bits of the second type being not more than k. The invention further relates to a modulator for carrying out the method of coding a sequence of binary data bits into a sequence of binary channel bits; to a conversion circuit comprising the 20 modulator; to a demodulator for decoding the data bits coded in accordance with the method; to a recording medium having an information structure comprising sequences of channel bit cells and to an arrangement for reproducing information bits derived from a transmission channel, a 25 recording medium in particular.

In digital transmission or magnetic and optical recording/reproduction systems the information to be transmitted or to be recorded is usually in the form of a sequence of symbols. These symbols together form the (often 30 binary) alphabet. For the case a binary alphabet is concerned (in the further course of this description this alphabet is represented by the symbols "1" and "0"), one symbol, for example the "1", can be recorded in accordance 1 9768 BHQ 00 &&7 2 -9 ' 1P 1900 with the NRZ-mark code as a transition between two states of magnetization or focus on the magnetic disc, tape or optical disc. The other symbol, the "O", is recorded by the absence of such a transition.

As a result of certain system requirements, constraints are imposed in practice on the sequences of symbols which may occur. Some systems are required to be self-clocking. This implies that the sequence of symbols to be transmitted or to be recorded should have sufficient 10 transitions to generate from the symbol sequence a clock signal which is required for detection and synchronization. A further requirement may be that certain symbol sequences must not occur in the information signal as these sequences are intended for special purposes, for example as a syn-15 chronizing sequence. Imitation of the synchronizing sequence by the information signal cancels the unambiguity of the synchronizing signal and, consequently, its suitability for that purpose. It may further be required that the transitions do not follow too closely after each other in order 20 to limit the intersymbol interference.

In the case of magnetic or optical recording this requirement may also be related to the information density on the recording medium, as, when at a predetermined minimum distance between two consecutive transitions on the recor- ding medium the minimum time interval (Tm^n) corresponding therewith of the signal to be recorded may be increased, the information density is increased to the same extent. Also the required minimum band width (B . ) is correlated to the ^ v mm' minimum distance T . between transitions (B . = ). mm v mxn 2T . ' When use is made of information channels wKxch do not transmit direct current, as is usually the case with magnetic recording channels, this results in the requirement that the symbol sequences in the information channel comprise.-, the lowest possible (possibly no) direct current component.

A(2) Description of the prior art.

A method of the type described in the opening paragraph is disclosed in reference D(1). The article relates 1 9768 jttq nn 007 3 ^9 1Q 1Q80 to block codes based on d-, k- or (d, k)-constrained q-nary blocks of symbols, which blocks satisfy the following requirements: (a) d-constraint: two "1"-type symbols are separated by a run of at least d consecutive symbols of the "0" type; (b) k-constraint: the maximum length of a run of consecutive symbols of the type "0" is k.

A sequence of, for example, binary data bits is divided into consecutive and sequential blocks, each having 10 m data bits. These blocks of m data bits are coded into blocks of n information bits (n !> m). Since n} m, the number of combinations with n information bits exceeds the number of possible blocks of data bits (2m). If, for example, the d-constraint requirement is imposed on the blocks of infor-15 mation bits to be transmitted or to be recorded, mapping of the 2m blocks of data bits onto likewise 2m blocks of information bits (out of a possible number of 2n blocks) is chosen so that mapping is only carried out on those blocks of information bits which satisfy the requirement 20 imposed.

Table I on page 439 of reference D(1) shows how many different blocks of information bits there are, depending on the length of the block (n) and the requirement imposed on d. So, there are 8 blocks of information bits 25 having a length n=4 at the condition that the minimum distance d=1. Consequently, blocks of data bits having a q length m=3 (2=8 data words) could be represented by blocks of information bits having a length n=4, two consecutive 111 "-type symbols in the blocks of information bits 30 being separated by at least one "0"-type symbol. For this example, coding then is ( v indicates mapping of one block onto the other block and vice versa): 000 * 0000 001 4. * 0001 0 1 0 4 > 0010 011 <£ > 0100 100 < * 0101 101 * > 1000 1 9768 ^PIIQ 0O OOT 4 'J- I J- I 0 110 4 1001 1 1 1 *> i> 1010 When linking up the block of information bits it is in some cases, however, not possible to satisfy the 5 requirement (in the example the d-constraint) without taking further measures. In the said article it is proposed to include separation bits between the blocks of information bits. For the case of d-constraint coding one block of separation bits, comprising d-bits of the "0"-type 10 is sufficient. In the above-mentioned example, where d=1, one separation bit (one zero) is therefore sufficient. Each block of 3 data bits is then encloded by 5 (4+1) channel bits .

This coding method has the disadvantage that the 15 contribution of the low frequencies (including d c) to the frequency spectrum of the stream of channel bits is rather high. A further disadvantage is that the coding converters (modulator, demodulator), the demodulator in particular, are complicated.

As regards the first disadvantage it should be noted that reference D(2) indicates that the direct current unbalance of (d, k)-constrained codes can be limited by interconnecting the blocks of channel bits by means of a so-called inverting or a non-inverting link. Acting thus, 25 the sign of the contribution of the instantaneous block of channel bits to the direct current unbalance is chosen so that the direct current unbalance of the preceding blocks of channel bits is reduced. However, here a (d, k)-con-strained code is concerned whose blocks of information bits 30 can be linked-up without coming into conflict with the (d, k)-constraint, so that the addition of separation bits for reasons of (d, k)-constraining is not necessary. (b) Summary of the invention.

It is an object of the invention to provide a method of the type described in the opening paragraph for the coding of a sequence of binary data bits into a sequence of binary channel bits which improves the low-frequency spectrum properties of the signal to be derived from the |976£3 channel bits and which method enables the use of a simple demodulator.

According to a broad aspect of the invention there is provided a method of coding a sequence of binary data bits into a sequence of binary channel bits., this sequence of data bits being divided into consecutive and sequential blocks, each comprising m data bits, these blocks being coded into sequential blocks of (n^ + n^) channel bits (n^ + n2)>m, each of these blocks of channel bits comprising a block of n^ information bits and a block of n2 separation bits such that sequential blocks of information bits are separated by each time one block of separation bits, two sequential channel bits of a first type, the type "1", are separated by at least d sequential and consecutive bits of a second type, the type "0", and the number of sequential and consecutive channel bits of the second type being not more than k, characterized in that the method comprises the following steps: -1- converting blocks, containing m-bits of data bits into block containing n^ bits of information bits; -2- generating a set of possible sequences of channel bits, each sequence comprising at least one block of information bits and one block of separation bits and these possible sequences each comprising the blocks of information bits supplemented by one of the possible bit combinations of the blocks of separation bits; -3- determining the direct current unbalance of each of the possible sequences of channel bits determined in the preceding step; -4- determining for each of the possible sequences of channel bits the sum of the number of separation bits and the number of consecutive information bits of the "0" type which immediately precede a bit of the "1" type and the sum of the number following after a bit of the "l"-type, this "l"-type bit forming part of one of the block of separation bits, and the sum of the number of separation bits and the number of consecutive information bits of the "O" type immediately preceding and following after that block of separation bits^ -5- generating a first indication signal for those channel bit sequences the values of the sums determined in the preceding step of which are higher than d and not more than equal to k. -6- selecting from the sequences of channel bits which resulted in the first 9 JUNl985°jJ indication signal that sequence of channel bits which minimizes the direct current imbalance.

Embodiments of the invention and their advantages will now be further described with reference to the drawings. In these drawings: Figure 1 shows some bit sequences for illustrating an embodiment of the coding format according to the — 1 9768 -J?HQ 80 -OO? 6 9-1 P-1 9ftQ- invention; Figure 2 shows some further embodiments of the format of the channel coding to be used in the reduction of the direct current unbalance according to the invention; 5 Figure 3 is a flow chart of an embodiment of the method according to the invention; Figure 4 illustrates a block of synchronizing bits for use in the method according to the invention; Figure 5 shows an embodiment of a demodulator 10 in accordance with the invention for decoding the <iaca bits which were coded in accordance with the method; Figure 6 shows an embodiment of the means for detecting a sequence of synchronizing bite according to the invention; Figure 7 shows an embodiment of a frame - format for use in the method according to the invention.

Corresponding elements in the Figures have been given the same reference symbols.

D. References. (1) Tang, D.T., Bahl, L.R., "Block codes for a class of constrained noiseless channels". Information and Control, Vol. 17, no. 5, Dec. 1970, pp.436-461. (2) Patel, A.M., "Charge-constrained byte-oriented (0,3) code", IBM Technical Disclosure Bulletin, Vol. 19, Nr. 25 7. Dec, 1976, pp.2715-2717.

E. Description of the embodiments.

Figure 1 shows some bit sequences to illustrate the method of coding a run of binary data bits (Figure 1a) into a run of binary channel bits (Figure 1b). The run of 30 data bits is divided into consecutive and sequential blocks BD. Each block of data bits comprises m databits. By way of example, the choice m = 8 will be used in the further course of this description and in the Figures. The same applies, however, for any other value of m. A block of m 35 data bits BD_^ generally comprises one of the 2m possible bit sequences.

Such bit sequences are not so suitable for direct optical or magnetical recording and that for several reasons. # 191683 «f-HQ 80 -&oy~ 7 2-1 Vhen namely two data symbols of the "1" type, which are for example recorded on the recording medium as a transition from one magnetizing direction to the other or as a transition to a pit, immediately follow after each another, 5 then these transitions must not be too close to each other in view of their mutual interaction. This limits the information density. At the same time the minimum band width B . which is required to transmit or record the bit stream mm ^ is increased when the minimum distance T . between conse- mm cutive transitions" (B- . = 1/(2T .. ) is small. Another min min- requirement which is often imposed on data transmission and optical or magnetical recording systems is that the bit sequences must have sufficient transitions to recover from the transmitted signal a clock signal with which syn-15 chronization can be carried out. A block having m zeroes, preceded in worst case situations by a block ending in a number of zeroes and followed by a block beginning with a number of zeroes, would endanger the clock extraction.

Information channels which do not transmit direct 20 current, such as magnetic recording channels must further satisfy the requirement that the data stream to be recorded comprises a direct current component which is as small as possible. With optical recording it is desirable that the low-frequency portion of the data spectrum is suppressed 25 to the best possible extent, this in view of the servo controls. In addition, the demodulation is simplified when the direct current component is relatively small.

For the above and other reasons a so-called channel coding is performed on the data bits before they 30 are transmitted via the channel or before they are recorded. In the case of block coding (reference D(l))the blocks of data bits which each contain m bits are coded as blocks of information bits which each comprise information bits. Figure 1 shows how the block of data bits is converted into a block of information bits BI.^. By way of example, the choice n^ = 14 will be used in the further course of this description and in the Figures. As n is greater than m, not all the combinations which can be formed IS V <■> 197683 # F4IQ- OQ &&?- 8 with bits are utilized: those combinations which do not fit in well with the channel to be utilized are not used. So, in the example given only 256 words need to be selected from the more than 16.000 possible channel words for the 5 required one-to-one mapping of data words onto channel words. Consequently, some requirements may be imposed on the channel words. One requirement is that between two consecutive information bits of a first type, the "1" type, at least d sequential and consecutivecinformation bits of W one type, the "0" type, are situated within the same block of n^ information bits. Table I on page 439 of reference D(l) shows how many such binary words there are, depending on the value of d. It appears from the table that for n^ = 14 there are 277 words with at least two (d=2) bits of the "0" type between consecutive bits (of the "1" type). When coding blocks of eight data bits, of which there g may be 2 = 256 combinations, as blocks of l4 channel bits the requirement d=2 can therefore be amply satisfied.

Catenation of the block of information bits BI. 1 is, however, not possible without further measures when the same requirements of d-constrained is not only imposed within a block of bits but also extends over the boundary between two consecutive blocks. To this end, reference D(1) proposes (page 451) to include one or more separation bits between the blocks of channel bits. It can be easily seen that when a number of "0"-type separation bits at least equal to d is included, that the d—constraint is satisfied. Figure 1 shows that a block of channel bits BC^ consist of the block of information bits BS. and a block of 1 separation bits BS^. The block of separation bits comprises n^ bits so that the block of channel bits comprises n^ + bits. By way of example the choice n^ = 3 vill be used in the further course of the description and in the Figures, unless indicated differently.

In order to make the clock generation as reliable as possible a further requirement may be that the maximum ?ij%T^ ;*'number of "O" type bits which may occur uninterruptedly **"* between two consecutive "T" type bits within one block of {■it ^ 197633 , niQ oo 007 9 9. u 1900 information bits is limited to a predetermined value k. In the example where m=8 and n ^ = 1 4 it is possible to eliminate from the 277 words which satisfy d=2, those words, for example, which have a very high value for k. It appears 8 that k may be limited to 10. Consequently, a set of 2 (in general 2m) blocks of data bits of 8 bits each (in general m) is mapped onto a set of also 2^ (in general 2m) blocks of information bits, which information bits have been selected from 2^ (in general 2n1) possible blocks of 10 information bits, which is partly the result of the fact that the following requirements have been imposed: d=2 and k=10 (in general d, k-constrained). It is still at one's option which one of the blocks of data bits is to be associated with one of the blocks of information bits. In the 15 above-mentioned reference (Dl) a number translation from data bits to information bits is unambiguously determined in a mathematically closed form. Although this translation can, in principle, be used, preference is given to a different association as will be further explained herein-20 after.

Catenation of the furthermore k-constrained channel words BI^ is only possible, which also applies for the d-constrained blocks, when separation blocks have been arranged between the blocks of information bits In principle the same separation blocks of n^ bits each can be used for this purpose as the requirements d-constrained and k-constrained are not each other's opposite, but are rather complementary. When, consequently, the sum of the number of bit values of the "0" type preceding a given 30 separation block exceeds the number of values following after that separation block and the n^ bits of the separation block itself exceed the value k., then at least one of the bit values of the "O" type of the separation block should be replaced by a bit value of the "1" type in order 35 to split the sequence of zeroes into sequences which are each not more than k bits long.

In addition to their function of ensuring that the requirements of (d, k)-contraint are satisfied, the 1 9768 RttQ- 80 0#7 10 9-1 a 198Q separation blocks can be dimensioned so that they can also be utilized for minimizing the direct current unbalance.

This is cased on the recognition of the fact that for some catenations of blocks of information bits a predetermined 5 format of the block of separation bits is indeed prescribed but that in a large number of cases either no requirements or only limited requirements are imposed on the format of the block of separation bits. The degree of freedom created thus is used for minimizing the current unbalance. 10 The coming into existence and the growth of the direct current unbalance can be explained as follows. The block of information bits BI^ as shorn in Figure 1b is recorded on the recording medium, for example in the form of a KRZ-mark format. With, this format a "1" is marked by a 15 transition at the beginning of the relevant bit cell and becomes a "0" when no transition is recorded. The bit sequence shown in BI^ then assumes a shape which is denoted by WF, in which shape this bit sequence is recorded on the recording medium. This sequence has a direct current un-20 balance as for the present sequence the positive level has a length which is longer than the negative level. A measure which is often used for the direct current unbalance is the digital sum value, abbreviated to d.s.v. Assuming the levels of the wave form to be WF + 1 and -1, respectively, the 25 d.s.v. is then equal to the running integral of the wave form WF ans if +6T in the example shorn in Figure 16, T being the length of one bit interval. When such sequences are repeated, the direct current unbalance will grow. Generally, this direct current unbalance results in a base 30 line movement and reduces the effective signal-to-noise ratio and, consequently, the reliability of the detection of the recorded signals.

The block of separation bits BS_^ is used as follows to limit the direct current unbalance. At a given instant a block of data bits BD^ is supplied. This block of data bits BD. is converted into a block of information x bits BI, for example by means of a Table stored in a store. Thereafter, a set of possible blocks of channel bits, con taining (n^ + n^) bits is generated. All these blocks comprise the same block of information bits (bit cells 1 to l4, inclusive, Figure 1b) supplemented by the possible bit combinations of the n^ separation bits (bit cells 15, 16 and 17, Figure 1b). Consequently, in the example shown in XI ^ Figure 1b a set consisting of 2 =8 possible blocks of channel bits is produced. Thereafter the following parameters are determined from each of the possible blocks of channel bits, in principle in an arbitrary sequence: r.a) it is determined" for the , relevant possible block of channel bits, in view of the preceding block of channel bits, whether the requirement of d-constrained and the requirement of k-constrained do not conflict with the format of the present block of separation bits; d) determination of the d.s.v. for the relevant, possible block of channel bits.

A first indication signal is generated for those possible blocks of channel bits which do not conflict with the d—constraint and k—constraint requirements. The choice of the coding parameters guarantees that such an indication signal is generated for at least one of the possible blocks of information bits. Finally, from the possible blocks of channel bits for which a first indication signal has been generated that block of channel bits is, for example, selected which has in an absolute sense the lowest d.s.v. However, a still better method is the accumulation of the d.s.v. of the preceding blocks of channel bits and to select from the blocks of channel bits which are eligible for the next-coming transmission that block which will cause the absolute value of the accumulated d.s.v. to decrease. The word selected thus is transmitted or recorded.

An advantage of this method is that the separation bits which are already necessary for other purposes can now also be utilized in a simple manner for the limitation of the direct current unbalance. An additional advantage is that the intervention in the signal to be transmitted is limited to the blocks of separation bits and does not extend to the blocks of information bits (ignoring the # 197683 12 IO-t-2 ■ 1 ft&Q- polarity of the wave form to be transmitted or recorded).

The demodulation of the read, recorded signal then only relates to the information bits. The separation bits may be left out of consideration.

Figure 2 shows some further embodiments of the method. Figure 2a shows schematically the sequences of blocks of channel bits ..., BC. ., BC., BC. „, ..., these ' i-1' i' i+1' blocks comprising a predetermined number of (n^ + n0) bits.

Each block of channel bits comprises blocks of information bits consisting of bits, and block's of separation bits. . .

BS. „, BS. „, BS. , BS. „, . . . , each consi sting of n„ bits. i-1' 1-1' i' 1+1' ' 2 In this embodiment the direct current unbalance is determined across several blocks, for example as shown in Figure 2a across two blocks of channel bits BC^ and BC. The direct current unbalance is determined in a i + l similar manner as described for the embodiment of Figure 1, on the proviso that the possible formats of superblocks are generated for each superblock SBC_^, that is to say the blocks of information bits for block BC. and blocks BC. „ l 1 + 1 are supplemented by all the possible combinations which can be formed with the separation bits of blocks BS^ and block BS. „ . That combination which minimizes the direct i + 1 current unbalance is thereafter selected from this set.

This method has the advantage that the remaining direct current unbalance has a more uniform character as it is considered more than one block of channel bits in advance which intervention is optimum.

An advantageous variant of this method has the distinctive feature that the superblock SBC^ (Figure 2a) is shifted one block of channel bits only after the direct current unbalance has been minimized. This means that block BC_^ (in Figure 2a), which is part of the superblock SBC_^, is processed and that the subsequent superblock SBC. . (not shown) contains the blocks BC. „ and BC. i+1 x ' i+1 i+2 (not shown) for which the above-described direct current unbalance minimizing operation is performed. So the Jjlock BC. . is part of both the superblock SBC. and the T.' , i + 1 i ^ • subsequent block SBC^+^. It is then perfectly possible f'HQ 8u W 197683 that the (provisional) choice for the separation bits in block BS. „, made in superblock SBC. differs from the x+1' * 1 ultimate choice made in superblock SBC. _ . As each block l+l is assessed several times (twice in the present example) the direct current unbalance and consequently the noise contribution is further reduced.

Figure 2b shows a further embodiment in which the direct current unbalance is determined for several blocks simultaneously (SBCj), for example as shown in Figure (i) (2) (3 > 2b for four blocks of channel bits BCj ; BCj , BIC.j' ' (4) and BCj^ '. Each of these blocks of channel bits comprises a predetermined number of n^ information bits. However, the number of separation bits comprised in the blocks of separation bits BSj^^, BSj^^, BSj^~^ and BSj^^ is not the 15 same for each block of channel bits. The number of information bits may, for example, amount to 14 and the number of separation bits for the blocks BSj^^, BSj^^ and BSj^"^ 19Y6ST3 i^fiQ udee-7 (b may be 2 for each block and 6 for block BSjv . Determining the direct current unbalance is carried out in a similar manner as described for the embodiment of Figure 2a. in the foregoing and which also apply here, this method has the advantage that the availability of a relatively long block of separation bits increases the possibilities to reducing the direct current unbalance. More specifically, the remaining direcjt current unbalance of sequence -of channel bits in which each block of channel bits comprises an equal number of, for example, 3 hits is larger than the remaining direct current unbalance of a sequence of channel bits the blocks of separation bits of which comprise an average of 3 bits, divided however into 2-2-2-6 bits. quences of functions and associated states of the method can be realized by means of universal sequential logic circuits such as commercially available microprocessors with associated stores and peripheral equipment. Figure 3 shows a flow chart of such an implementation. The following • explonatory texts are associated with the legends of the geometrical figures which illustrate, time-sequentially, the functions and states of the coding method. Column A shows the reference symbol, B the legend and column C the explanatory text associated with the relevant geometrical Figure.

In addition to the advantages already mentioned It should be noted that the described time se- A B C 1 DSC :=0; acc . i: =0; the digital sum value (d.s.v) of the preceding blocks of channel bits is given the value zero at the start of the method. The first data word BD is given the number i=0. Proceed the geometrical figure 2; 2 The block of data bits of m bits of the number i is selected from a store. Proceed to geometrical PJ1Q 00 -] 5- 197683 -^9— 1 gL. 1 900- 3 BI. (BD.) 1 v 1' 4 j : =0 5 j : =3 + 1 6 j .< Q? 25 7 BC"? : =BI. +BS^ 1 1 8 DSV^=? 9 > ? max .15 JU^ 1982 -w! figure 3; The block of data bi ts having number _i (BD^) is converted into a block of information bits consisting of n^ bits (BI^) by means of a Table stored in the store; proceed to geometrical Figure k; A parameter j_ is initiated at a value O; the parameter j_ is the number' of one of the q blocks of channel bits consisting of n^+n^ bits which is possibly eligible for transmission or recording; proceed to geometrical Figure 5» The parameter is increased by 1; proceed to geometrical Figure 6.

When the relevant parameters have been determined of all the c[ possible blocks of channel bits, operations are continued by the operation indicated by geometrical Figure 13. In geometrical Figure 6 this is indicated by the link N.

When j $ Q> operations are continued by the operation indicated by geometrical Figure 7; The j possible block of channel bits BC^ is formed by supplementing the block of information bits BI_^ by the j ^ combination of the block of separation bits BS*^ ; proceed to geometrical Figure 8; i/3"i The. d.s.v. of the j possible block of channel bits is determined proceed to geometrical Figure 9, It is checked whether the jpossible block of channel bits on catenation with the preceding blocks 1 9768 3^1(4 6u "| u | IJSw 1 1 12 <d^^? min DSV ^ ^ i=max DSV^^s=DSV^ J ^ + DSV acc acc 13 min^/DSV:=DSV^e^ . th of channel bits BC. „ satisfies i-1 the k-constraint requirement. If this requirement is satisfied, operations are continued by the operation indicated in geometrical Figure 10 (link V). If this require' ment is not satisfied, then the following step is the operation indicated by geometrical* Figure 11 (link Y).

It is checked whether the j possible block of channel bits on catenation with the preceding block of channel bits BC. „ satisfies i-1 the d-constraint requirement. If this requirement is satisfied the following step is the operation indicated by geometrical Figure 12 (link N). When this requirement is not satisfied, then the operation is continued by the step indicated by geometrical Figure 11 (link y); The d.s.v. of the j^ block of channel bits is given such a high value (max) that this block can definitely not be selected; proceed to geometrical Figure 12; The d.s.v. of the block of channel bits (dsv^*^ is added to the accumulated dsv (DSV ) of s acc' the preceding blocks of channel bits to obtain a new accumulated value of the d.s.v. (DSV acc proceed to geometrical Figure 5j The minimum value of the dsv of the cj_ possible blocks of channel bits is determined. This appears to be the d.s.v. of the first 19 7 6 PIIQ GO 007 -17- -9 <12 1980 block of channel bits (proceed to geometrical Figure 14); 14 BC"!" The first block of channel bits is i ■(1) selected from the c|_ possible blocks proceed to geometrical figure 15; DSV :=DSVv ' The accumulated value of the d.s.v. acc (DSV ) is made equal to the acc accumulated value of the d.s.v. of the selected first block of infor-10 mation bits; proceed to geometri cal Figure 16; 16 i:=i+1 The number of the blocks of data and information bits is increased by one. Proceed to geometrical Figure 2; the cycle is now repeated for the next, the (i+l)S^ block of data bi ts.

The flow chart shown above is applicable to the embodiment shown in Figure 1. For the embodiments of Figure 2 the corresponding flow charts hold, talcing the modifications already described into consideration.

In order to enable a distinction when demodulating the transmitted or recorded stream of channel bits between the information bits and the separation bits (n^+n^) namely n^ synchronizing information bits and n^ synchronizing separation bits, are included in the stream of channel bits blocks. A block of synchronizing bits is, for example, inserted after each predetermined number of blocks of information and separation bits. After detection of this word it can then be unambiguously determined in which bit position information bits and in which bit positions separation bits are present. Measures should therefore be taken to prevent the synchronization word from being imitated by certain bit sequences in the information and separation blocks. To this end a unique block of synchronizing bits, that is to say synchronizing bits which are not present in information and separation bit sequences, can be chosen. Sequences which do not satisfy the require- 197683 Pttt; 80 0^-7 - ] 8- 9-1 a^-1980 ment of being d-constrained or k-constrained are not so attractive for this purpose as the information density or the self-clocking properties are then affected negatively. However, the choice is very limited within the group of block of synchronizing bits includes, for example, at least two times in succession and consecutively a sequence which comprise-s S bits of the. "0"-type between two sequen-10 tial bits of the "1"-type. Preferably, S is equal to k.

Figure h shows a block of synchronizing bits SYN. The block comprises two times in succession and consecutively a sequence (10000000000, 1 followed by 10 zeroes) denoted by SYNP^ and SYNP^ respectively. This sequence may also be 15 present in the channel bit stream, namely for sequences where k=10. However, to prevent the sequence from occurring two times in succession and consecutively outside the block of synchronizing bits, the first indication signal is suppressed when the sum of the number of separation bits 20 and the number of sequential and consecutive information bits of the "0" type immediately preceeding a bit of the "1" type, the latter forming part of the block of separation bits, is equal to k and also equal to the sum of the number of consecutive and sequential information bits of the "0" 25 type which immediately follows after the said bit of the "1" type of the block of separation bits. The other, already indicated way to prevent imitation would be to use two times in succession the sequence 100000000000 thus 1, followed by 11 zeroes. also comprises a block of synchronization separation bits. The function of the block of separation bits is exactly the same as the function described in the foregoing of the block of separation bits between the blocks of information sequences which satisfy the (d, k)-constraint requirements.

A different method is therefore proposed. The In addition, the block of synchronization bits C£|V^ ' 1 976 EIIQ 00 OQf -19- >9-1 a- 1 9&e- ch.ann.el bits as it occurs two times in succession and consecutively, these same measures also prevent this pattern from occurring three times before or after the block of synchronizing bits.

The above-described method, which may also be referred to as modulating or encoding, is of a considerably simpler character in the opposite direction, that is to say during demodulation or decoding. Limitation of the direct current unbalance is effected without affecting the 10 blocks of information bits, so that the information in the separation blocks is irrelevant for demodulating the information. In addition, the choice taken at the modulator end which m bit long block of data bits is associated with which n^ long block of information bit is of importance 15 not only for the modulator but also for the demodulator. Namely, the complexity of the demodulator depends on this choice. In magnetic recording systems the complexity of modulator and demodulator are of equal importance as they are in general both present in the apparatus. In systems 20 for optical recording, the recording medium is of the "readonly" type so that the consumer equipment need only comprise a demodulator. So, in this latter case it is particularly important to reduce the complexity of the demodulator as much as possible, even at the cost of the complexity of the 25 modulator .

Figure 5 shows an embodiment of a demodulator which demodulates the blocks of 8 data bits from blocks of 1k information bits. Figure 5a shows the block schematic circuit diagram of the demodulator and Figure 5b shows schemtically a portion of the circuitry. The demodulator comprises AND-gates 17-0 to 17-51, inclusive, each having one or more inputs. One of the 1h bits of the blocks of information bits is applied to each input, which are of the inverting or non-inverting type. Figure 5b shows in 3® column how this is carried out. Column 1 represents the least significant bit position C^ of the 14-bit information block, column ~\h the most significant bit position C^ and the intermediate columns 2 to 13, inclusive, re- 1 976 PTTQ nn aay -20- -9 1 J 19^ present the remaining, corresponding with the bit position, significant bit positions. The lines O to 51, inclusive, relate to the number of the AMD-gate, that is to say line 0 relates to the input format of AMD-gate 17-0, line 1 relates to the input format of AJSTD-gate 17-1 » etc. A symbol 1 in the i^*1 column of line j_ signified that the t li j AND-gate 17 is supplied via a non-inverting input with the content of the bit position B^ . A symbol 0 in the 1 ^ column of line signifies that the AND-gate 17 is supplied via an inverting input with the content of the "fc h i bit position (C.). Consequently, (line o), an inverting "fell input of AMD-gate 17-0 is connected to the i bit position (C^), and a non-inverting input is connected to the 4^*1 bit position (CJ; (line 1) a non-inverting input of AMD- 3T d, gate 17-0 is connected to the 3 bit position, 0^); etc.

The demodulator further comprises 8 OR-gates 18-1 to 18-8, inclusive, the inputs of which are connected to the outputs of the AMD-gates 17-0 to 17-51, inclusive.

Figure 5b shows in column A^ how this is realized. Column A^ relates to AMD-gate 18 — 1, column A^ relates to AND-gate 18-2, ... and column Ao relates to AND-gate 18-8. A til. ^ til latter A in the i column of the j line indicates that the output of AMD-gate 17 — j is connected to the input of OR-gate 18-i.

For the AMD-gates 17-50 and 17r51 the circuit is modified as follows. An inverting output of both AMD-gate 17-50 and 17-51 are each connected to an input of a further AND-gate 19* An output of OR-circuit 18-4 is connected to a further input of AMD-gate 19.

Each output of the OR-gates 18 — 1, 18-2, 18-3 and 18-5 to 18-8, inclusive, and an output of AND-gate 19 are connected to an output 20-i. The decoded block of 8 data bits is consequently available in parallel form at this output.

The demodulator shown in Figure 5a may, alternatively, be in the form of a so-called FPLA (field programmable logic array), for example the Signetics bipolar FPLA type 82S100/82S101. The Table shown in Figure 5 is the 1 9768 PIIQ 80 OQff -21- D 12 1980. programmable table for this array.

The demodulator shown in Figure 5 is, because of its simplicity, emminently suitably for optical recording systems of the "read-only" type.

The block of synchronizing bits can be detected with the means shown in Figure 6. The transmitted or read recorded signal is applied to an input terminal 21. The signal is in the MRZ-M(ark) format. This signal is applied directly to a first input of an OR-gate 22 and to a second 10 input of OR-gate 23 via a delay element 23. A so-called NRZ-I signal is then available at the output of OR-gate 22, which is connected to the input of a shift register 2k. The shift register comprises a number of sections, each having a tap, which number is equal to the numberof 15 bits comprised in the block of synchronizing bits. In the example used in the foregoing, the shift register must have 23 sections, namely in order to be able to contain the sequence 10000000000100000000001. Each tap is connected to an input of an AND-gate 25, which input is either an in-20 verting or a non-inverting input. When the synchronization sequence is present at the inputs of AND-gate 25, a signal will then be generated at an output 26 of this AND-gate which may be used as an indication signal for the detection of the synchronizing pattern. By means of this signal the 25 bit stream is divided in two blocks of (n^+n^) bits each. These blocks of channel bits are shifted, one after the other, in a further shift register. The most sifnigicant n^ bits are read in parallel and applied to the inputs of the AND-gates 17, as shown in Figure 5a. The least signi-30 ficant bits are irrelevant for the demodulation.

The coded signal is, for example, recorded on an optical recording medium. The signal has a form denoted by WF in Figure 1b. The signal is applied on the recording medium in a helical information structure. The information structure comprises a sequence of a number of superblocks, for example of the type shown in Figure 7« A superblock SB^ comprises a block of synchronizing bits SYN^, this block being implemented as shown in Figure h, and a number -PIIQ SO 007 197683 9 - 1J I '>&&- (33 in the embodiment) of blocks of channel bits, each having (n1+n2) bits BC 1 , BC2, ... BC^. A channel bit of the "1" type is represented by a transition in the recording medium, for example a transition from no-pit to pit; a chan-5 nel bit of the "0" type is represented on the recording medium by the absence of a transition. The helical information track is subdivided into elementary cells, the bit cells. On the recording medium these bit cells form a spatial structure, which corresponds to a subdivision in .j the time (period time, of, one. bi.t) .of. the stream of channel bi ts .

Independent of the content of the information and separation bits, a number of details can be distinguished at the recording medium. For the medium the k-constraint implies that the maximum distance between two consecutive transitions is k+1 bit cells. The longest pit (or no-pit) has therefore a length of (k+1) bit cells. The d-constaint implies that the minimum distance between the two consecutive transitions is d+1. The shortest bit (or no-pit) 20 has therefore a length of (d+l) bit cells. Furthermore, at regular distances, there is a pit of the maximum length followed by (or preceded by) a no-pit of the maximum length. This structure is part of the block of the synchronization bits.

In a preferred embodiment k=10, d=2 and a super-block SB_^ comprises 588 channel bit cells. The super block SB_^ comprises a block of synchronization bits of 27 bit cells and 33 blocks of channel bit cells, each having 17 (l4+3) channel bit cells.

A modulator, a transmission channel, for example an optical recording medium, and a demodulator may together be part of a system, for example a system for the conversion of analog information (music, speech) into digital information, which information is recorded on an optical recording medium. The information recorded on the record- ing medium (or a copy thereof) can be reproduced by means of an arrangement which is suitable for the reproduction „„ of- the type of information which has been recorded on the l* 15 JUNI982 1 9768 eiiq so ooff. -23- recording medium.

The conversion circuit comprises in particular an analog-to-digital converter for converting the analog signal (music, speech) to be recorded into a digital signal of a predetermined format (source coding). In addition, the conversion circuit may include a portion of an error- correction system. In the conversion circuit the digital signal is converted into a format by means of which the errors which particularly occur during reading of the re- cording medium can be corrected in the arrangement for the reproduction of the signals. An error correction system which is suitable for this purpose is disclosed in the Patent Applications which have been filed by Messrs. Sony s "fc Corporation in Japan under number 1^539 on 21 May 1980 "fctl and 5 June 1980, respectively.

The digital, error-protected signal is thereafter applied to the modulator described in the foregoing (channel coding) for conversion into a digital signal which is adapted to the channel properties. In addition, the syn-20 chronization pattern is supplied and the signal is brought to a suitable frame format. The signal thus obtained is used to generate a control signal, for example for a laser (NRZ-mark format) by means of which a helical information structure is applied on the recording medium in the 25 form of a sequence of pits/no pits of a predetermined length.

The recording medium or a copy thereof can be read by means of an arrangement for the reproduction of the information bit derived from the recording medium. To this 30 end, the arrangement comprises a modulator, which has already been described in detail, the decoder portion of the error correction system and a digital/analog converter for reconstituting a replica of the analog signal which is applied to the conversion circuit.

Claims (18)

WHj- 80 g&7 -24- 197683 «y- lii-1 yfi0 WHAT WE CLAIM ZS«

1. A method of coding a sequence of binary data bits into a sequence of binary channel bits, this sequence of data bits being divided into consecutive and sequential blocks, each comprising m data bits, these blocks being coded into sequential blocks of (n^ +' n-2~) channel Lbits (n„ + n_) S m, each of these blocks of channel bits com-s 1 d' ' '-t prising a block of n^ information bits and a block of n^ separation bits such that sequential blocks of information bits are separated by each time one block of separation bits, two sequential channel bits of a first type, the type "1", are separated by at least d sequential and consecutive bits of a second type, the type "0", and the number of sequential and consecutive channel bits of the second type being not more than k, characterized in that the method comprises the following steps: -1- converting blocks, containing m-bits of data bits into block containing n^ bits of information bits; -2- generating a set of possible sequences of channel bits, each sequence comprising at least one block of information bits and one block of separation bits and these possible sequences each comprising the blocks of information bits supplemented by one of the possible bit combinations of the blocks of separation bits; -3- determining the direct current unbalance of each of the possible sequences of channel bits determined in the preceding step; -k- determining for each of the possible sequences of channel bits the sum of the number of separation bits and the number of consecutive and coquontial information bits of the "O" type which immediately precede a bit of the "1" type and the sum of the number following r * I "~+ype. after a bit of the "V'-type, this • bit forming part of of one of the block of separation bits, and the sum of t97683 f J'lm 8U UB7 -25- P II! I 1900 the number of separation bits and the number of consecutive and ooquontial information bits of the "0" type immediately preceding and following after that block of separation bits. 5 -5- generating a first indication signal for thosechannel bit sequences the values of the sums determined in the preceding step of which are higher than d and not more than equal to k. -6- selecting from the sequences of channel bits which 10 resulted in the first indication:signal that sequence of channel bits which minimizes the direct current unbalance .

2. A method as claimed in Claim 1, characterized in that the fifth step comprises the following sub-step: a. 15 -5 - suppressing the first indication signal for that sequence of channel bits for which the sum, determined in the fourth step, of the number of separation bits and the number of consecutive and sequential information bits of the "0"-type immediately preceding a bit 20 of the "1" type of the block of separation bits is equal to the sum, which was also determined in the fourth step, of the number of separation bits and the number of consecutive and sequential information bits of the "0" type which immediately follows after a bit 25 of the "1" type of the block of separation bits, this sum being equal to s; and in that the method further comprises the following steps: -7- dividing a sequence of blocks of (n^ + n^) channel bits 30 into consecutive and sequential frames, each having p blocks; -8- inserting a block of synchronization channel bits between every two sequential frames, this block of synchronization channel bits comprising a predetermined 35 block of n^ synchronization infonnation bits, this block comprising at least two times in succession and conse-//^ cutively a sequence which comprises, between two sequen- Lc tial bits of the "1" type, s bits of the "0" type and 1 19JUM985~| - 26 - 197683 furthermore oanprising a block of synchronization separation bits, this block of separation bits being determined by carrying out the steps -2- to -6-, inclusive/ with respect to the block of synchronization channel bits.

3. A method as claimed in claim 2, characterized in that s=k.

4. A method as claimed in any one of the preceding claims, characterized in that the sixth step comprises the further sub-steps: - determining the accumulated direct current unbalance of the preceding blocks of channel bits; - determining the absolute value of the sum of the accumulated direct current imbalance and the direct current unbalance of each of the sequences of channel bits which resulted in the first indication signal.

5. A method as claimed in any one of the preceding claims, diaracterized in that the sequence of channel bits comprises four blocks of information bits each having n^ bits and four blocks of separation bits, in that three blocks of separation bits have a first length i^' and one block a length n^ and that r^^n-^'.

6. A method as claimed in claim 5, characterized in that n-^ = 14, r^" = 6 and m = 8.

7. A method as claimed in any one of claims 1 to 4, characterized in that the sequence of channel bits ccrprises one block of information bits having n^ bits and a block of separation bits having bits.

8. A method as claimed in claim 7, characterized in that n^ = 14, ri2 = 3 and m = 8.

9. A method as claimed in any one of claims 1 to 4, characterized in that the sequence of channel bits is formed by at least tews blocks of channel bits and that consecutive sequences of channel bits jointly relate to at least one block of channel bits.

10. A demodulator for decoding the data bits coded in accordance with the method claimed in any one of the pre- 197683 -27- <o-1g-1i)00 ceding Claims 2 to 9 inolucivo, characterized in that the demodulator comprises: - means for detecting the synchronizing pattern; - means for dividing the run of channel bits into blocks 5 each having (n^ + n^) channel bits; - means for separating the blocks having n^ information bits from the blocks having n^ separation bits; - means for converting a block of information bits into the block of m ,.da.ta..Jb.its . '3

11. A demodulator as claime.d _ in Claim _ 10 , characterized in that the conversion means comprise AND-gates, each AND-gate having inputs to which there are applied in parallel the information bits coming from at least one predetermined bit position of the block of 15 information bits in that the means further comprise OR gates having inputs which are connected in a predetermined manrff to the outputs of the AND-gates and that these OR-gates further have outputs for outputting the' decoded AND-gate bits in parallel. 20

12. A recording medium having an information struc ture comprising sequences of channel bit cells, these channel bit cells each comprising a binary data bit which is represented by a level transition or no level transition at the beginning of the bit cell, characterized in that 25 the maximum distance between two consecutive transitions is equal to the length of (k+l) bit cells, in that the minimum distance between two consecutive transitions is equal to the length of (d+l) bit cells, that sequences of not more than two times the maximum distance of (k+l) bit cells are present, and in that the said sequences are part of a synchronizing sequence.

, 13. A recording medium as claimed in Claim 12, EB 1985£| charact erized in that k=10, d=2; in that the recording // medium comprises between two consecutive sequences which 35 are at the maximum distance from each other a frame having 561 channel bit cells, this frame comprising 33 blocks each having 17 channel bit cells and in that the synchronizing sequence comprises 27 channel bit cells. - 28 - 137S83

14. A modulator for carrying out the method of coding a sequence of binary data bits into a sequence of binary channel bits, as claimed in any one of the claims 1 to 9.

15. A conversion circuit comprising a modulator as claimed in claim 14.

16. A method of coding a sequence of binary data bits substantially as herein described with reference to the accompanying drawings.

17. A demodulator for decoding coded date bits substantially as herein described with rofarnncnoe to the accompanying drawings.

18. A recording medium substantially as herein described with reference to the accompanying drawings. N V PHILIPS' GDCEHLAMPHSTFABRIEKEN By Their Attorneys HENRY HUGHES LIMITED