JPS5837828A - Audio signal reproducer - Google Patents

Abstract

PURPOSE:To ensure a reproduction with high quality, by producing clock and synchronizing signals after extracting the recording signal of a digital audio disk and then producing the reading signal with both clock and synchronizing signals to reproduce an audio signal. CONSTITUTION:A pickup 1 is provided with a digital audio disk (DAD) player with its number of revolutions controlled accurately. This pickup 1 radiates a laser beam to the surface of the DAD and receives the reflected light to convert it into an electric signal. A clock oscillator 2 produces a signal which receives the control of phase by the signal picked up from the player 1. A synchronizing signal producing part 3 produces a synchronizing signal in each prescribed period form the outputs of the player 1 and the oscillator 2. A reading signal producing part 4 produces a reading signal synchronizing with the information part from the outputs of the oscillator 2 and the part 3. An information signal reading part 5 reads only the signal at an area where an audio signal is converted into a digital signal among the signals of the player 1 and from the signal of the player 1 and the reading signal of the part 4. The readout 5 signal undergoes a D/A conversion 6. Thus a reproduction is possible with high quality.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital audio disc (hereinafter referred to as DA) in which audio signals are converted into digital signals and recorded.
Conventionally, in order to record audio signals on a recording disc, the depth of the O-groove of the audio disc was adjusted in an analog manner in response to changes in the audio signal. Please change it. However, there is a limit to the sound quality that can be obtained using Jin's method, and as a method to solve this problem, a DAD has been proposed that converts the audio signal into a digital signal and then records it on a recording disc according to predetermined rules. An object of the present invention is to provide an audio signal external generation device that reads and reproduces audio signals from good signals recorded on a DAD.

In order to achieve such an objective, the device of the present invention
A clock signal and a synchronization signal are generated by the signal picked up from the AD record player, a readout signal is generated by the clock signal and the synchronization signal, and a readout signal is generated by the readout signal of the signal picked up from the DAD. It plays audio signals from inside.

There is a recording disc DAD recorded by a digital method, and this is recorded according to the format shown in Figure #I1 (a). In the same figure, synchronization part 4, for example, %0
It consists of a total of 22 bits, including a partial program 1 consisting of 11 consecutive bits of 1, followed by 11 consecutive bits of 111. Also, the recording section
It consists of a fixed number of consecutive bits of 01 or %11. This recording section 8 includes a 5-bit first redundant section B1 in which 11 and %01 bits are alternately present, and an information section B in which an analog audio signal is converted into a 14-bit digital signal. , 3-bit redundant part B of #E2 in which bits %II and %O1 exist alternately, and one frame is constructed in the following order.

First, the synchronization section A is followed by the first redundancy section B1.

This is followed by a recording section B in which the information section B and the second redundant fits Bs are alternately inserted 33 times later, and the synchronization section and the recording section 1 together constitute one frame C. A plurality of 7-ray 50 KFi recordings are recorded consecutively on the disc.

In this case, recording section B is defined as not having a combination of consecutive 11-bit %0#t or %11, no matter what the information content is. According to this definition, the synchronization signal placed at the beginning of one frame can be distinguished from the recording part B, and a signal (hereinafter referred to as the synchronization signal) that rises at the boundary between the synchronization part A and the recording part B as shown in Fig. 1 (←) ) can occur.

Furthermore, based on this synchronization signal, a signal (hereinafter referred to as a readout signal) that rises at the trailing edge of each information signal is generated as shown in FIG. It is possible to read out only the information fRS B s from the received signal and reproduce the audio (M number).

FIG. 2 is a block diagram showing one embodiment of the apparatus according to the present invention. The laser beam is emitted onto the surface of the DAD, and the reflected light of this laser beam is received by a phototransistor and converted into an electrical signal as shown in FIG.

A clock oscillator 2 generates a signal whose phase is controlled by the signal picked up from the DAD player 1. Reference numeral 3 denotes a synchronizing signal generating section, which takes the signal picked up from the DAD player 1, generates it from the Q-tsuku generator 2, and generates it from the 4-tsuku signal as shown in Fig. WJ1 (b).
One synchronizing signal is generated at a fixed period as shown by K. Reference numeral 4 denotes a read signal generating section which generates a read bias signal synchronized with the information section 1 of (a) as shown in FIG. Reference numeral 5 denotes an information signal reading section which converts the audio signal of the signal picked up from the DAD player 1 into a digital signal from the signal picked up from the DAD player 1 and the continuous signal generated by the continuous signal generation section 4. Only the converted *S signal, that is, the information part B3 of FIG. 1G) is continuously output. Reference numeral 6 denotes a digital-to-analog converter 6 (hereinafter referred to as a D/MU converter) which converts the good signal expressed in digital format and read out by the TV station 5 into an analog format. Note that the information signal reading section 5 reads the serial signal at 14
It consists of a serial input/parallel output type shift register 5 for converting into a bit parallel signal and a two-way circuit 5 for holding this output signal.

The operation of the device according to the present invention configured as described above is as follows. The DAD player 1 is shown in Figure 1G mentioned above.
) is picked up and supplied to the clock oscillator 2, which generates a clock signal whose phase is controlled by the signal picked up from the DAD player 1.

The signal picked up from the DAD router 1 and the clock signal are supplied to a synchronization signal generating section 3, which generates a synchronization signal of the type ζ puffer as shown in FIG. 1(b). The clock signal and the synchronization signal are then supplied to the successive signal generating section 4, which generates a successive timing signal as shown in FIG.

On the other hand, the signal picked up from the DAD player 1 is supplied to the serial-in parallel output shift register 5t IIC of the information signal reading section S, and this shift register 51
has a 14-bit output signal end, and the shift register 51 takes in the input signal and sends it out from the output end 7, and each time the input (i!) is taken in, the signal at the output end is transferred to the adjacent is shifted to the output end.

Therefore, all 14 bits constituting the clear information sBl are stored in the shift register 51 at the trailing edge of the clear information part B3 in FIG.
The output signal of the output register 51 is output from the latch circuit 5. IC is supplied. At this time, latch circuit 5! Since the output signal shown in FIG. 1 is supplied from the successive signal generating section 4 to
! From among the signals held and output by the DAD player shown in Figure 111 (0), the first signal Pl:
Only B* appears one after another. The information section B read out by the information signal calling section 5 is converted from a digital format to an analog format by a D/A converter 6, so that the DADK
It is possible to play back an audio signal from a recorded signal.

In this case, the synchronization signal generating section 3 is configured as shown in the conceptual diagram shown in the correlation chart tiJIJ of the output signals of the third prisoner, for example. JI4 diagram (A) is a signal picked up from the DAD player 1, and the time width of this signal is supplied to the input terminal T shown in I3 diagram. %JI4
Figure ←) an) It shows the width of the figure and the corresponding number of bits. The fourth rKJf role is a 1ml pulse signal that is processed by the differentiating circuit 8 from the input signal supplied to the input terminal 1 in FIG. 3 and output. Figure 4 (E) shows the count value output from the first kakunta 9, and Figure #I4 (G) shows the count value output from the second counter 1o of the Ml counter 9. #Il parallel register 110 holds the output from the 4th
The illustrated example shows the second @[.

ml, the second parallel shift register 11, 120 latch tie pulses are each seen from the differentiator circuit 8.13. ! l, second parallel shift register 11.1
Each count value of 2 is 1e 2f: 7-da 14
, 15. A matching circuit 16 is provided so that an output signal appears at an output terminal 18 when the count values decoded by the first and second decoders 14 and 15 match the number "11".

Note that this is a 17Vi inverter, and a clock signal is supplied from the second clock oscillator 2 to the input terminal T&.

Further, the successive signal generating section 4 is configured as shown in Figure 5, and the correlation between the input and output signals of each part in Figure 5 is as shown in the time chart shown in Figure 6.
In FIG. 5, one input terminal of the AND circuit 19 is supplied with the clock signal shown in FIG. 6 0) from the clock oscillator 2 of FIG. 2 via the input terminal 20. On the other hand, jl
! The set signal input terminal S of the storage circuit 21 is connected to the synchronizing signal generator 4 of FIG.
The 0th line to which the synchronization signal indicated by the arrow is supplied is the 6th W7A.
This is the waveform shown by (P)K, which sets the first memory circuit 21, and its output signal is as shown in FIG. Since the AND circuit 18 is supplied to the JIK6 figure f
9 is supplied to the input terminal IN of the M1 frequency divider 230.The M1 frequency divider 1!23 is composed of, for example, a 5-ary counter, and when the pulse signal is divided by 5 times, the output tJi2 shown in #I6 is shown in the figure. Since the set signal input terminal 8 of the memory circuit 24 is supplied, the second memory circuit 24 is set, and the output signal shown in FIG. 6) is supplied to one input terminal of the AND circuit 2S. The other input jllK of this AND circuit 25 is as shown in FIG.
Since the clock signal shown in Fig. 6 (g) is leaked from the circuit and the output signal shown in Fig. 6 (g) is supplied to the set signal input terminal 8 of @3 memory circuit 2T, the memory circuit 27i is set,
The output signal is supplied to one input terminal of AND-w12. Since the AND circuit 2S supplies the signal shown in FIG. 6(a) to the other input terminal Kr of the AND gate 280, the AND circuit 28 outputs the output signal shown in FIG.
The input terminal INK of the frequency divider 2s is supplied.

The frequency divider 2 consists of a ternary counter, and #
! Since the output signal shown in Fig. 6 Q)) is supplied to the reset input terminal 1 of the @2 frequency divider 26 and the reset input terminal R1 of the third memory @*2T, #! 2 minute X machine 26 and 3rd
Memory circuit 27 is reset.

Then, when the reset signal shown in FIG. 96 (S) disappears, the second frequency division (to) 26 is again divided into the signal f shown in FIG. (The output signal shown in h is supplied to the third storage circuit 2T. As a result, the jI3 frequency divider 29 again divides the signal shown in M6 in FIG. #I2 frequency division port 26 and third storage circuit 21 are reset.

Therefore, one pulse is generated for every 17 bits, which is the total number of bits of the information section Bs and the second redundant section Bs of the second division w4 device 26 lines in Figure 1 (as shown). The fourth frequency divider 30, which is supplied to the frequency divider sO, is composed of, for example, a 33-decimal counter, and outputs the output signal shown in FIG.
4 and 27. Since the output signal is supplied to the reset input terminals of the frequency dividers 23, 26, and 2I, the respective circuits are reset.As a result, the output signal of the W, I storage circuit 21 is not supplied to the AND circuit 1B. In the circuit of FIG. 5, an output signal of 33IIA is obtained from the output terminal 31 during the period T as shown in FIG.

Then, as shown by the arrow E in Figure 1II1, when the synchronizing signal is supplied to the input terminal 22 again, the readout signal [33@] is obtained again from the output terminal 31. As a result, a successive signal is obtained from the output terminal 31, which is generated in synchronization with the period of the information section B, as shown in FIG. M1 (c).

As explained above, the audio signal reproduction company according to the present invention generates a clock signal and a synchronization signal using a signal picked up from a DAD record player, and generates a read signal using the clock signal and synchronization signal. This read signal is used to reproduce the audio signal from the signal picked up from r) AD.
0 capable of playing high quality audio signals

[Brief explanation of drawings]

Fig. 1 is a diagram showing the No. 46 format of the signal picked up from the DAD and the timing of the synchronization signal and readout signal generated based on this signal, and Fig. #I2 shows an embodiment of the audio signal generation device according to the present invention. Figure 3 is a block diagram showing the implementation of the synchronization signal detection section, Figure 4 is a diagram showing the correlation of No. 0m in the synchronization signal detection section, Figure 5 is an implementation of the readout signal generation section. A block diagram showing an example, and FIG. 6 is a time chart of signals of the read signal generation section.
... Synchronization signal generation section, 4 ... Read signal generation section, 5
...Breaking signal continuous output section, 6...Digital-to-analog converter (D/A converter) port

Claims (1)

[Claims] A pickup means for extracting the recorded signal from the disk on which the audio signal converted to the digital signal is recorded at a predetermined location as a broadcasting part, and a pickup means whose phase is controlled by the recorded signal and generates a tsuku signal. a clock oscillator, a synchronization signal generating section that generates a synchronization signal at predetermined intervals from the recording signal and the psock signal; a read signal generating section that generates a signal; an information signal reading section that decodes the recorded signal according to a predetermined rule using the successive signals; and a digital signal that converts the signal decoded by the information signal reading section from a digital signal to an analog signal.・An audio signal playback device consisting of an analog converter.