JPS576423A - Demodulating circuit of mfm modulation signal - Google Patents

Abstract

PURPOSE:To prevent propagation of a demodulation error of a data, by utilizing a PLL circuit again in accordance with a demodulation synchronizing signal, and demodulating a clock pulse, in a data and a synchronizing signal which have been demodulated by use of a PLL circuit. CONSTITUTION:An MFM signal which has been reproduced is inputted to an edge detecting pulse generating circuit 1, and an edge detecting pulse (c) synhronizing with an edge of the MFM signal is outputted from the circuit 1. This pulse (c) is inputted to a PLL circuit 2, a 101 pattern detecting circuit 5, and an FF circuit 4, and a demodulation synchronizing signal (j) is obtained from a synchronizing detecting circuit 6 of a demodulating circuit 7. The signal (j) is inputted to a PLL circuit 8, and a clock pulse (k) synchronizing with the signal (j) is obtained from the circuit 8. As far as this pulse (k) is concerned, a pulse (k) never goes out of order even if reproduction of a data falls into disorder during that time, if only synchronizing signal is reproduced exactly. Accordingly, when the pulse (k) is utilized, it is possible to obtain a demodulated data whose error is fewer than that of an FF circuit 12.